-------------------------------------------------------------------------------- -- File name : nlb6253.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V2.0 rev3 22 MAR 96 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.2 R. Steele 96 OCT 21 Updated timing generics -- V2.3 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.4 R. Munden 98 SEP 22 Changed delay mode to transport -- V2.5 R. Munden 07 JUN 18 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: NLB -- Technology: ECL -- Part: NLB6253 -- -- Description: Quad 2-bit Synchronous Demultiplexer with Reset -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY nlb6253 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_R : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_QA : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_COUT : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D_CLK : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_R_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_R_posedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : Boolean := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor D : IN std_ulogic := '0'; CLK : IN std_ulogic := '0'; R : IN std_ulogic := '0'; COUT : OUT std_ulogic := 'U'; COUTNeg : OUT std_ulogic := 'U'; QA : OUT std_ulogic := 'U'; QANeg : OUT std_ulogic := 'U'; QB : OUT std_ulogic := 'U'; QBNeg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_level0 OF nlb6253 : ENTITY IS TRUE; END nlb6253; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF nlb6253 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL R_ipd : std_ulogic := 'X'; SIGNAL QAint : std_ulogic := 'X'; SIGNAL QBint : std_ulogic := 'X'; SIGNAL COUTint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D_ipd, D, tipd_D); w_2: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_3: VitalWireDelay (R_ipd, R, tipd_R); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => QA, a => QAint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => QANeg, a => QAint, ResultMap => ('U','X','Z','1')); a_3: VitalBUF (q => QB, a => QBint, ResultMap => ('U','X','Z','1')); a_4: VitalINV (q => QBNeg, a => QBint, ResultMap => ('U','X','Z','1')); a_5: VitalBUF (q => COUT, a => COUTint, ResultMap => ('U','X','Z','1')); a_6: VitalINV (q => COUTNeg, a => COUTint, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehavior : PROCESS (CLK_ipd, D_ipd, R_ipd) -- Timing Check Variables VARIABLE Tviol_DA_CLK : X01 := '0'; VARIABLE TD_DA_CLK : VitalTimingDataType; VARIABLE Tviol_DB_CLK : X01 := '0'; VARIABLE TD_DB_CLK : VitalTimingDataType; VARIABLE Rviol_R_CLK : X01 := '0'; VARIABLE TD_R_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_R : X01 := '0'; VARIABLE PD_R : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE PrevDataA : std_logic_vector(0 to 2); VARIABLE PrevDataB : std_logic_vector(0 to 2); VARIABLE PrevDataC : std_logic_vector(0 to 2); VARIABLE PrevDataQA : std_logic_vector(0 to 2); VARIABLE Dint : std_ulogic; VARIABLE QA_zd : std_ulogic; VARIABLE QB_zd : std_ulogic; VARIABLE CLK_div_2 : std_ulogic; VARIABLE BLANK : std_ulogic := '0'; -- Output Glitch Detection Variables VARIABLE QA_GlitchData : VitalGlitchDataType; VARIABLE QB_GlitchData : VitalGlitchDataType; VARIABLE COUT_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D_ipd, TestSignalName => "D_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D_CLK, SetupLow => tsetup_D_CLK, HoldHigh => thold_D_CLK, HoldLow => thold_D_CLK, -- CLK_div_2 is '1', but will change to '0' CheckEnabled => (R_ipd = '0' and CLK_div_2 = '1'), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6253", TimingData => TD_DA_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DA_CLK ); VitalSetupHoldCheck ( TestSignal => D_ipd, TestSignalName => "D_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D_CLK, SetupLow => tsetup_D_CLK, HoldHigh => thold_D_CLK, HoldLow => thold_D_CLK, -- CLK_div_2 is '0', but will change to '1' CheckEnabled => (R_ipd = '0' and CLK_div_2 = '0'), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6253", TimingData => TD_DB_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DB_CLK ); VitalRecoveryRemovalCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", Recovery => trecovery_R_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/nlb6253", TimingData => TD_R_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_R_CLK ); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, HeaderMsg => InstancePath & "/nlb6253", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", PulseWidthHigh => tpw_R_posedge, HeaderMsg => InstancePath & "/nlb6253", CheckEnabled => TRUE, PeriodData => PD_R, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_R ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Rviol_R_CLK or Pviol_CLK or Pviol_R; VitalStateTable ( StateTable => TFFR_tab, DataIn => (Violation, CLK_ipd, R_ipd), Result => CLK_div_2, PreviousDataIn => PrevDataC ); -- Output f/f: order important VitalStateTable ( StateTable => DFFN_tab, DataIn => (BLANK, CLK_div_2, Dint), Result => QA_zd, PreviousDataIn => PrevDataQA ); -- Input f/fs VitalStateTable ( StateTable => DFF_tab, DataIn => (Tviol_DA_CLK, CLK_div_2, D_ipd), Result => Dint, PreviousDataIn => PrevDataA ); VitalStateTable ( StateTable => DFFN_tab, DataIn => (Tviol_DB_CLK, CLK_div_2, D_ipd), Result => QB_zd, PreviousDataIn => PrevDataB ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => QAint, OutSignalName => "QAint", OutTemp => QA_zd, Mode => VitalTransport, GlitchData => QA_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_QA, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => QBint, OutSignalName => "QBint", OutTemp => QB_zd, Mode => VitalTransport, GlitchData => QB_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_QA, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => COUTint, OutSignalName => "COUTint", OutTemp => CLK_div_2, Mode => VitalTransport, GlitchData => COUT_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_COUT, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;