-------------------------------------------------------------------------------- -- File name : nlb6241.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2008 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V2.0 rev3 22 MAR 96 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.2 R. Steele 96 OCT 21 Updated timing generics -- V2.3 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, -- and updated TimingChecks & PathDelays -- V2.4 R. Munden 98 SEP 21 Changed delay mode to transport -- V2.5 R. Munden 06 NOV 10 Made resultmap locally static -- V2.6 R. Munden 08 MAY 07 Corrected VITAL timing generics -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: NLB -- Technology: ECL -- Part: NLB6241 -- -- Description: 4-bit ripple counter with enable -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY nlb6241 IS GENERIC ( -- tipd delays: interconnect path delays tipd_ENeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_R : VitalDelayType01 := VitalZeroDelay01; tipd_S0 : VitalDelayType01 := VitalZeroDelay01; tipd_S1 : VitalDelayType01 := VitalZeroDelay01; tipd_S2 : VitalDelayType01 := VitalZeroDelay01; tipd_S3 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q1 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q2 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q3 : VitalDelayType01 := ECLUnitDelay01; tpd_R_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_S0_Q0 : VitalDelayType01 := ECLUnitDelay01; -- trecovery values: release times trecovery_S0_CLK : VitalDelayType := ECLUnitDelay; trecovery_S1_CLK : VitalDelayType := ECLUnitDelay; trecovery_S2_CLK : VitalDelayType := ECLUnitDelay; trecovery_S3_CLK : VitalDelayType := ECLUnitDelay; trecovery_R_CLK : VitalDelayType := ECLUnitDelay; trecovery_ENeg_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_R_posedge : VitalDelayType := ECLUnitDelay; tpw_S0_posedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- ticd values: delayed clock times for negative timing constraints ticd_CLK : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : Boolean := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor, 1 pull-up ENeg : IN std_ulogic := '1'; CLK : IN std_ulogic := '0'; CLKNeg : IN std_ulogic := '0'; R : IN std_ulogic := '0'; S0 : IN std_ulogic := '0'; S1 : IN std_ulogic := '0'; S2 : IN std_ulogic := '0'; S3 : IN std_ulogic := '0'; Q0 : OUT std_ulogic := 'U'; Q0Neg : OUT std_ulogic := 'U'; Q1 : OUT std_ulogic := 'U'; Q1Neg : OUT std_ulogic := 'U'; Q2 : OUT std_ulogic := 'U'; Q2Neg : OUT std_ulogic := 'U'; Q3 : OUT std_ulogic := 'U'; Q3Neg : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF nlb6241 : ENTITY IS TRUE; END nlb6241; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF nlb6241 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL ENeg_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL CLK_dly : std_ulogic := 'X'; SIGNAL R_ipd : std_ulogic := 'X'; SIGNAL S0_ipd : std_ulogic := 'X'; SIGNAL S1_ipd : std_ulogic := 'X'; SIGNAL S2_ipd : std_ulogic := 'X'; SIGNAL S3_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; SIGNAL Q3int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (ENeg_ipd, ENeg, tipd_ENeg); w_2: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_3: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_4: VitalWireDelay (R_ipd, R, tipd_R); w_5: VitalWireDelay (S0_ipd, S0, tipd_S0); w_6: VitalWireDelay (S1_ipd, S1, tipd_S1); w_7: VitalWireDelay (S2_ipd, S2, tipd_S2); w_8: VitalWireDelay (S3_ipd, S3, tipd_S3); END BLOCK; ---------------------------------------------------------------------------- -- Negative Timing Constraint Delays ---------------------------------------------------------------------------- SignalDelay : BLOCK BEGIN s_1: VitalSignalDelay (CLK_dly, CLK_ipd, ticd_CLK); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q0, a => Q0int, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => Q0Neg, a => Q0int, ResultMap => ('U','X','Z','1')); a_3: VitalBUF (q => Q1, a => Q1int, ResultMap => ('U','X','Z','1')); a_4: VitalINV (q => Q1Neg, a => Q1int, ResultMap => ('U','X','Z','1')); a_5: VitalBUF (q => Q2, a => Q2int, ResultMap => ('U','X','Z','1')); a_6: VitalINV (q => Q2Neg, a => Q2int, ResultMap => ('U','X','Z','1')); a_7: VitalBUF (q => Q3, a => Q3int, ResultMap => ('U','X','Z','1')); a_8: VitalINV (q => Q3Neg, a => Q3int, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- ECL Clock with Enable Process and NTC Delay included ---------------------------------------------------------------------------- ECLclock : PROCESS (CLK_ipd, CLKNeg_ipd, ENeg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLKint_pre : std_ulogic; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab(CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode ), Result => CLKint_pre, PreviousDataIn => PrevData ); CLKint_zd := VitalOR2 (a => CLKint_pre, b => ENeg_ipd); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, Mode => VitalTransport, GlitchData => CLK_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => ticd_CLK, PathCondition => TRUE), 1 => (InputChangeTime => CLKNeg_ipd'LAST_EVENT, PathDelay => ticd_CLK, PathCondition => TRUE) ) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehavior : PROCESS (CLKint, R_ipd, S0_ipd, S1_ipd, S2_ipd, S3_ipd) -- Timing Check Variables VARIABLE Rviol_R_CLK : X01 := '0'; VARIABLE TD_R_CLK : VitalTimingDataType; VARIABLE Rviol_S0_CLK : X01 := '0'; VARIABLE TD_S0_CLK : VitalTimingDataType; VARIABLE Rviol_S1_CLK : X01 := '0'; VARIABLE TD_S1_CLK : VitalTimingDataType; VARIABLE Rviol_S2_CLK : X01 := '0'; VARIABLE TD_S2_CLK : VitalTimingDataType; VARIABLE Rviol_S3_CLK : X01 := '0'; VARIABLE TD_S3_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_R : X01 := '0'; VARIABLE PD_R : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_S0 : X01 := '0'; VARIABLE PD_S0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_S1 : X01 := '0'; VARIABLE PD_S1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_S2 : X01 := '0'; VARIABLE PD_S2 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_S3 : X01 := '0'; VARIABLE PD_S3 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q0_zd : std_ulogic; VARIABLE Q1_zd : std_ulogic; VARIABLE Q2_zd : std_ulogic; VARIABLE Q3_zd : std_ulogic; VARIABLE PrevData0 : std_logic_vector(0 to 3); VARIABLE PrevData1 : std_logic_vector(0 to 3); VARIABLE PrevData2 : std_logic_vector(0 to 3); VARIABLE PrevData3 : std_logic_vector(0 to 3); -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; VARIABLE Q3_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalRecoveryRemovalCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, Recovery => trecovery_R_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/nlb6241", TimingData => TD_R_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_R_CLK ); VitalRecoveryRemovalCheck ( TestSignal => S0_ipd, TestSignalName => "S0_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, Recovery => trecovery_S0_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/nlb6241", TimingData => TD_S0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_S0_CLK ); VitalRecoveryRemovalCheck ( TestSignal => S1_ipd, TestSignalName => "S1_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, Recovery => trecovery_S1_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/nlb6241", TimingData => TD_S1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_S1_CLK ); VitalRecoveryRemovalCheck ( TestSignal => S2_ipd, TestSignalName => "S2_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, Recovery => trecovery_S2_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/nlb6241", TimingData => TD_S2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_S2_CLK ); VitalRecoveryRemovalCheck ( TestSignal => S3_ipd, TestSignalName => "S3_ipd", RefSignal => CLKint, RefSignalName => "CLKint", RefDelay => ticd_CLK, Recovery => trecovery_S3_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/nlb6241", TimingData => TD_S3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_S3_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLK_posedge, HeaderMsg => InstancePath & "/nlb6241", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", PulseWidthHigh => tpw_R_posedge, HeaderMsg => InstancePath & "/nlb6241", CheckEnabled => TRUE, PeriodData => PD_R, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_R ); VitalPeriodPulseCheck ( TestSignal => S0_ipd, TestSignalName => "S0_ipd", PulseWidthHigh => tpw_S0_posedge, HeaderMsg => InstancePath & "/nlb6241", CheckEnabled => TRUE, PeriodData => PD_S0, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_S0 ); VitalPeriodPulseCheck ( TestSignal => S1_ipd, TestSignalName => "S1_ipd", PulseWidthHigh => tpw_S0_posedge, HeaderMsg => InstancePath & "/nlb6241", CheckEnabled => TRUE, PeriodData => PD_S1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_S1 ); VitalPeriodPulseCheck ( TestSignal => S2_ipd, TestSignalName => "S2_ipd", PulseWidthHigh => tpw_S0_posedge, HeaderMsg => InstancePath & "/nlb6241", CheckEnabled => TRUE, PeriodData => PD_S2, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_S2 ); VitalPeriodPulseCheck ( TestSignal => S3_ipd, TestSignalName => "S3_ipd", PulseWidthHigh => tpw_S0_posedge, HeaderMsg => InstancePath & "/nlb6241", CheckEnabled => TRUE, PeriodData => PD_S3, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_S3 ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Rviol_R_CLK OR Rviol_S0_CLK OR Rviol_S1_CLK OR Rviol_S2_CLK OR Rviol_S3_CLK OR Pviol_CLK OR Pviol_R OR Pviol_S0 OR Pviol_S1 OR Pviol_S2 OR Pviol_S3; VitalStateTable ( StateTable => TFFSR_tab, DataIn => (Violation, CLKint, S0_ipd, R_ipd), Result => Q0_zd, PreviousDataIn => PrevData0 ); VitalStateTable ( StateTable => TFFSR_tab, DataIn => (Violation, Q0_zd, S1_ipd, R_ipd), Result => Q1_zd, PreviousDataIn => PrevData1 ); VitalStateTable ( StateTable => TFFSR_tab, DataIn => (Violation, Q1_zd, S2_ipd, R_ipd), Result => Q2_zd, PreviousDataIn => PrevData2 ); VitalStateTable ( StateTable => TFFSR_tab, DataIn => (Violation, Q2_zd, S3_ipd, R_ipd), Result => Q3_zd, PreviousDataIn => PrevData3 ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0int", OutTemp => Q0_zd, Mode => VitalTransport, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => S0_ipd'LAST_EVENT, PathDelay => tpd_S0_Q0, PathCondition => TRUE), 2 => (InputChangeTime => R_ipd'LAST_EVENT, PathDelay => tpd_R_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1int", OutTemp => Q1_zd, Mode => VitalTransport, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q1, PathCondition => TRUE), 1 => (InputChangeTime => S1_ipd'LAST_EVENT, PathDelay => tpd_S0_Q0, PathCondition => TRUE), 2 => (InputChangeTime => R_ipd'LAST_EVENT, PathDelay => tpd_R_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2int", OutTemp => Q2_zd, Mode => VitalTransport, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q2, PathCondition => TRUE), 1 => (InputChangeTime => S2_ipd'LAST_EVENT, PathDelay => tpd_S0_Q0, PathCondition => TRUE), 2 => (InputChangeTime => R_ipd'LAST_EVENT, PathDelay => tpd_R_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q3int, OutSignalName => "Q3int", OutTemp => Q3_zd, Mode => VitalTransport, GlitchData => Q3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q3, PathCondition => TRUE), 1 => (InputChangeTime => S3_ipd'LAST_EVENT, PathDelay => tpd_S0_Q0, PathCondition => TRUE), 2 => (InputChangeTime => R_ipd'LAST_EVENT, PathDelay => tpd_R_Q0, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;