-------------------------------------------------------------------------------- -- File name : nlb6221.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997-2006 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V2.0 rev3 22 MAR 96 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.2 R. Steele 96 OCT 21 Updated timing generics -- V2.3 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.4 R. Steele 97 JUN 30 Changed setup CheckEnable to true -- V2.5 R. Munden 98 SEP 21 Changed delay mode to transport -- V2.6 R. Munden 02 APR 03 Corrected Dummy VPD -- V2.7 R. Munden 06 Oct 28 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: NLB -- Technology: ECL -- Part: NLB6221 -- -- Description: Quad D-Flip/flop with Master Reset -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY nlb6221 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_DNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLKA : VitalDelayType01 := VitalZeroDelay01; tipd_CLKB : VitalDelayType01 := VitalZeroDelay01; tipd_MR : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLKA_Q : VitalDelayType01 := ECLUnitDelay01; tpd_MR_Q : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D_CLKA : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D_CLKA : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_MR_CLKA : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_MR_posedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period tperiod_CLKA_posedge: VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor, 1 pull-up D : IN std_ulogic := '0'; DNeg : IN std_ulogic := '1'; CLKA : IN std_ulogic := '0'; CLKB : IN std_ulogic := '0'; MR : IN std_ulogic := '0'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF nlb6221 : ENTITY IS TRUE; END nlb6221; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF nlb6221 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL DNeg_ipd : std_ulogic := 'X'; SIGNAL CLKA_ipd : std_ulogic := 'X'; SIGNAL CLKB_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Dint : std_ulogic := 'X'; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D_ipd, D, tipd_D); w_2: VitalWireDelay (DNeg_ipd, DNeg, tipd_DNeg); w_3: VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA); w_4: VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB); w_5: VitalWireDelay (MR_ipd, MR, tipd_MR); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalOR2 (q => CLKint, a => CLKB_ipd, b => CLKA_ipd); a_2: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_3: VitalINV (q => QNeg, a => Qint, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- D inputs Process ---------------------------------------------------------------------------- Dinputs : PROCESS (D_ipd, DNeg_ipd) -- Functionality Results Variables VARIABLE Dint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Dint_zd := ECL_s_or_d_inputs_tab (D_ipd, DNeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => Dint, OutSignalName => "Dint", OutTemp => Dint_zd, GlitchData => D_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehavior : PROCESS (Dint, CLKint, MR_ipd) -- Timing Check Variables VARIABLE Tviol_D_CLK : X01 := '0'; VARIABLE TD_D_CLK : VitalTimingDataType; VARIABLE Rviol_MR_CLK : X01 := '0'; VARIABLE TD_MR_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MR : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 3); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => Dint, TestSignalName => "Dint", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D_CLKA, SetupLow => tsetup_D_CLKA, HoldHigh => thold_D_CLKA, HoldLow => thold_D_CLKA, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/nlb6221", TimingData => TD_D_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_CLK ); VitalRecoveryRemovalCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", RefSignal => CLKint, RefSignalName => "CLKint", Recovery => trecovery_MR_CLKA, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/nlb6221", TimingData => TD_MR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MR_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLKA_posedge, HeaderMsg => InstancePath & "/nlb6221", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, HeaderMsg => InstancePath & "/nlb6221", CheckEnabled => TRUE, PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_CLK OR Rviol_MR_CLK OR Pviol_CLK OR Pviol_MR; VitalStateTable ( StateTable => DFFR_tab, DataIn => (Violation, CLKint, Dint, MR_ipd), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, Mode => VitalTransport, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLKA_Q, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;