-------------------------------------------------------------------------------- -- File name : nlb6210.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997-2003 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V2.0 rev3 23 MAR 96 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Steele 96 OCT 21 Updated timing generics -- V2.2 R. Munden 98 SEP 09 changed style from concurrent proceedures -- to process, from inertial delay to -- transport and added period checks -- V2.3 R. Munden 03 FEB 22 Fixed GlitchData variables -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: NLB -- Technology: ECL -- Part: NLB6210 -- -- Description: 4 fan-out buffer with enable and complementary outputs -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY nlb6210 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_ENeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_D_QA : VitalDelayType01 := ECLUnitDelay01; tpd_ENeg_QA : VitalDelayType01 := ECLUnitDelay01; -- tperiod_min: minimum clock period = 1/max freq tperiod_D_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; InstancePath : STRING := DefaultECLInstancePath; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor D : IN std_logic := '0'; ENeg : IN std_logic := '0'; QA : OUT std_logic := 'U'; QB : OUT std_logic := 'U'; QC : OUT std_logic := 'U'; QD : OUT std_logic := 'U'; QANeg : OUT std_logic := 'U'; QBNeg : OUT std_logic := 'U'; QCNeg : OUT std_logic := 'U'; QDNeg : OUT std_logic := 'U' ); ATTRIBUTE VITAL_level0 OF nlb6210 : ENTITY IS TRUE; END nlb6210; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF nlb6210 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL ENeg_ipd : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D_ipd, D, tipd_D); w_2: VitalWireDelay (ENeg_ipd, ENeg, tipd_ENeg); END BLOCK; ---------------------------------------------------------------------------- -- VITALBehavior Process ---------------------------------------------------------------------------- VITALBehavior1 : PROCESS(D_ipd, ENeg_ipd) -- Functionality Results Variables VARIABLE Y_zd : std_ulogic := 'X'; VARIABLE YNeg_zd : std_ulogic := 'X'; VARIABLE Pviol_D : X01 := '0'; VARIABLE PD_D : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ENeg : X01 := '0'; VARIABLE PD_ENeg : VitalPeriodDataType := VitalPeriodDataInit; -- Output Glitch Detection Variables VARIABLE QA_GlitchData : VitalGlitchDataType; VARIABLE QANeg_GlitchData : VitalGlitchDataType; VARIABLE QB_GlitchData : VitalGlitchDataType; VARIABLE QBNeg_GlitchData : VitalGlitchDataType; VARIABLE QC_GlitchData : VitalGlitchDataType; VARIABLE QCNeg_GlitchData : VitalGlitchDataType; VARIABLE QD_GlitchData : VitalGlitchDataType; VARIABLE QDNeg_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => D_ipd, TestSignalName => "D", Period => tperiod_D_posedge, HeaderMsg => InstancePath & "/nlb6210", CheckEnabled => TRUE, PeriodData => PD_D, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_D ); VitalPeriodPulseCheck ( TestSignal => ENeg_ipd, TestSignalName => "ENeg", Period => tperiod_D_posedge, HeaderMsg => InstancePath & "/nlb6210", CheckEnabled => TRUE, PeriodData => PD_ENeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_ENeg ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Y_zd := VitalOR2 (a => D_ipd, b => ENeg_ipd, ResultMap => ECL_wired_or_rmap); YNeg_zd := VitalNOR2 (a => D_ipd, b => ENeg_ipd, ResultMap => ECL_wired_or_rmap); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => QA, OutSignalName => "QA", OutTemp => Y_zd, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => tpd_D_QA, PathCondition => TRUE ), 1 => (InputChangeTime => ENeg_ipd'LAST_EVENT, PathDelay => tpd_ENeg_QA, PathCondition => TRUE ) ), Mode => VitalTransport, GlitchData => QA_GlitchData ); VitalPathDelay01 ( OutSignal => QANeg, OutSignalName => "QANeg", OutTemp => YNeg_zd, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => tpd_D_QA, PathCondition => TRUE ), 1 => (InputChangeTime => ENeg_ipd'LAST_EVENT, PathDelay => tpd_ENeg_QA, PathCondition => TRUE ) ), Mode => VitalTransport, GlitchData => QANeg_GlitchData ); VitalPathDelay01 ( OutSignal => QB, OutSignalName => "QB", OutTemp => Y_zd, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => tpd_D_QA, PathCondition => TRUE ), 1 => (InputChangeTime => ENeg_ipd'LAST_EVENT, PathDelay => tpd_ENeg_QA, PathCondition => TRUE ) ), Mode => VitalTransport, GlitchData => QB_GlitchData ); VitalPathDelay01 ( OutSignal => QBNeg, OutSignalName => "QBNeg", OutTemp => YNeg_zd, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => tpd_D_QA, PathCondition => TRUE ), 1 => (InputChangeTime => ENeg_ipd'LAST_EVENT, PathDelay => tpd_ENeg_QA, PathCondition => TRUE ) ), Mode => VitalTransport, GlitchData => QBNeg_GlitchData ); VitalPathDelay01 ( OutSignal => QC, OutSignalName => "QC", OutTemp => Y_zd, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => tpd_D_QA, PathCondition => TRUE ), 1 => (InputChangeTime => ENeg_ipd'LAST_EVENT, PathDelay => tpd_ENeg_QA, PathCondition => TRUE ) ), Mode => VitalTransport, GlitchData => QC_GlitchData ); VitalPathDelay01 ( OutSignal => QCNeg, OutSignalName => "QCNeg", OutTemp => YNeg_zd, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => tpd_D_QA, PathCondition => TRUE ), 1 => (InputChangeTime => ENeg_ipd'LAST_EVENT, PathDelay => tpd_ENeg_QA, PathCondition => TRUE ) ), Mode => VitalTransport, GlitchData => QCNeg_GlitchData ); VitalPathDelay01 ( OutSignal => QD, OutSignalName => "QD", OutTemp => Y_zd, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => tpd_D_QA, PathCondition => TRUE ), 1 => (InputChangeTime => ENeg_ipd'LAST_EVENT, PathDelay => tpd_ENeg_QA, PathCondition => TRUE ) ), Mode => VitalTransport, GlitchData => QD_GlitchData ); VitalPathDelay01 ( OutSignal => QDNeg, OutSignalName => "QDNeg", OutTemp => YNeg_zd, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => tpd_D_QA, PathCondition => TRUE ), 1 => (InputChangeTime => ENeg_ipd'LAST_EVENT, PathDelay => tpd_ENeg_QA, PathCondition => TRUE ) ), Mode => VitalTransport, GlitchData => QDNeg_GlitchData ); END PROCESS; END vhdl_behavioral;