-------------------------------------------------------------------------------- -- File name : nlb6203.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997, 1998 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V2.0 rev3 23 MAR 96 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Munden 98 SEP 09 changed style from concurrent proceedures -- to process, from inertial delay to -- transport and added period checks -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: NLB -- Technology: ECL -- Part: NLB6203 -- -- Description: 3-input AND gate with complementary NAND output -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.all; USE IEEE.VITAL_timing.all; LIBRARY FMF; USE FMF.ecl_utils.all; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY nlb6203 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A : VitalDelayType01 := VitalZeroDelay01; tipd_B : VitalDelayType01 := VitalZeroDelay01; tipd_C : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_A_Y : VitalDelayType01 := ECLUnitDelay01; tpd_B_Y : VitalDelayType01 := ECLUnitDelay01; tpd_C_Y : VitalDelayType01 := ECLUnitDelay01; -- tperiod_min: minimum clock period = 1/max freq tperiod_A_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; InstancePath : STRING := DefaultECLInstancePath; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); port ( -- 0 denotes internal pull-down resistor A : IN std_logic := '0'; B : IN std_logic := '0'; C : IN std_logic := '0'; Y : OUT std_logic := 'U'; YNeg : OUT std_logic := 'U' ); ATTRIBUTE VITAL_level0 OF nlb6203 : ENTITY IS TRUE; END nlb6203; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF nlb6203 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL A_ipd : std_ulogic := 'X'; SIGNAL B_ipd : std_ulogic := 'X'; SIGNAL C_ipd : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (A_ipd, A, tipd_A); w_2: VitalWireDelay (B_ipd, B, tipd_B); w_3: VitalWireDelay (C_ipd, C, tipd_C); END BLOCK; ---------------------------------------------------------------------------- -- VITALBehavior Process ---------------------------------------------------------------------------- VITALBehavior1 : PROCESS(A_ipd, B_ipd, C_ipd) -- Functionality Results Variables VARIABLE Y_zd : std_ulogic := 'X'; VARIABLE YNeg_zd : std_ulogic := 'X'; VARIABLE Pviol_A : X01 := '0'; VARIABLE PD_A : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_B : X01 := '0'; VARIABLE PD_B : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_C : X01 := '0'; VARIABLE PD_C : VitalPeriodDataType := VitalPeriodDataInit; -- Output Glitch Detection Variables VARIABLE Y_GlitchData : VitalGlitchDataType; VARIABLE YNeg_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => A_ipd, TestSignalName => "A", Period => tperiod_A_posedge, HeaderMsg => InstancePath & "/nlb6203", CheckEnabled => TRUE, PeriodData => PD_A, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_A ); VitalPeriodPulseCheck ( TestSignal => B_ipd, TestSignalName => "B", Period => tperiod_A_posedge, HeaderMsg => InstancePath & "/nlb6203", CheckEnabled => TRUE, PeriodData => PD_B, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_B ); VitalPeriodPulseCheck ( TestSignal => C_ipd, TestSignalName => "C", Period => tperiod_A_posedge, HeaderMsg => InstancePath & "/nlb6203", CheckEnabled => TRUE, PeriodData => PD_C, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_C ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Y_zd := VitalAND3 (a => A_ipd, b => B_ipd, c => C_ipd, ResultMap => ECL_wired_or_rmap); YNeg_zd := VitalNAND3 (a => A_ipd, b => B_ipd, c => C_ipd, ResultMap => ECL_wired_or_rmap); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Y, OutSignalName => "Y", OutTemp => Y_zd, Paths => ( 0 => (InputChangeTime => A_ipd'LAST_EVENT, PathDelay => tpd_A_Y, PathCondition => TRUE ), 1 => (InputChangeTime => B_ipd'LAST_EVENT, PathDelay => tpd_B_Y, PathCondition => TRUE ), 2 => (InputChangeTime => C_ipd'LAST_EVENT, PathDelay => tpd_C_Y, PathCondition => TRUE ) ), Mode => VitalTransport, GlitchData => Y_GlitchData ); VitalPathDelay01 ( OutSignal => YNeg, OutSignalName => "YNeg", OutTemp => YNeg_zd, Paths => ( 0 => (InputChangeTime => A_ipd'LAST_EVENT, PathDelay => tpd_A_Y, PathCondition => TRUE ), 1 => (InputChangeTime => B_ipd'LAST_EVENT, PathDelay => tpd_B_Y, PathCondition => TRUE ), 2 => (InputChangeTime => C_ipd'LAST_EVENT, PathDelay => tpd_C_Y, PathCondition => TRUE ) ), Mode => VitalTransport, GlitchData => YNeg_GlitchData ); END PROCESS; END vhdl_behavioral;