--------------------------------------------------------------------------------
--  File name: semirigid.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1997 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:  | mod date: | changes made:
--    V3.0     R. Steele   97 OCT 25   All new methodology; preliminary
--------------------------------------------------------------------------------
--   PART DESCRIPTION:
-- 
--   Library:     MISC
--   Technology:  N/A
--   Part:        SEMIRIGID
-- 
--   Desciption:  Delay Line  
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.gen_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY semirigid IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_B              : VitalDelayType01 := (10 ps, 10 ps);
        tipd_A              : VitalDelayType01 := (10 ps, 10 ps);
        -- tpd delays
        tpd_A_B             : VitalDelayType01 := (10 ps, 10 ps);
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        A               : INOUT std_logic := 'Z'; 
        B               : INOUT std_logic := 'Z'  
    );                                            
    ATTRIBUTE VITAL_level0 OF semirigid : ENTITY IS TRUE;
END semirigid;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
-- Note that this model will not work well unless there is some default
-- TIPD delay.  The simulator must also be set for a resolution that directly
-- corresponds to that minimum delay.  Furtermore, since this model uses a 
-- break-before-make method, glitches lasting one delta delay are often created
-- on an event.
--------------------------------------------------------------------------------

ARCHITECTURE vhdl_behavioral OF semirigid IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS FALSE;

    SIGNAL B_ipd            : std_ulogic := 'X';
    SIGNAL A_ipd            : std_ulogic := 'X';
    SIGNAL A_Busy           : BOOLEAN := FALSE;
    SIGNAL B_Busy           : BOOLEAN := FALSE;
    SIGNAL What_A_is        : std_logic := 'Z';
    SIGNAL What_B_is        : std_logic := 'Z';


BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (B_ipd, B, tipd_B);
        w_2 : VitalWireDelay (A_ipd, A, tipd_A);

    END BLOCK;

    A_side : PROCESS

        VARIABLE FirstA         : BOOLEAN := TRUE;
        VARIABLE AFromB         : BOOLEAN := FALSE;
        VARIABLE AFromA         : BOOLEAN := FALSE;
        VARIABLE A_Before       : std_logic := 'X';
        VARIABLE Delay          : TIME := 1 us;

    BEGIN

        WAIT ON    A'TRANSACTION, B_IPD'TRANSACTION, A_Busy'TRANSACTION
             UNTIL NOW > 0 ps;

        IF (A'ACTIVE) THEN
            IF (AFromB OR AFromA) THEN
                AFromB := FALSE;
                AFromA := FALSE;
            ELSE
                IF (FirstA) THEN
                    A <= 'Z';
                    FirstA := FALSE;
                ELSE
                    What_A_is <= A;
                    A <= A_Before;
                    AFromA := TRUE;
                    FirstA := TRUE;
                END IF;
            END IF;
        END IF;

        IF (B_IPD'ACTIVE OR A_Busy) THEN

            Delay := VitalCalcDelay(
                         NewVal => What_B_is,
                         OldVal => A_Before,
                         Delay  => tpd_A_B
                     );

            IF (A'QUIET) THEN
                A <= TRANSPORT What_B_is AFTER Delay;
                AFromB := TRUE;
                A_Before := What_B_is;
                A_Busy <= TRANSPORT FALSE AFTER Delay;
            ELSE
                A_Busy <= TRANSPORT TRUE AFTER Delay;
            END IF;
        END IF;

    END PROCESS;

    B_side : PROCESS

        VARIABLE FirstB         : BOOLEAN := TRUE;
        VARIABLE BFromA         : BOOLEAN := FALSE;
        VARIABLE BFromB         : BOOLEAN := FALSE;
        VARIABLE B_Before       : std_logic := 'X';
        VARIABLE Delay          : TIME := 1 us;

    BEGIN

        WAIT ON    B'TRANSACTION, A_IPD'TRANSACTION, B_Busy'TRANSACTION
             UNTIL NOW > 0 ns;

        IF (B'ACTIVE) THEN
            IF (BFromA OR BFromB) THEN
                BFromA := FALSE;
                BFromB := FALSE;
            ELSE
                IF (FirstB) THEN
                    B <= 'Z';
                    FirstB := FALSE;
                ELSE
                    What_B_is <= B;
                    B <= B_Before;
                    BFromB := TRUE;
                    FirstB := TRUE;
                END IF;
            END IF;
        END IF;

        IF (A_IPD'ACTIVE OR B_Busy) THEN

            Delay := VitalCalcDelay(
                         NewVal => What_A_is,
                         OldVal => B_Before,
                         Delay  => tpd_A_B
                     );

            IF (B'QUIET) THEN
                B <= TRANSPORT What_A_is AFTER Delay;
                BFromA := TRUE;
                B_Before := What_A_is;
                B_Busy <= TRANSPORT FALSE AFTER Delay;
            ELSE
                B_Busy <= TRANSPORT TRUE AFTER Delay;
            END IF;
        END IF;

    END PROCESS;

END vhdl_behavioral;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_dummy of semirigid IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_dummy : ARCHITECTURE IS FALSE;

    SIGNAL B_ipd               : std_ulogic := 'X';
    SIGNAL A_ipd               : std_ulogic := 'X';

BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (B_ipd, B, tipd_B);
        w_2 : VitalWireDelay (A_ipd, A, tipd_A);

    END BLOCK;

    A <= 'Z';
    B <= 'Z';

END vhdl_dummy;