-- -----------------------------------------------------------------------------
--   File Name : sc0900.vhd
-- -----------------------------------------------------------------------------
--  Copyright (C) 1996-2008 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY :
-- 
--    version |  author   | mod date | changes made:
--    V2.0     R. Steele   96 AUG 06   Conformes to style guide
--    V2.1     R. Munden   97 MAR 01   Changed XGenerationOn to XOn, added MsgOn,
--                                     and updated TimingChecks & PathDelays
--    V2.2     R. Munden   08 MAY 07   Made resultmap locally static
-- -----------------------------------------------------------------------------
--   PART DESCRIPTION :
-- 
--   Library:     MISC
--   Technology:  GaAs
--   Part:        SC0900
-- 
--   Desciption:  Variable Amplitude Driver
-- -----------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.all;
                USE IEEE.VITAL_primitives.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY sc0900 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_SIN             : VitalDelayType01 := VitalZeroDelay01;
        tipd_SINNeg          : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_SIN_SOUT         : VitalDelayType01 := ECLUnitDelay01;
        -- generic control parameters
        InstancePath     : STRING := DefaultECLInstancePath;
        TimingChecksOn   : BOOLEAN := DefaultECLTimingChecks;
        MsgOn               : BOOLEAN := DefaultECLMsgOn;
        XOn              : BOOLEAN := DefaultECLXOn;
        -- For FMF SDF technology file usage
        TimingModel      : STRING := DefaultECLTimingModel
    );
    PORT (
        -- 0 denotes pull-down resistor
        SIN           : IN    STD_LOGIC := '0';
        SINNeg        : IN    STD_LOGIC := '0';
        SOUT          : OUT   STD_LOGIC := 'U';
        SOUTNeg       : OUT   STD_LOGIC := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of sc0900 : ENTITY IS TRUE;
END sc0900;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of sc0900 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL SIN_ipd        : std_ulogic := 'X';
    SIGNAL SINNeg_ipd     : std_ulogic := 'X';
    SIGNAL SINint         : std_ulogic := 'X';

BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (SIN_ipd, SIN, tipd_SIN);
        w_2: VitalWireDelay (SINNeg_ipd, SINNeg, tipd_SINNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalBUF (q => SOUT, a => SINint, ResultMap => ('U','X','Z','1'));
    a_2: VitalINV (q => SOUTNeg, a => SINint, ResultMap => ('U','X','Z','1'));

    ----------------------------------------------------------------------------
    -- ECL Clock Process with delay
    ----------------------------------------------------------------------------
    ECLClock : PROCESS (SIN_ipd, SINNeg_ipd)

        -- Functionality Results Variables
        VARIABLE Mode           : X01;
        VARIABLE SINint_zd      : std_ulogic;
        VARIABLE PrevData       : std_logic_vector(0 to 2);
 
        -- Output Glitch Detection Variables
        VARIABLE SIN_GlitchData   : VitalGlitchDataType;
 
    BEGIN
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Mode := ECL_diff_mode_tab (SIN_ipd, SINNeg_ipd);

        VitalStateTable (
            StateTable      => ECL_clk_tab,
            DataIn          => (SIN_ipd, SINNeg_ipd, Mode),
            Result          => SINint_zd,
            PreviousDataIn  => PrevData
        );
 
        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => SINint,
            OutSignalName   => "SINint",
            OutTemp         => SINint_zd,
            GlitchData      => SIN_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => SIN_ipd'LAST_EVENT,
                      PathDelay         => tpd_SIN_SOUT,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => SINNeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_SIN_SOUT,
                      PathCondition     => TRUE)
            )
        );
 
    END PROCESS;

END vhdl_behavioral;