--------------------------------------------------------------------------------
--  File Name: max809.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2000 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    00 Nov 30   Initial release
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    MISC
--  Technology: TTL/CMOS
--  Part:       MAX809
-- 
--  Description: Microprocessor Reset Circuit
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY max809 IS
    GENERIC (
        -- tpd delays
        tpd_VCC_RSTNeg           : VitalDelayType01 := UnitDelay01;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        GND             : IN    std_ulogic := 'U';
        VCC             : IN    std_ulogic := 'U';
        RSTNeg          : OUT   std_ulogic := '0'
    );
    ATTRIBUTE VITAL_LEVEL0 of max809 : ENTITY IS TRUE;
END max809;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of max809 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;


BEGIN

    ----------------------------------------------------------------------------
    -- Behavior Process
    ----------------------------------------------------------------------------
    RESET : PROCESS(VCC)

    -- Functionality Results Variables
    VARIABLE RST_zd   : std_ulogic;

    -- Output Glitch Detection Variables
    VARIABLE RST_GlitchData   : VitalGlitchDataType;

    BEGIN

        RST_zd := VCC;

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => RSTNeg,
            OutSignalName   => "RSTNeg",
            OutTemp         => RST_zd,
            GlitchData      => RST_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => VCC'LAST_EVENT,
                      PathDelay         => tpd_VCC_RSTNeg,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS RESET;

END vhdl_behavioral;