--------------------------------------------------------------------------------
--  File Name: jumper.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1997 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Steele   97 SEP 08   Initial release
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    MISC
--  Technology: N/A
--  Part:       JUMPER
-- 
--  Desciption: Circuit board jumper gap
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY jumper IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_B              : VitalDelayType01 := (10 ps,10 ps);
        tipd_A              : VitalDelayType01 := (10 ps,10 ps);
        -- tpd delays
        tpd_A_B                         : VitalDelayType := 10 ps
    );
    PORT (
        A               : INOUT std_logic := 'Z'; 
        B               : INOUT std_logic := 'Z'  
    );                                            

    ATTRIBUTE VITAL_LEVEL0 of jumper : ENTITY IS TRUE;
END jumper;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of jumper IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE;

    SIGNAL B_ipd               : std_ulogic := 'X';
    SIGNAL A_ipd               : std_ulogic := 'X';

BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (B_ipd, B, tipd_B);
        w_2 : VitalWireDelay (A_ipd, A, tipd_A);

    END BLOCK;

    A <= 'Z';
    B <= 'Z';

END vhdl_behavioral;


--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_ecl_open of jumper IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_ecl_open : ARCHITECTURE IS FALSE;

    SIGNAL B_ipd               : std_ulogic := 'X';
    SIGNAL A_ipd               : std_ulogic := 'X';

BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (B_ipd, B, tipd_B);
        w_2 : VitalWireDelay (A_ipd, A, tipd_A);

    END BLOCK;

    A <= 'L';
    B <= 'L';

END vhdl_ecl_open;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
-- Note that this model will not work well unless there is some default
-- TIPD delay.  The simulator must also be set for a resolution that directly
-- corresponds to that minimum delay.
--------------------------------------------------------------------------------

ARCHITECTURE vhdl_wire OF jumper IS
    ATTRIBUTE VITAL_level1 OF vhdl_wire : ARCHITECTURE IS FALSE;

    SIGNAL B_ipd      : std_ulogic := 'X';
    SIGNAL A_ipd      : std_ulogic := 'X';
    SIGNAL A_BUSY     : BOOLEAN := FALSE;
    SIGNAL B_BUSY     : BOOLEAN := FALSE;
    SIGNAL WHAT_A_IS  : std_logic := 'Z';
    SIGNAL WHAT_B_IS  : std_logic := 'Z';


BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (B_ipd, B, tipd_B);
        w_2 : VitalWireDelay (A_ipd, A, tipd_A);

    END BLOCK;

    ASIDE : PROCESS

        VARIABLE firstA     : BOOLEAN := TRUE;
        VARIABLE AFROMB     : BOOLEAN := false;
        VARIABLE AFROMA     : BOOLEAN := false;
        VARIABLE A_BEFORE   : std_logic := 'X';

    BEGIN

        WAIT ON    A'TRANSACTION, B_IPD'TRANSACTION, A_BUSY'TRANSACTION
             UNTIL NOW > 0 ns;


            IF (A'ACTIVE) THEN
                IF (AFROMB OR AFROMA) THEN
                    AFROMB := FALSE;
                    AFROMA := FALSE;
                ELSE
                    IF (FIRSTA) THEN
                        A <= 'Z';
                        FIRSTA := FALSE;
                    ELSE
                        WHAT_A_IS <= A;
                        A <= A_BEFORE;
                        AFROMA := TRUE;
                        FIRSTA := TRUE;
                    END IF;
                END IF;
            END IF;

            IF (B_IPD'ACTIVE OR A_BUSY) THEN
                IF (A'QUIET) THEN
                    --WAIT FOR TPD_A_B;
                    A <= transport WHAT_B_IS after tpd_a_b;
                    AFROMB := TRUE;
                    A_BEFORE := WHAT_B_IS;
                    A_BUSY <= transport FALSE after tpd_a_b;
                ELSE
                    A_BUSY <= transport TRUE after tpd_a_b;
                END IF;
            END IF;


    END PROCESS;

    BSIDE : PROCESS

        VARIABLE firstB     : BOOLEAN := TRUE;
        VARIABLE BFROMA     : BOOLEAN := false;
        VARIABLE BFROMB     : BOOLEAN := false;
        VARIABLE B_BEFORE   : std_logic := 'X';

    BEGIN

        WAIT ON    B'TRANSACTION, A_IPD'TRANSACTION, B_BUSY'TRANSACTION
             UNTIL NOW > 0 ns;


            IF (B'ACTIVE) THEN
                IF (BFROMA OR BFROMB) THEN
                    BFROMA := FALSE;
                    BFROMB := FALSE;
                ELSE
                    IF (FIRSTB) THEN
                        B <= 'Z';
                        FIRSTB := FALSE;
                    ELSE
                        WHAT_B_IS <= B;
                        B <= B_BEFORE;
                        BFROMB := TRUE;
                        FIRSTB := TRUE;
                    END IF;
                END IF;
            END IF;

            IF (A_IPD'ACTIVE OR B_BUSY) THEN
                IF (B'QUIET) THEN
                    --WAIT FOR TPD_A_B;
                    B <= transport WHAT_A_IS after tpd_a_b;
                    BFROMA := TRUE;
                    B_BEFORE := WHAT_A_IS;
                    B_BUSY <= transport FALSE after tpd_a_b;
                ELSE
                    B_BUSY <= transport TRUE after tpd_a_b;
                END IF;
            END IF;


    END PROCESS;


END vhdl_wire;