-- ---------------------------------------------------------------
--   File name : conn.vhd
-- ---------------------------------------------------------------
--  Copyright (C) 1997 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--   MODIFICATION HISTORY :
-- 
--      version no: |   author: |   mod. date: |    changes made:
--      V1.0            rev3        02/16/96    Initial coding
--      V1.1            rev3        02/24/97    Added internal signal
--                                              for wire delay
-- ---------------------------------------------------------------
--   PART DESCRIPTION :
-- 
--   Library:       CONNECTOR
--   Technology:    N/A
--   Part:          CONN
-- 
--   Description:   generic connector
-- 
------------------------------------------------------------------ 
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.all;
                USE IEEE.VITAL_primitives.all;

------------------------------------------------------------------
-- ENTITY DECLARATION
------------------------------------------------------------------
ENTITY conn IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A              : VitalDelayType01 := VitalZeroDelay01
    );
    PORT (    
        A               : INOUT  STD_LOGIC := 'Z'
	);
    ATTRIBUTE VITAL_LEVEL0 of conn : ENTITY IS TRUE;
END conn;

------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF conn IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic;

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        VitalWireDelay (A_ipd, A, tipd_A);

    END BLOCK;

END vhdl_behavioral;