-------------------------------------------------------------------------------- -- File Name: adv7179.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2004 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 V.Ljubisavljevic 04 Oct 28 Initial release -- -- This model must be compiled without VITAL compliance checking -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: VIDEO_ENCODER_VHDL -- Technology: CMOS -- Part: ADV7174/ADV7179 -- Description: PAL/NTSC Video Encoder -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.math_real.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY adv7179 IS GENERIC ( -- tipd delays: interconnect path delays tipd_P0 : VitalDelayType01 := VitalZeroDelay01; tipd_P1 : VitalDelayType01 := VitalZeroDelay01; tipd_P2 : VitalDelayType01 := VitalZeroDelay01; tipd_P3 : VitalDelayType01 := VitalZeroDelay01; tipd_P4 : VitalDelayType01 := VitalZeroDelay01; tipd_P5 : VitalDelayType01 := VitalZeroDelay01; tipd_P6 : VitalDelayType01 := VitalZeroDelay01; tipd_P7 : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_HSYNCNeg : VitalDelayType01 := VitalZeroDelay01; tipd_VSYNCNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BLANKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLOCK : VitalDelayType01 := VitalZeroDelay01; tipd_SCLOCK : VitalDelayType01 := VitalZeroDelay01; tipd_SDATA : VitalDelayType01 := VitalZeroDelay01; tipd_ALSB : VitalDelayType01 := VitalZeroDelay01; tipd_SCRESET : VitalDelayType01 := VitalZeroDelay01; tipd_TTX : VitalDelayType01 := VitalZeroDelay01; -- tpd values tpd_CLOCK_HSYNCNeg : VitalDelayType01Z := UnitDelay01Z; tpd_CLOCK_TTXREQ : VitalDelayType01Z := UnitDelay01Z; -- tsetup values: setup times tsetup_P0_CLOCK : VitalDelayType := UnitDelay; tsetup_HSYNCNeg_CLOCK : VitalDelayType := UnitDelay; tsetup_SDATA_SCLOCK : VitalDelayType := UnitDelay; tsetup_SCLOCK_SDATA : VitalDelayType := UnitDelay; tsetup_TTX_CLOCK : VitalDelayType := UnitDelay; -- thold values: hold times thold_P0_CLOCK : VitalDelayType := UnitDelay; thold_HSYNCNeg_CLOCK_noedge_MASTER_EQ_0: VitalDelayType := UnitDelay; thold_HSYNCNeg_CLOCK_noedge_MASTER_EQ_1: VitalDelayType := UnitDelay; thold_SCLOCK_SDATA : VitalDelayType := UnitDelay; thold_TTX_CLOCK : VitalDelayType := UnitDelay; -- tpw values: pulse widths tpw_CLOCK_posedge : VitalDelayType := UnitDelay; tpw_CLOCK_negedge : VitalDelayType := UnitDelay; tpw_SCLOCK_posedge : VitalDelayType := UnitDelay; tpw_SCLOCK_negedge : VitalDelayType := UnitDelay; tpw_RESETNeg_negedge : VitalDelayType := UnitDelay; -- analog generics: value of Vref input In Volts Vref : real; -- generic control parameters InstancePath : STRING:= DefaultInstancePath; TimingChecksOn : BOOLEAN:= DefaultTimingChecks; MsgOn : BOOLEAN:= DefaultMsgOn; XOn : BOOLEAN:= DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING:= DefaultTimingModel ); PORT ( P0 : IN std_ulogic := 'U'; P1 : IN std_ulogic := 'U'; P2 : IN std_ulogic := 'U'; P3 : IN std_ulogic := 'U'; P4 : IN std_ulogic := 'U'; P5 : IN std_ulogic := 'U'; P6 : IN std_ulogic := 'U'; P7 : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; HSYNCNeg : INOUT std_logic := 'U'; VSYNCNeg : INOUT std_logic := 'U'; BLANKNeg : INOUT std_logic := 'U'; CLOCK : IN std_ulogic := 'U'; SCLOCK : IN std_ulogic := 'U'; SDATA : INOUT std_logic := 'U'; ALSB : IN std_ulogic := 'U'; SCRESET : IN std_ulogic := 'U'; TTX : IN std_ulogic := 'U'; TTXREQ : OUT std_logic := 'U'; OUTA : OUT real := 0.0; OUTB : OUT real := 0.0; OUTC : OUT real := 0.0 ); ATTRIBUTE VITAL_LEVEL0 of adv7179 : ENTITY IS TRUE; END adv7179; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of adv7179 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "adv7179"; CONSTANT resolution : NATURAL := 10; CONSTANT DEVICE_ADDR : std_logic_vector(5 DOWNTO 0):="010101"; CONSTANT SYNC_LUMA : NATURAL := 102; CONSTANT CLK_PERIOD : TIME := 38 ns; SIGNAL P0_ipd : std_ulogic := 'U'; SIGNAL P1_ipd : std_ulogic := 'U'; SIGNAL P2_ipd : std_ulogic := 'U'; SIGNAL P3_ipd : std_ulogic := 'U'; SIGNAL P4_ipd : std_ulogic := 'U'; SIGNAL P5_ipd : std_ulogic := 'U'; SIGNAL P6_ipd : std_ulogic := 'U'; SIGNAL P7_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; SIGNAL HSYNCNeg_ipd : std_ulogic := 'U'; SIGNAL VSYNCNeg_ipd : std_ulogic := 'U'; SIGNAL BLANKNeg_ipd : std_ulogic := 'U'; SIGNAL CLOCK_ipd : std_ulogic := 'U'; SIGNAL SCLOCK_ipd : std_ulogic := 'U'; SIGNAL SDATA_ipd : std_ulogic := 'U'; SIGNAL ALSB_ipd : std_ulogic := 'U'; SIGNAL SCRESET_ipd : std_ulogic := 'U'; SIGNAL TTX_ipd : std_ulogic := 'U'; SIGNAL TTXREQ_ipd : std_ulogic := 'U'; SIGNAL SHDNNeg_ipd : std_ulogic := 'U'; SIGNAL UPDATEA : std_ulogic := '0'; SIGNAL UPDATEB : std_ulogic := '0'; SIGNAL UPDATEC : std_ulogic := '0'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (P0_ipd, P0, tipd_P0); w_2 : VitalWireDelay (P1_ipd, P1, tipd_P1); w_3 : VitalWireDelay (P2_ipd, P2, tipd_P2); w_4 : VitalWireDelay (P3_ipd, P3, tipd_P3); w_5 : VitalWireDelay (P4_ipd, P4, tipd_P4); w_6 : VitalWireDelay (P5_ipd, P5, tipd_P5); w_7 : VitalWireDelay (P6_ipd, P6, tipd_P6); w_8 : VitalWireDelay (P7_ipd, P7, tipd_P7); w_9 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg); w_10 : VitalWireDelay (HSYNCNeg_ipd, HSYNCNeg, tipd_HSYNCNeg); w_11 : VitalWireDelay (VSYNCNeg_ipd, VSYNCNeg, tipd_VSYNCNeg); w_12 : VitalWireDelay (BLANKNeg_ipd, BLANKNeg, tipd_BLANKNeg); w_13 : VitalWireDelay (CLOCK_ipd, CLOCK, tipd_CLOCK); w_14 : VitalWireDelay (SCLOCK_ipd, SCLOCK, tipd_SCLOCK); w_15 : VitalWireDelay (SDATA_ipd, SDATA, tipd_SDATA); w_16 : VitalWireDelay (ALSB_ipd, ALSB, tipd_ALSB); w_17 : VitalWireDelay (SCRESET_ipd, SCRESET, tipd_SCRESET); w_18 : VitalWireDelay (TTX_ipd, TTX, tipd_TTX); END BLOCK; Behavior : BLOCK PORT ( P : IN std_logic_vector(7 DOWNTO 0) :=(OTHERS => 'U'); RESETNeg : IN std_ulogic := 'U'; HSYNCNeg_in : IN std_ulogic := 'U'; HSYNCNeg_out : OUT std_logic := 'U'; VSYNCNeg_in : IN std_ulogic := 'U'; VSYNCNeg_out : OUT std_logic := 'U'; BLANKNeg_in : IN std_ulogic := 'U'; BLANKNeg_out : OUT std_logic := 'U'; CLOCK : IN std_ulogic := 'U'; SCLOCK : IN std_ulogic := 'U'; SDATA_in : IN std_logic := 'U'; SDATA_out : OUT std_logic := 'U'; ALSB : IN std_ulogic := 'U'; SCRESET : IN std_ulogic := 'U'; TTX : IN std_ulogic := 'U'; TTXREQ : OUT std_logic := 'U'; OUTA : OUT real := 0.0; OUTB : OUT real := 0.0; OUTC : OUT real := 0.0 ); PORT MAP ( P(7) => P7_ipd, P(6) => P6_ipd, P(5) => P5_ipd, P(4) => P4_ipd, P(3) => P3_ipd, P(2) => P2_ipd, P(1) => P1_ipd, P(0) => P0_ipd, RESETNeg => RESETNeg_ipd, HSYNCNeg_in => HSYNCNeg_ipd, HSYNCNeg_out => HSYNCNeg, VSYNCNeg_in => VSYNCNeg_ipd, VSYNCNeg_out => VSYNCNeg, BLANKNeg_in => BLANKNeg_ipd, BLANKNeg_out => BLANKNeg, CLOCK => CLOCK_ipd, SCLOCK => SCLOCK_ipd, SDATA_in => SDATA_ipd, SDATA_out => SDATA, ALSB => ALSB_ipd, SCRESET => SCRESET_ipd, TTX => TTX_ipd, TTXREQ => TTXREQ, OUTA => OUTA, OUTB => OUTB, OUTC => OUTC ); -- Parallel State Machine : State_Type TYPE state_type IS ( RESET, ACTIVE_LINE, HBLANK_SYNC, HBLANK_BURST, HBLANK ); -- I2C State Machine : I2C_State_Type TYPE I2C_state_type IS ( IDLE, ADDR_ACK, SUBADDR_ACK, WRITE_ACK, READ_ACK, ADDR_LATCH, SUBADDR_LATCH, READ, WRITE ); SUBTYPE dacval_type IS NATURAL RANGE 0 TO (2**resolution-1); SUBTYPE dacreg_type IS std_logic_vector(resolution-1 DOWNTO 0); TYPE BURST_TYPE IS ARRAY (0 TO 5) OF std_logic_vector(7 DOWNTO 0); TYPE FSC_TYPE IS ARRAY (0 TO 5) OF REAL; TYPE REG_TYPE IS ARRAY (0 TO 47) OF std_logic_vector(7 DOWNTO 0); TYPE CAPT_REG IS ARRAY (0 TO 3) OF std_logic_vector(7 DOWNTO 0); TYPE COEF_TYPE IS ARRAY (0 TO 54) OF REAL; TYPE COEF_ARRAY IS ARRAY (0 TO 6) OF COEF_TYPE; TYPE ORDER_TYPE IS ARRAY (0 TO 6) OF POSITIVE; TYPE FILT_TYPE IS ARRAY (0 TO 54) OF NATURAL; SIGNAL current_state : state_type; SIGNAL next_state : state_type; SIGNAL I2C_current_state : I2C_state_type; SIGNAL I2C_next_state : I2C_state_type; -- Powerup SIGNAL PoweredUp : std_logic := '0'; SIGNAL AV_PATTERN : std_logic := '0';-- SAV/EAV Pattern Flag SIGNAL HBLANK_in : std_logic := '0'; SIGNAL HBURST_in : std_logic := '0'; SIGNAL HSYNC_in : std_logic := '0'; SIGNAL EvenField : BOOLEAN := FALSE; SIGNAL dacvalA : dacval_type; SIGNAL dacvalB : dacval_type; SIGNAL dacvalC : dacval_type; SIGNAL OUTA_zd : real := 0.0; SIGNAL OUTB_zd : real := 0.0; SIGNAL OUTC_zd : real := 0.0; SIGNAL HSYNCNeg_zd : std_logic := 'Z'; SIGNAL VSYNCNeg_zd : std_logic := 'Z'; SIGNAL BLANKNeg_zd : std_logic := 'Z'; SIGNAL SDATA_zd : std_logic := 'Z'; SIGNAL TTXREQ_zd : std_logic := 'Z'; SIGNAL HSYNCNeg_tmp : std_logic := '0'; SIGNAL VSYNCNeg_tmp : std_logic := '0'; SIGNAL BLANKNeg_tmp : std_logic := '0'; SIGNAL ACK : std_logic := '0'; SIGNAL ACK_in : std_logic := '0'; SIGNAL ACK_out : std_logic := '0'; SIGNAL START : std_logic := '0'; SIGNAL STOP : std_logic := '0'; SIGNAL HBLANK_SYNC_act : std_logic := '0'; SIGNAL TTX_EN : BOOLEAN := FALSE; SIGNAL TTXREQ_EN : std_logic := '0'; SHARED VARIABLE d_cnt : NATURAL RANGE 0 TO 3:= 0; -- Capture Registers SHARED VARIABLE CREG : CAPT_REG:=(OTHERS=>(OTHERS=>'1')); -- input components SHARED VARIABLE Yin, Cb, Cr : std_logic_vector(7 DOWNTO 0) :=(OTHERS=>'0'); -- U, V input components SHARED VARIABLE Uin, Vin : std_logic_vector(7 DOWNTO 0) :=(OTHERS=>'0'); -- Luma with added synchronization SHARED VARIABLE Ysync : std_logic_vector(8 DOWNTO 0) :=(OTHERS=>'0'); -- Chroma with added burst SHARED VARIABLE Uburst : std_logic_vector(7 DOWNTO 0) :=(OTHERS=>'0'); SHARED VARIABLE Vburst : std_logic_vector(7 DOWNTO 0) :=(OTHERS=>'0'); SHARED VARIABLE HSYNC_cnt : NATURAL := 0; SHARED VARIABLE COEF_LUMA : COEF_ARRAY; SHARED VARIABLE COEF_CHROMA : COEF_ARRAY; SHARED VARIABLE Y_filt : FILT_TYPE:=(OTHERS=>0); SHARED VARIABLE U_filt : FILT_TYPE:=(OTHERS=>0); SHARED VARIABLE V_filt : FILT_TYPE:=(OTHERS=>0); SHARED VARIABLE REG_ARRAY : REG_TYPE; ALIAS MODE: std_logic_vector(2 DOWNTO 0)IS REG_ARRAY(7)(2 DOWNTO 0); ALIAS STANDARD: std_logic_vector(1 DOWNTO 0)IS REG_ARRAY(0)(1 DOWNTO 0); ALIAS TTXREQ_R: std_logic_vector(3 DOWNTO 0)IS REG_ARRAY(16#19#)(7 DOWNTO 4); ALIAS TTXREQ_F: std_logic_vector(3 DOWNTO 0)IS REG_ARRAY(16#19#)(3 DOWNTO 0); SHARED VARIABLE N_LUMA : ORDER_TYPE; SHARED VARIABLE N_CHROMA : ORDER_TYPE; SHARED VARIABLE DACA : STD_LOGIC_VECTOR(9 DOWNTO 0); SHARED VARIABLE DACB : STD_LOGIC_VECTOR(9 DOWNTO 0); SHARED VARIABLE DACC : STD_LOGIC_VECTOR(9 DOWNTO 0); SHARED VARIABLE VBLANK : BOOLEAN := FALSE; SHARED VARIABLE VBLANK_BURST: BOOLEAN := FALSE; SHARED VARIABLE CLK_cnt : NATURAL; SHARED VARIABLE Chr_cnt : NATURAL; SHARED VARIABLE LineCnt : NATURAL; SHARED VARIABLE DELTA_F : REAL := 0.0; SHARED VARIABLE alpha : REAL := 0.0; SHARED VARIABLE TTXControl : STD_LOGIC_VECTOR(15 DOWNTO 0); SHARED VARIABLE LastELine : NATURAL; SHARED VARIABLE LastOLine : NATURAL; SHARED VARIABLE FirstELine : NATURAL; SHARED VARIABLE FirstOLine : NATURAL; SHARED VARIABLE EBurstLine : NATURAL; SHARED VARIABLE OBurstLine : NATURAL; SHARED VARIABLE TTXcnt : NATURAL; SHARED VARIABLE TTXcntAUX : NATURAL; SHARED VARIABLE ADDR_cnt : NATURAL; SHARED VARIABLE I2C_data : std_logic_vector(7 DOWNTO 0); SHARED VARIABLE REG_ADDR : NATURAL; BEGIN PoweredUp <= '1' AFTER 100 ns; ---------------------------------------------------------------------------- -- Behavior Process ---------------------------------------------------------------------------- VITALTimingCheck : PROCESS (CLOCK, SCLOCK, SDATA_in, HSYNCNeg, VSYNCNeg, BLANKNeg, RESETNeg, TTX, P) -- Timing Check Variables VARIABLE Tviol_P0_CLOCK : X01 := '0'; VARIABLE Tviol_HSYNCNeg_CLOCK_slave : X01 := '0'; VARIABLE Tviol_HSYNCNeg_CLOCK_master: X01 := '0'; VARIABLE Tviol_VSYNCNeg_CLOCK_slave : X01 := '0'; VARIABLE Tviol_VSYNCNeg_CLOCK_master: X01 := '0'; VARIABLE Tviol_BLANKNeg_CLOCK_slave : X01 := '0'; VARIABLE Tviol_BLANKNeg_CLOCK_master: X01 := '0'; VARIABLE Tviol_SDATA_SCLOCK : X01 := '0'; VARIABLE Tviol_SCLOCK_SDATA_setup : X01 := '0'; VARIABLE Tviol_SCLOCK_SDATA_hold : X01 := '0'; VARIABLE Tviol_TTX_CLOCK : X01 := '0'; VARIABLE TD_P0_CLOCK : VitalTimingDataType; VARIABLE TD_HSYNCNeg_CLOCK_slave : VitalTimingDataType; VARIABLE TD_HSYNCNeg_CLOCK_master: VitalTimingDataType; VARIABLE TD_VSYNCNeg_CLOCK_slave : VitalTimingDataType; VARIABLE TD_VSYNCNeg_CLOCK_master: VitalTimingDataType; VARIABLE TD_BLANKNeg_CLOCK_slave : VitalTimingDataType; VARIABLE TD_BLANKNeg_CLOCK_master: VitalTimingDataType; VARIABLE TD_SDATA_SCLOCK : VitalTimingDataType; VARIABLE TD_SCLOCK_SDATA_setup : VitalTimingDataType; VARIABLE TD_SCLOCK_SDATA_hold : VitalTimingDataType; VARIABLE TD_TTX_CLOCK : VitalTimingDataType; -- Pulse width cheks variables VARIABLE Pviol_CLOCK : X01 := '0'; VARIABLE Pviol_SCLOCK : X01 := '0'; VARIABLE Pviol_RESETNeg : X01 := '0'; VARIABLE PD_CLOCK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_SCLOCK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => P(0), TestSignalName => "P", RefSignal => CLOCK, RefSignalName => "CLOCK", SetupHigh => tsetup_P0_CLOCK, SetupLow => tsetup_P0_CLOCK, HoldHigh => thold_P0_CLOCK, HoldLow => thold_P0_CLOCK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_P0_CLOCK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_P0_CLOCK ); VitalSetupHoldCheck ( TestSignal => HSYNCNeg, TestSignalName => "HSYNCNeg", RefSignal => CLOCK, RefSignalName => "CLOCK", SetupHigh => tsetup_HSYNCNeg_CLOCK, SetupLow => tsetup_HSYNCNeg_CLOCK, HoldHigh => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_0, HoldLow => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_0, CheckEnabled => MODE(0)='0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_HSYNCNeg_CLOCK_slave, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSYNCNeg_CLOCK_slave ); VitalSetupHoldCheck ( TestSignal => HSYNCNeg_tmp, TestSignalName => "HSYNCNeg", RefSignal => CLOCK, RefSignalName => "CLOCK", HoldHigh => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_1, HoldLow => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_1, CheckEnabled => MODE(0)='1', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_HSYNCNeg_CLOCK_master, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSYNCNeg_CLOCK_master ); VitalSetupHoldCheck ( TestSignal => VSYNCNeg, TestSignalName => "VSYNCNeg", RefSignal => CLOCK, RefSignalName => "CLOCK", SetupHigh => tsetup_HSYNCNeg_CLOCK, SetupLow => tsetup_HSYNCNeg_CLOCK, HoldHigh => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_0, HoldLow => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_0, CheckEnabled => MODE(0)='0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_VSYNCNeg_CLOCK_slave, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_VSYNCNeg_CLOCK_slave ); VitalSetupHoldCheck ( TestSignal => VSYNCNeg_tmp, TestSignalName => "VSYNCNeg", RefSignal => CLOCK, RefSignalName => "CLOCK", HoldHigh => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_1, HoldLow => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_1, CheckEnabled => MODE(0)='1', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_VSYNCNeg_CLOCK_master, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_VSYNCNeg_CLOCK_master ); VitalSetupHoldCheck ( TestSignal => BLANKNeg, TestSignalName => "BLANKNeg", RefSignal => CLOCK, RefSignalName => "CLOCK", SetupHigh => tsetup_HSYNCNeg_CLOCK, SetupLow => tsetup_HSYNCNeg_CLOCK, HoldHigh => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_0, HoldLow => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_0, CheckEnabled => MODE(0)='0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_BLANKNeg_CLOCK_slave, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BLANKNeg_CLOCK_slave ); VitalSetupHoldCheck ( TestSignal => BLANKNeg_tmp, TestSignalName => "BLANKNeg", RefSignal => CLOCK, RefSignalName => "CLOCK", HoldHigh => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_1, HoldLow => THOLD_HSYNCNeg_CLOCK_noedge_MASTER_EQ_1, CheckEnabled => MODE(0)='1', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_BLANKNeg_CLOCK_master, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BLANKNeg_CLOCK_master ); VitalSetupHoldCheck ( TestSignal => SDATA_in, TestSignalName => "SDATA_in", RefSignal => SCLOCK, RefSignalName => "SCLOCK", SetupHigh => tsetup_SDATA_SCLOCK, SetupLow => tsetup_SDATA_SCLOCK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SDATA_SCLOCK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDATA_SCLOCK ); VitalSetupHoldCheck ( TestSignal => SCLOCK, TestSignalName => "SCLOCK", RefSignal => SDATA_in, RefSignalName => "SDATA_in", SetupHigh => tsetup_SCLOCK_SDATA, CheckEnabled => I2C_current_state=IDLE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SCLOCK_SDATA_setup, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SCLOCK_SDATA_setup ); VitalSetupHoldCheck ( TestSignal => TTX, TestSignalName => "TTX", RefSignal => CLOCK, RefSignalName => "CLOCK", SetupHigh => tsetup_TTX_CLOCK, SetupLow => tsetup_TTX_CLOCK, HoldHigh => thold_TTX_CLOCK, HoldLow => thold_TTX_CLOCK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_TTX_CLOCK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_TTX_CLOCK ); VitalSetupHoldCheck ( TestSignal => SCLOCK, TestSignalName => "SCLOCK", RefSignal => SDATA_in, RefSignalName => "SDATA_in", HoldHigh => thold_SCLOCK_SDATA, CheckEnabled => I2C_current_state=IDLE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_SCLOCK_SDATA_hold, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SCLOCK_SDATA_hold ); VitalPeriodPulseCheck ( TestSignal => CLOCK, TestSignalName => "CLOCK", PulseWidthHigh => tpw_CLOCK_posedge, PulseWidthLow => tpw_CLOCK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_CLOCK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLOCK ); VitalPeriodPulseCheck ( TestSignal => SCLOCK, TestSignalName => "SCLOCK", PulseWidthHigh => tpw_SCLOCK_posedge, PulseWidthLow => tpw_SCLOCK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_SCLOCK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCLOCK ); VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESETNeg", PulseWidthLow => tpw_RESETNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RESETNeg ); Violation := Tviol_P0_CLOCK OR Tviol_HSYNCNeg_CLOCK_slave OR Tviol_HSYNCNeg_CLOCK_master OR Tviol_VSYNCNeg_CLOCK_slave OR Tviol_VSYNCNeg_CLOCK_master OR Tviol_BLANKNeg_CLOCK_slave OR Tviol_BLANKNeg_CLOCK_master OR Tviol_SDATA_SCLOCK OR Tviol_SCLOCK_SDATA_setup OR Tviol_SCLOCK_SDATA_hold OR Tviol_TTX_CLOCK OR Pviol_CLOCK OR Pviol_SCLOCK OR Pviol_RESETNeg; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY Warning; END IF; END PROCESS VITALTimingCheck; ------------------------------------------------------------------------ -- sequential process for reset control and FSM state transition ------------------------------------------------------------------------ StateTransition : PROCESS(next_state, I2C_next_state, RESETNeg, PoweredUp) BEGIN IF PoweredUp = '1' THEN --Hardware reset timing control IF falling_edge(RESETNeg) THEN current_state <= RESET; I2C_current_state <= IDLE; ELSE current_state <= next_state; I2C_current_state <= I2C_next_state; END IF; ELSE current_state <= RESET; I2C_current_state <= IDLE; END IF; END PROCESS StateTransition; ------------------------------------------------------------------------ -- Main Behavior Process -- combinational process for next state generation ------------------------------------------------------------------------ StateGen :PROCESS(RESETNeg, AV_PATTERN, HBLANK_in, HBURST_in, HSYNC_in, HSYNCNeg_zd, HSYNCNeg_in, BLANKNeg_in, BLANKNeg_zd) BEGIN IF RESETNeg /= '1' THEN next_state <= current_state; ELSE CASE current_state IS WHEN RESET => IF rising_edge(AV_PATTERN) THEN next_state <= ACTIVE_LINE; ELSIF(rising_edge(HSYNCNeg_in) AND MODE="110") OR (rising_edge(HSYNCNeg_zd) AND (MODE="001" OR MODE="111")) OR (falling_edge(HSYNCNeg_in) AND (MODE="010" OR MODE="100"))OR (falling_edge(HSYNCNeg_zd) AND (MODE="011" OR MODE="101")) THEN next_state <= HBLANK_SYNC; ELSE next_state <= RESET; END IF; WHEN ACTIVE_LINE => IF rising_edge(AV_PATTERN) OR (rising_edge(HSYNCNeg_in) AND MODE="110") OR (rising_edge(HSYNCNeg_zd) AND (MODE="001" OR MODE="111")) OR (falling_edge(HSYNCNeg_in) AND (MODE="010" OR MODE="100")) OR (falling_edge(HSYNCNeg_zd) AND (MODE="011" OR MODE="101")) THEN next_state <= HBLANK_SYNC; ELSE next_state <= ACTIVE_LINE; END IF; WHEN HBLANK_SYNC => IF rising_edge(HBLANK_in) THEN next_state <= HBLANK; ELSE next_state <= HBLANK_SYNC; END IF; WHEN HBLANK => IF rising_edge(AV_PATTERN) OR rising_edge(BLANKNeg_in) OR rising_edge(BLANKNeg_zd) THEN next_state <= ACTIVE_LINE; ELSIF rising_edge(HBURST_IN) THEN next_state <= HBLANK_BURST; ELSIF rising_edge(HSYNC_in) THEN next_state <= HBLANK_SYNC; ELSE next_state <= HBLANK; END IF; WHEN HBLANK_BURST => IF rising_edge(HBLANK_in) THEN next_state <= HBLANK; ELSE next_state <= HBLANK_BURST; END IF; END CASE; END IF; END PROCESS StateGen; ------------------------------------------------------------------------ --FSM Output generation and general functionality ------------------------------------------------------------------------ Functional : PROCESS(RESETNeg, current_state, CLOCK, HSYNCNeg_zd, HSYNCNeg_in) FUNCTION BURST(CNT: IN NATURAL; SubCarrier: STD_LOGIC_VECTOR(31 DOWNTO 0)) RETURN STD_LOGIC_VECTOR IS VARIABLE DELTA_F, Var_tmp: REAL:=0.0; BEGIN DELTA_F := 2.0*math_pi*REAL(to_nat(SubCarrier)/4)/REAL(2**30); Var_tmp := 52.0*sin(DELTA_F*REAL(CNT-336)+math_pi)+128.0; RETURN to_slv(INTEGER(Var_tmp),8); END FUNCTION BURST; BEGIN IF RESETNeg = '1' THEN CASE current_state IS WHEN RESET => HBLANK_SYNC_act <='0'; HSYNC_cnt := 0; Ysync := (OTHERS=>'0'); Uburst := (OTHERS=>'0'); Vburst := (OTHERS=>'0'); WHEN ACTIVE_LINE => HBLANK_SYNC_act <='0'; HSYNC_cnt := 0; Ysync := to_slv((to_nat(Yin)+SYNC_LUMA),9); Uburst := Uin; Vburst := Vin; WHEN HBLANK_SYNC => HBLANK_SYNC_act <='1'; HSYNC_cnt := HSYNC_cnt + 1; IF HSYNC_cnt=270 THEN HBLANK_in <= '1', '0' AFTER 1 ns; END IF; Ysync := (OTHERS=>'0'); -- HSync pulse Uburst := X"80"; Vburst := X"80"; WHEN HBLANK_BURST => HBLANK_SYNC_act <='0'; HSYNC_cnt := HSYNC_cnt + 1; IF HSYNC_cnt=456 THEN HBLANK_in <= '1', '0' AFTER 1 ns; END IF; Ysync := to_slv(SYNC_LUMA,9); -- Y HSync Blank value Uburst := BURST(HSYNC_cnt, REG_ARRAY(12)®_ARRAY(11)& REG_ARRAY(10)®_ARRAY(9)); Vburst := Uburst; WHEN HBLANK => HBLANK_SYNC_act <='0'; HSYNC_cnt := HSYNC_cnt + 1; IF (NOT VBLANK OR VBLANK_BURST) AND HSYNC_cnt=336 THEN HBURST_in <= '1', '0' AFTER 1 ns; ELSIF(VBLANK AND NOT VBLANK_BURST AND HSYNC_cnt=1992) OR (rising_edge(HSYNCNeg_zd) AND (MODE="001" OR MODE="101")) OR (rising_edge(HSYNCNeg_in) AND MODE="100" ) OR (falling_edge(HSYNCNeg_zd) AND (MODE="011" OR MODE="111")) OR (falling_edge(HSYNCNeg_in) AND (MODE="010" OR MODE="110")) THEN HSYNC_in <= '1', '0' AFTER 1 ns; HSYNC_cnt := 0; END IF; IF TTX_EN AND TTX='1' THEN -- Teletext Enabled Ysync:= to_slv(SYNC_LUMA+16#FF#,9); ELSE Ysync:= to_slv(SYNC_LUMA,9); -- Y HSync Blank value END IF; Uburst := X"80"; Vburst := X"80"; END CASE; END IF; END PROCESS Functional; ---------------------------------------------- --TTXREQ Enable Generator ---------------------------------------------- TTXREQ_Enable:PROCESS(HBLANK_SYNC_act) VARIABLE TTXREQ_ris, TTXREQ_fall : TIME; BEGIN TTXREQ_ris :=(48-to_nat(TTXREQ_R))*CLK_PERIOD + 10.2 us; TTXREQ_fall:=TTXREQ_ris+(1440-to_nat(TTXREQ_F))*CLK_PERIOD; IF rising_edge(HBLANK_SYNC_act) AND VBLANK_BURST THEN TTXREQ_EN <= '0', '1' AFTER TTXREQ_ris, '0' AFTER TTXREQ_fall; END IF; END PROCESS TTXREQ_Enable; ---------------------------------------------- --TTXREQ Generator ---------------------------------------------- TTXREQ_GEN:PROCESS(CLOCK, TTXREQ_EN) BEGIN IF REG_ARRAY(3)(6)='1' THEN IF rising_edge(TTXREQ_EN) THEN TTXREQ_zd <= '1'; TTXCnt:= 1; TTXCntAUX:= 0; ELSIF TTXREQ_EN='1' AND rising_edge(CLOCK) THEN CASE (TTXCnt MOD 38) IS WHEN 10 | 19 | 28 | 37 => IF TTXCntAUX<2 THEN TTXREQ_zd <= '0'; TTXCntAUX:= TTXCntAUX+1; ELSE TTXREQ_zd <= '1'; TTXCnt:= TTXCnt+1; TTXCntAUX:= 0; END IF; WHEN OTHERS => IF TTXCntAUX<3 THEN TTXREQ_zd <= '0'; TTXCntAUX:= TTXCntAUX+1; ELSE TTXREQ_zd <= '1'; TTXCnt:= TTXCnt+1; TTXCntAUX:= 0; END IF; END CASE; END IF; ELSE TTXREQ_zd <= TTXREQ_EN; END IF; END PROCESS TTXREQ_GEN; ---------------------------------------------- --HSYNCNeg and BLANKNeg Generator(Master Mode) ---------------------------------------------- VTG_HSYNC_BLANK:PROCESS(CLOCK) VARIABLE BlankLength, LineLength, FrameLength : NATURAL; VARIABLE BlankCycleLow, BlankCycleHigh, Cnt: NATURAL; VARIABLE HSYNC_pulse : TIME; BEGIN CASE REG_ARRAY(8)(1 DOWNTO 0) IS WHEN "00" => HSYNC_pulse := 1*CLK_PERIOD; WHEN "01" => HSYNC_pulse := 4*CLK_PERIOD; WHEN "10" => HSYNC_pulse := 16*CLK_PERIOD; WHEN "11" => HSYNC_pulse := 128*CLK_PERIOD; WHEN OTHERS => NULL; END CASE; HSYNC_pulse:= HSYNC_pulse + 1 ns; CASE STANDARD IS WHEN "00" | "10" => LastELine := 525; -- Last Active Line in Even Field FirstOLine := 21; -- First Active Line in Odd Field LastOLine := 262; -- Last Active Line in Odd Field FirstELine := 284; -- First Active Line in Even Field -- First Line with Burst in Odd Field during vertical retrace OBurstLine := 10; -- First Line with Burst in Even Field during vertical retrace EBurstLine := 273; BlankLength:= 276; LineLength := BlankLength + 1440; BlankCycleLow := LineLength-32; BlankCycleHigh:= 244; FrameLength := 525; WHEN "01" => LastELine := 624; -- Last Active Line in Even Field FirstOLine := 22; -- First Active Line in Odd Field LastOLine := 311; -- Last Active Line in Odd Field FirstELine := 335; -- First Active Line in Even Field -- First Line with Burst in Odd Field during vertical retrace OBurstLine := 7; -- First Line with Burst in Even Field during vertical retrace EBurstLine := 319; BlankLength := 288; LineLength := BlankLength + 1440; BlankCycleLow := LineLength-24; BlankCycleHigh:= 264; FrameLength := 625; WHEN OTHERS => NULL; END CASE; IF LineCnt>=LastELine OR LineCnt<=FirstOLine OR (LineCnt>=LastOLine AND LineCnt<=FirstELine) THEN VBLANK := TRUE; ELSE VBLANK := FALSE; END IF; IF (LineCnt>=OBurstLine AND LineCnt<=FirstOLine) OR (LineCnt>=EBurstLine AND LineCnt<=FirstELine) THEN VBLANK_BURST := TRUE; ELSE VBLANK_BURST := FALSE; END IF; -- Teletext Handling IF REG_ARRAY(3)(5)='1' THEN IF (LineCnt>=OBurstLine AND LineCnt<=FirstOLine) THEN -- Odd field TTXControl:= REG_ARRAY(16#13#)®_ARRAY(16#12#); IF TTXControl(LineCnt-OBurstLine)='1' THEN TTX_EN<= FALSE, TRUE AFTER 10.2 us; ELSE TTX_EN<= FALSE; END IF; ELSIF (LineCnt>=EBurstLine AND LineCnt -- Master Mode IF CLK_cnt0 THEN HSYNCNeg_zd <= '1'; ELSE HSYNCNeg_zd <= '0'; END IF; IF NOT VBLANK THEN BLANKNeg_zd <= '1'; ELSE BLANKNeg_zd <= '0'; END IF; CLK_cnt := (CLK_cnt + 1) MOD (LineLength + 1); WHEN "011" | "101" | "111" => -- Master Mode IF CLK_cnt=1 THEN HSYNCNeg_zd <= '0', '1' AFTER (HSYNC_pulse); END IF; IF NOT VBLANK THEN IF CLK_cnt=BlankCycleLow THEN BLANKNeg_zd <= '0'; ELSIF CLK_cnt=BlankCycleHigh THEN BLANKNeg_zd <= '1'; END IF; ELSE BLANKNeg_zd <= '0'; END IF; CLK_cnt := (CLK_cnt + 1) MOD (LineLength + 1); WHEN "000" => -- Slave Mode CLK_cnt := 0; HSYNCNeg_zd <= 'Z'; BLANKNeg_zd <= 'Z'; -- Start/End of Active Video Detection IF CREG(0)= X"FF" AND CREG(1)= X"00" AND CREG(2)= X"00" AND CREG(3)= X"00" THEN AV_PATTERN <= '1', '0' AFTER 1 ns; LineCnt := (LineCnt+1) MOD (2*FrameLength+1); -- there is a two AV_PATTERNs per line (SAV and EAV) -- so Line Counter must be halfed Cnt:= (LineCnt+1)/2; IF Cnt>=LastELine OR Cnt<=FirstOLine OR (Cnt>=LastOLine AND Cnt<=FirstELine) THEN VBLANK := TRUE; ELSE VBLANK := FALSE; END IF; IF (Cnt>=OBurstLine AND Cnt<=FirstOLine) OR (Cnt>=EBurstLine AND Cnt<=FirstELine) THEN VBLANK_BURST := TRUE; ELSE VBLANK_BURST := FALSE; END IF; END IF; WHEN "010" | "100" | "110" => -- Slave Mode CLK_cnt:= 0; HSYNCNeg_zd <= 'Z'; BLANKNeg_zd <= 'Z'; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS VTG_HSYNC_BLANK; ------------------------------- --VSYNCNeg Generator(Master Mode) ------------------------------- VTG_VSYNC:PROCESS(HSYNCNeg_zd, HSYNCNeg_in) VARIABLE VS_HS_delay, VSYNC_pulse, OddEvenDelay, EvenFieldDelay: TIME; VARIABLE OddLine, EvenLine, FrameLength : NATURAL; BEGIN CASE REG_ARRAY(8)(3 DOWNTO 2) IS WHEN "00" => VS_HS_delay := 0*CLK_PERIOD; WHEN "01" => VS_HS_delay := 4*CLK_PERIOD; WHEN "10" => VS_HS_delay := 8*CLK_PERIOD; WHEN "11" => VS_HS_delay := 16*CLK_PERIOD; WHEN OTHERS => NULL; END CASE; CASE REG_ARRAY(8)(5 DOWNTO 4) IS WHEN "00" => VSYNC_pulse := 1*CLK_PERIOD; WHEN "01" => VSYNC_pulse := 4*CLK_PERIOD; WHEN "10" => VSYNC_pulse := 16*CLK_PERIOD; WHEN "11" => VSYNC_pulse := 128*CLK_PERIOD; WHEN OTHERS => NULL; END CASE; CASE STANDARD IS WHEN "00" | "10" => OddLine := 4; EvenLine := 266; FrameLength := 526; OddEvenDelay := 864/2*CLK_PERIOD; WHEN "01" => OddLine := 1; EvenLine := 313; FrameLength := 626; OddEvenDelay := 858/2*CLK_PERIOD; WHEN OTHERS => NULL; END CASE; IF REG_ARRAY(8)(4)='1' THEN EvenFieldDelay := 32 us; ELSE EvenFieldDelay := 0 ns; END IF; CASE MODE IS WHEN "001" => IF rising_edge(HSYNCNeg_zd) THEN LineCnt := (LineCnt + 1) MOD FrameLength; IF (LineCnt>=OddLine AND LineCnt IF falling_edge(HSYNCNeg_zd) THEN LineCnt := (LineCnt + 1) MOD FrameLength; IF LineCnt=OddLine THEN VSYNCNeg_zd<='0' AFTER VS_HS_delay; ELSIF LineCnt=EvenLine THEN VSYNCNeg_zd<='1' AFTER (VS_HS_delay+EvenFieldDelay); END IF; END IF; WHEN "101" => IF falling_edge(HSYNCNeg_zd) THEN LineCnt := (LineCnt + 1) MOD FrameLength; IF LineCnt=OddLine THEN VSYNCNeg_zd <= '0' AFTER VS_HS_delay, '1' AFTER (VSYNC_pulse+VS_HS_delay); ELSIF LineCnt=EvenLine THEN VSYNCNeg_zd <= '0' AFTER (VS_HS_delay+OddEvenDelay), '1' AFTER (VSYNC_pulse+VS_HS_delay+OddEvenDelay); END IF; END IF; WHEN "111" => IF falling_edge(HSYNCNeg_zd) THEN LineCnt := (LineCnt + 1) MOD FrameLength; IF LineCnt=OddLine THEN VSYNCNeg_zd <= '1' AFTER VS_HS_delay; ELSIF LineCnt=EvenLine THEN VSYNCNeg_zd <= '0' AFTER VS_HS_delay; END IF; END IF; WHEN "000" | "010" | "100" | "110" => -- Slave mode IF rising_edge(HSYNCNeg_in) THEN LineCnt := (LineCnt + 1) MOD FrameLength; END IF; VSYNCNeg_zd <= 'Z'; WHEN OTHERS => NULL; END CASE; END PROCESS VTG_VSYNC; ------------------------------------------------------------------------ -- I2C FSM: combinational process for next state generation ------------------------------------------------------------------------ I2C_StateGen:PROCESS(RESETNeg, START, STOP, ACK_in, ACK_out) BEGIN IF RESETNeg /= '1' THEN I2C_next_state <= I2C_current_state; ELSE CASE I2C_current_state IS WHEN IDLE => IF rising_edge(START) THEN I2C_next_state <= ADDR_LATCH; END IF; WHEN ADDR_ACK => IF rising_edge(STOP) THEN I2C_next_state <= IDLE; ELSIF rising_edge(ACK_out) AND ACK='0' THEN IF I2C_data(0)='0' THEN I2C_next_state <= SUBADDR_LATCH; ELSIF I2C_data(0)='1' THEN I2C_next_state <= READ; END IF; END IF; WHEN ADDR_LATCH => IF rising_edge(STOP) THEN I2C_next_state <= IDLE; ELSIF rising_edge(ACK_in) THEN I2C_next_state <= ADDR_ACK; ELSE I2C_next_state <= ADDR_LATCH; END IF; WHEN SUBADDR_LATCH => IF rising_edge(STOP) THEN I2C_next_state <= IDLE; ELSIF rising_edge(ACK_in) THEN I2C_next_state <= SUBADDR_ACK; ELSE I2C_next_state <= SUBADDR_LATCH; END IF; WHEN SUBADDR_ACK => IF rising_edge(STOP) THEN I2C_next_state <= IDLE; ELSIF rising_edge(ACK_out) AND ACK='0' THEN I2C_next_state <= WRITE; END IF; WHEN READ => IF rising_edge(STOP) THEN I2C_next_state <= IDLE; ELSIF rising_edge(ACK_in) THEN I2C_next_state <= READ_ACK; ELSE I2C_next_state <= READ; END IF; WHEN READ_ACK => IF rising_edge(STOP) THEN I2C_next_state <= IDLE; ELSIF rising_edge(ACK_out) THEN IF ACK='0' THEN I2C_next_state <= READ; ELSE I2C_next_state <= IDLE; END IF; END IF; WHEN WRITE => IF rising_edge(STOP) THEN I2C_next_state <= IDLE; ELSIF rising_edge(START)THEN I2C_next_state <= ADDR_LATCH; ELSIF rising_edge(ACK_in) THEN I2C_next_state <= WRITE_ACK; ELSE I2C_next_state <= WRITE; END IF; WHEN WRITE_ACK => IF rising_edge(STOP) THEN I2C_next_state <= IDLE; ELSIF rising_edge(ACK_out) AND ACK='0' THEN I2C_next_state <= WRITE; END IF; END CASE; END IF; END PROCESS I2C_StateGen; ------------------------------------------------------------------------ --I2C FSM: Output generation and general functionality ------------------------------------------------------------------------ I2C_Functional : PROCESS(RESETNeg, I2C_current_state, SCLOCK, START) BEGIN IF RESETNeg = '1' THEN CASE I2C_current_state IS WHEN IDLE => ADDR_cnt := 8; ACK <= '1'; ACK_in <= '0'; ACK_out <= '0'; SDATA_zd <= 'Z'; WHEN ADDR_ACK | SUBADDR_ACK | WRITE_ACK => IF falling_edge(SCLOCK) THEN -- Acknowledge terminates SDATA_zd <= 'Z' AFTER 100 ns; ACK_out <= '1' AFTER 200 ns, '0' AFTER 201 ns; ELSE SDATA_zd <= ACK; -- Acknowledge bit ADDR_cnt := 8; END IF; WHEN READ_ACK => SDATA_zd <= 'Z'; ADDR_cnt := 8; IF rising_edge(SCLOCK) THEN ACK <= SDATA_in; ELSIF falling_edge(SCLOCK) THEN -- Acknowledge terminates SDATA_zd <= '1' AFTER 100 ns; ACK_out <= '1' AFTER 200 ns, '0' AFTER 201 ns; END IF; WHEN ADDR_LATCH => IF rising_edge(SCLOCK) THEN SDATA_zd <= 'Z'; IF ADDR_cnt>0 THEN I2C_data(ADDR_cnt-1) := SDATA_in; ADDR_cnt := ADDR_cnt - 1; END IF; ELSIF falling_edge(SCLOCK) THEN IF ADDR_cnt=0 THEN IF I2C_data(7 DOWNTO 2)=DEVICE_ADDR THEN ACK <= '0'; ELSE ACK <= '1'; END IF; ACK_in <= '1' AFTER 200 ns, '0' AFTER 201 ns; END IF; END IF; WHEN SUBADDR_LATCH => ACK <= '1'; ACK_in <= '0'; IF rising_edge(SCLOCK) THEN SDATA_zd <= 'Z'; IF ADDR_cnt>0 THEN I2C_data(ADDR_cnt-1) := SDATA_in; ADDR_cnt := ADDR_cnt - 1; END IF; ELSIF falling_edge(SCLOCK) THEN IF ADDR_cnt=0 THEN IF I2C_data(7 DOWNTO 0)>to_slv(47,7) THEN -- Invalid register address ACK <= '1'; ELSE ACK <= '0'; REG_ADDR:=to_nat(I2C_data(7 DOWNTO 0)); END IF; ACK_in <= '1' AFTER 200 ns, '0' AFTER 201 ns; END IF; END IF; WHEN READ => ACK <= '1'; ACK_in <= '0'; IF rising_edge(SCLOCK) THEN IF ADDR_cnt>0 THEN IF REG_ADDR<48 THEN SDATA_zd <= REG_ARRAY(REG_ADDR)(ADDR_cnt-1); END IF; ADDR_cnt := ADDR_cnt - 1; END IF; ELSIF falling_edge(SCLOCK) THEN IF ADDR_cnt=0 THEN ACK <= '0'; ACK_in <= '1' AFTER 200 ns, '0' AFTER 201 ns; SDATA_zd <= 'Z' AFTER 100 ns; REG_ADDR := REG_ADDR + 1; END IF; END IF; WHEN WRITE => ACK <= '1'; ACK_in <= '0'; SDATA_zd <= 'Z'; IF rising_edge(SCLOCK) THEN IF ADDR_cnt>0 THEN I2C_data(ADDR_cnt-1) := SDATA_in; ADDR_cnt := ADDR_cnt - 1; END IF; ELSIF falling_edge(SCLOCK) THEN IF ADDR_cnt=0 THEN ACK <= '0'; REG_ARRAY(REG_ADDR) := I2C_data; REG_ADDR := REG_ADDR + 1; ACK_in <= '1' AFTER 200 ns, '0' AFTER 201 ns; END IF; END IF; IF rising_edge(START) THEN ADDR_cnt := 8; END IF; END CASE; END IF; END PROCESS I2C_Functional; ------------------------- -- I2C START/STOP Detection ------------------------- Trigger_Process: PROCESS(SDATA_in) BEGIN IF SCLOCK='1' THEN IF falling_edge(SDATA_in) THEN START <= '1', '0' AFTER 1 ns; ELSIF SDATA_in'EVENT AND SDATA_in='1' AND SDATA_zd'LAST_EVENT/= 0 ns THEN STOP <= '1', '0' AFTER 1 ns; END IF; ELSE START <= '0'; STOP <= '0'; END IF; END PROCESS; ---------------------------------- -- Filer Process ---------------------------------- FILT_Process: PROCESS(CLOCK, RESETNeg) VARIABLE Y_slv_tmp, Cb_slv_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); VARIABLE Cr_slv_tmp : STD_LOGIC_VECTOR(7 DOWNTO 0); VARIABLE Y_tmp, U_tmp, V_tmp : REAL:=0.0; VARIABLE CHROMA_tmp : REAL:=0.0; VARIABLE Yf, Uf, Vf : STD_LOGIC_VECTOR(9 DOWNTO 0); VARIABLE R, G, B, CVSB, C : STD_LOGIC_VECTOR(9 DOWNTO 0); VARIABLE LCOEF : COEF_TYPE; VARIABLE CCOEF : COEF_TYPE; VARIABLE N : POSITIVE; FUNCTION SLV(Var : IN REAL; N : IN NATURAL) RETURN STD_LOGIC_VECTOR IS VARIABLE tmp_slv: STD_LOGIC_VECTOR(N-1 DOWNTO 0); VARIABLE Var_tmp: REAL:=0.0; BEGIN Var_tmp:= Var; IF Var_tmp < 0.0 THEN Var_tmp:= 0.0; END IF; tmp_slv := to_slv(INTEGER(Var_tmp),N); RETURN tmp_slv; END FUNCTION SLV; PROCEDURE YCbCr2YUV( Y : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Cb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); U : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); V : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)) IS VARIABLE U_real, V_real : REAL:=0.0; BEGIN U_real := 0.8738*(REAL(to_nat(Cb))) - 0.11*(REAL(to_nat(Cr))); V_real := 1.23*(REAL(to_nat(Cr))); U := SLV(U_real,8); V := SLV(V_real,8); END PROCEDURE YCbCr2YUV; PROCEDURE FILTER_INIT( N : OUT POSITIVE; LCOEF : OUT COEF_TYPE; CCOEF : OUT COEF_TYPE; DELTA_F : OUT REAL) IS VARIABLE LFILT, CFILT, NL, NC, int_tmp: INTEGER:=0; VARIABLE LCOEF_tmp, CCOEF_tmp: COEF_TYPE:=(OTHERS=>0.0); VARIABLE SubCarrier : STD_LOGIC_VECTOR(31 DOWNTO 0); VARIABLE tmp_real : REAL; BEGIN LFILT := to_nat(REG_ARRAY(0)(7 DOWNTO 5)); CFILT := to_nat(REG_ARRAY(0)(4 DOWNTO 2)); NL := N_LUMA(LFILT); NC := N_CHROMA(CFILT); LCOEF_tmp := COEF_LUMA(LFILT); CCOEF_tmp := COEF_CHROMA(CFILT); IF NL>NC THEN FOR I IN NL DOWNTO NL-NC LOOP CCOEF_tmp(I):=CCOEF_tmp(I-(NL-NC)); END LOOP; FOR I IN 0 TO NL-NC-1 LOOP CCOEF_tmp(I):=0.0; END LOOP; N := NL; ELSIF NC>NL THEN FOR I IN NC DOWNTO NC-NL LOOP LCOEF_tmp(I):=LCOEF_tmp(I-(NC-NL)); END LOOP; FOR I IN 0 TO NC-NL-1 LOOP LCOEF_tmp(I):=0.0; END LOOP; N := NC; END IF; LCOEF:= LCOEF_tmp; CCOEF:= CCOEF_tmp; SubCarrier := REG_ARRAY(12)®_ARRAY(11)®_ARRAY(10)®_ARRAY(9); tmp_real := REAL(to_nat(SubCarrier)/2)/REAL(2**31); DELTA_F:= 2.0*math_pi*tmp_real; END PROCEDURE FILTER_INIT; PROCEDURE YUV2RGB( Y : IN STD_LOGIC_VECTOR(9 DOWNTO 0); U : IN STD_LOGIC_VECTOR(9 DOWNTO 0); V : IN STD_LOGIC_VECTOR(9 DOWNTO 0); R : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); G : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); B : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)) IS VARIABLE Y_tmp, U_tmp, V_tmp : REAL; VARIABLE R_tmp, G_tmp, B_tmp : REAL; BEGIN Y_tmp := REAL(to_nat(Y)); U_tmp := REAL(to_nat(U)); V_tmp := REAL(to_nat(V)); R_tmp := Y_tmp + 1.140*V_tmp; G_tmp := Y_tmp - 0.395*U_tmp - 0.581*V_tmp; B_tmp := Y_tmp + 2.032*U_tmp; R := SLV(R_tmp,10); G := SLV(G_tmp,10); B := SLV(B_tmp,10); END PROCEDURE YUV2RGB; BEGIN IF RESETNeg='1' THEN IF rising_edge(CLOCK) THEN -- DMX Input signals CREG(d_cnt):=P; CASE d_cnt IS WHEN 0 => Cb_slv_tmp:=P; WHEN 1 | 3 => IF (Cb_slv_tmp>X"00" AND Cb_slv_tmpX"00" AND Cr_slv_tmpX"00" AND Y_slv_tmp Cr_slv_tmp:=P; END CASE; d_cnt :=(d_cnt + 1) MOD 4; -- Initialize Filter Coeffitients FILTER_INIT(N, LCOEF, CCOEF, DELTA_F); -- Shift inputs FOR I IN N DOWNTO 1 LOOP Y_filt(I):= Y_filt(I-1); U_filt(I):= U_filt(I-1); V_filt(I):= V_filt(I-1); END LOOP; Y_filt(0):= to_nat(Ysync); U_filt(0):= to_nat(Uburst); V_filt(0):= to_nat(Vburst); -- Filtering FOR I IN 0 TO N LOOP Y_tmp:= Y_tmp + LCOEF(I)*(REAL(Y_filt(I))); U_tmp:= U_tmp + CCOEF(I)*(REAL(U_filt(I))); V_tmp:= V_tmp + CCOEF(I)*(REAL(V_filt(I))); END LOOP; Yf := SLV(Y_tmp,10); Uf := SLV(U_tmp,10); Vf := SLV(V_tmp,10); -- Subcarrier phase alpha:= cos(2.0*math_pi*REAL(to_nat(REG_ARRAY(16#0D#)))/360.0); -- Chrominance component generation CHROMA_tmp := (REAL(to_nat(Uf)))*sin(DELTA_F*(REAL(Chr_cnt))+alpha) + (REAL(to_nat(Vf)))*cos(DELTA_F*(REAL(Chr_cnt))+alpha); C := SLV(CHROMA_tmp,10); Chr_cnt:= Chr_cnt+1; -- Composite video signal generation CVSB := SLV((Y_tmp + CHROMA_tmp),10); -- YUV to RGB YUV2RGB(Yf, Uf, Vf, R, G, B); -- DACA MUX IF REG_ARRAY(3)(3)='0' AND REG_ARRAY(3)(4)='0' THEN DACA := CVSB; ELSIF REG_ARRAY(3)(3)='0' AND REG_ARRAY(3)(4)='1' THEN DACA := C; ELSIF REG_ARRAY(3)(3)='1' AND REG_ARRAY(4)(0)='1' AND REG_ARRAY(4)(1)='0' THEN DACA := G; ELSIF REG_ARRAY(3)(3)='1' AND (REG_ARRAY(4)(0)='0' OR REG_ARRAY(4)(1)='1') THEN DACA := Yf; END IF; -- DACB, DACC MUX IF REG_ARRAY(4)(0)='0' THEN DACB := CVSB; DACC := C; ELSIF REG_ARRAY(4)(1)='0' THEN DACB := B; DACC := R; ELSE DACB := Uf;--Pb DACC := Vf;--Pr END IF; dacvalA <= to_nat(DACA); dacvalB <= to_nat(DACB); dacvalC <= to_nat(DACC); END IF; ELSE d_cnt := 0; Y_slv_tmp := X"00"; Cb_slv_tmp := X"00"; Cr_slv_tmp := X"00"; Y_filt := (OTHERS=>0); U_filt := (OTHERS=>0); V_filt := (OTHERS=>0); CLK_cnt:= 0; END IF; END PROCESS FILT_Process; ------------------------------------------------------------------------ -- Output generation ------------------------------------------------------------------------ SDATA_out <= SDATA_zd; OUTA_zd <= (REAL(dacvalA) * Vref/REAL(2**resolution)); OUTB_zd <= (REAL(dacvalB) * Vref/REAL(2**resolution)); OUTC_zd <= (REAL(dacvalC) * Vref/REAL(2**resolution)); OUTA <= OUTA_zd WHEN REG_ARRAY(1)(6)='0' ELSE 0.0; OUTB <= OUTB_zd WHEN REG_ARRAY(1)(5)='0' ELSE 0.0; OUTC <= OUTC_zd WHEN REG_ARRAY(1)(3)='0' ELSE 0.0; HSYNCNeg_output: PROCESS(HSYNCNeg_zd) VARIABLE H_GlitchData : VitalGlitchDataType; VARIABLE HSYNCNeg_t : std_logic; BEGIN IF REG_ARRAY(7)(0) = '1' THEN HSYNCNeg_t := HSYNCNeg_zd; ELSE HSYNCNeg_t := 'Z'; END IF; VitalPathDelay01Z( OutSignal => HSYNCNeg_tmp, OutSignalName => "HSYNCNeg", OutTemp => HSYNCNeg_t, Mode => VitalTransport, GlitchData => H_GlitchData, Paths => ( 0 => (InputChangeTime => CLOCK'LAST_EVENT, PathDelay => tpd_CLOCK_HSYNCNeg, PathCondition => TRUE)) ); END PROCESS HSYNCNeg_output; HSYNCNeg_out <= HSYNCNeg_tmp; VSYNCNeg_output: PROCESS(VSYNCNeg_zd) VARIABLE V_GlitchData : VitalGlitchDataType; VARIABLE VSYNCNeg_t : std_logic; BEGIN IF REG_ARRAY(7)(0) = '1' THEN VSYNCNeg_t := VSYNCNeg_zd; ELSE VSYNCNeg_t := 'Z'; END IF; VitalPathDelay01Z( OutSignal => VSYNCNeg_tmp, OutSignalName => "VSYNCNeg", OutTemp => VSYNCNeg_t, Mode => VitalTransport, GlitchData => V_GlitchData, Paths => ( 0 => (InputChangeTime => CLOCK'LAST_EVENT, PathDelay => tpd_CLOCK_HSYNCNeg, PathCondition => TRUE)) ); END PROCESS VSYNCNeg_output; VSYNCNeg_out <= VSYNCNeg_tmp; BLANKNeg_output: PROCESS(BLANKNeg_zd) VARIABLE B_GlitchData : VitalGlitchDataType; VARIABLE BLANKNeg_t : std_logic; BEGIN IF REG_ARRAY(7)(0) = '1' THEN BLANKNeg_t := BLANKNeg_zd; ELSE BLANKNeg_t := 'Z'; END IF; VitalPathDelay01Z( OutSignal => BLANKNeg_tmp, OutSignalName => "BLANKNeg", OutTemp => BLANKNeg_t, Mode => VitalTransport, GlitchData => B_GlitchData, Paths => ( 0 => (InputChangeTime => CLOCK'LAST_EVENT, PathDelay => tpd_CLOCK_HSYNCNeg, PathCondition => TRUE)) ); END PROCESS BLANKNeg_output; BLANKNeg_out <= BLANKNeg_tmp; TTXREQ_output: PROCESS(TTXREQ_zd) VARIABLE T_GlitchData : VitalGlitchDataType; VARIABLE TTXREQ_t : std_logic; BEGIN IF REG_ARRAY(3)(5) = '1' THEN TTXREQ_t := TTXREQ_zd; ELSE TTXREQ_t := 'Z'; END IF; VitalPathDelay01Z( OutSignal => TTXREQ, OutSignalName => "TTXREQ", OutTemp => TTXREQ_t, Mode => VitalTransport, GlitchData => T_GlitchData, Paths => ( 0 => (InputChangeTime => CLOCK'LAST_EVENT, PathDelay => tpd_CLOCK_TTXREQ, PathCondition => TRUE)) ); END PROCESS TTXREQ_output; ---------------------------------- -- Default Process ---------------------------------- default: PROCESS BEGIN -- Power Up Register Configuration REG_ARRAY(0) := X"00"; REG_ARRAY(1) := X"58"; REG_ARRAY(2) := X"00"; REG_ARRAY(3) := X"00"; REG_ARRAY(4) := X"10"; REG_ARRAY(5) := X"00"; REG_ARRAY(6) := X"00"; REG_ARRAY(7) := X"00"; REG_ARRAY(8) := X"00"; REG_ARRAY(9) := X"16"; REG_ARRAY(10):= X"7C"; REG_ARRAY(11):= X"F0"; REG_ARRAY(12):= X"21"; REG_ARRAY(13):= X"00"; REG_ARRAY(14):= X"00"; REG_ARRAY(15):= X"00"; REG_ARRAY(16):= X"00"; REG_ARRAY(17):= X"00"; REG_ARRAY(18):= X"00"; REG_ARRAY(19):= X"00"; REG_ARRAY(20):= X"00"; REG_ARRAY(21):= X"00"; REG_ARRAY(22):= X"00"; REG_ARRAY(23):= X"00"; REG_ARRAY(24):= X"00"; REG_ARRAY(25):= X"00"; REG_ARRAY(26):= X"00"; REG_ARRAY(27):= X"00"; REG_ARRAY(28):= X"00"; REG_ARRAY(29):= X"00"; REG_ARRAY(30):= X"00"; REG_ARRAY(31):= X"00"; REG_ARRAY(32):= X"00"; REG_ARRAY(33):= X"00"; REG_ARRAY(34):= X"00"; REG_ARRAY(35):= X"00"; REG_ARRAY(36):= X"00"; REG_ARRAY(37):= X"00"; REG_ARRAY(38):= X"00"; REG_ARRAY(39):= X"00"; REG_ARRAY(40):= X"00"; REG_ARRAY(41):= X"00"; REG_ARRAY(42):= X"00"; REG_ARRAY(43):= X"00"; REG_ARRAY(44):= X"00"; REG_ARRAY(45):= X"00"; REG_ARRAY(46):= X"00"; REG_ARRAY(47):= X"00"; --------------------------------- -- Luminance Filter Order --------------------------------- N_LUMA(0) := 21; N_LUMA(1) := 22; N_LUMA(2) := 54; N_LUMA(3) := 50; N_LUMA(4) := 45; N_LUMA(5) := 21; N_LUMA(6) := 12; --------------------------------- -- Luminance Filter Coeffitients --------------------------------- -- Low-Pass NTSC COEF_LUMA(0)(0) := 0.002628824623207; COEF_LUMA(0)(1) := -0.002220969277835; COEF_LUMA(0)(2) := -0.012030444164183; COEF_LUMA(0)(3) := -0.007250226632218; COEF_LUMA(0)(4) := 0.019850527341606; COEF_LUMA(0)(5) := 0.029667873424797; COEF_LUMA(0)(6) := -0.018997209258561; COEF_LUMA(0)(7) := -0.075675666817133; COEF_LUMA(0)(8) := -0.016925212026626; COEF_LUMA(0)(9) := 0.189112869966653; COEF_LUMA(0)(10) := 0.387773631938108; COEF_LUMA(0)(11) := 0.387773631938108; COEF_LUMA(0)(12) := 0.189112869966653; COEF_LUMA(0)(13) := -0.016925212026626; COEF_LUMA(0)(14) := -0.075675666817133; COEF_LUMA(0)(15) := -0.018997209258561; COEF_LUMA(0)(16) := 0.029667873424797; COEF_LUMA(0)(17) := 0.019850527341606; COEF_LUMA(0)(18) := -0.007250226632218; COEF_LUMA(0)(19) := -0.012030444164183; COEF_LUMA(0)(20) := -0.002220969277835; COEF_LUMA(0)(21) := 0.002628824623207; -- Low-Pass PAL COEF_LUMA(1)(0) := 0.003147619132957; COEF_LUMA(1)(1) := 0.007735344553024; COEF_LUMA(1)(2) := 0.000704214046275; COEF_LUMA(1)(3) := -0.015528016162325; COEF_LUMA(1)(4) := -0.009993405522270; COEF_LUMA(1)(5) := 0.026546400384871; COEF_LUMA(1)(6) := 0.032285437753010; COEF_LUMA(1)(7) := -0.037506283181799; COEF_LUMA(1)(8) := -0.084423461160340; COEF_LUMA(1)(9) := 0.045726377913258; COEF_LUMA(1)(10) := 0.310532625101572; COEF_LUMA(1)(11) := 0.451268881597496; COEF_LUMA(1)(12) := 0.310532625101572; COEF_LUMA(1)(13) := 0.045726377913258; COEF_LUMA(1)(14) := -0.084423461160340; COEF_LUMA(1)(15) := -0.037506283181799; COEF_LUMA(1)(16) := 0.032285437753010; COEF_LUMA(1)(17) := 0.026546400384871; COEF_LUMA(1)(18) := -0.009993405522270; COEF_LUMA(1)(19) := -0.015528016162325; COEF_LUMA(1)(20) := 0.000704214046275; COEF_LUMA(1)(21) := 0.007735344553024; COEF_LUMA(1)(22) := 0.003147619132957; -- Notch NTSC COEF_LUMA(2)(0) := 0.000513530244839; COEF_LUMA(2)(1) := 0.000526390372827; COEF_LUMA(2)(2) := -0.000979139694666; COEF_LUMA(2)(3) := -0.000410899162044; COEF_LUMA(2)(4) := 0.001780119987020; COEF_LUMA(2)(5) := 0.000145839767996; COEF_LUMA(2)(6) := -0.003007871634237; COEF_LUMA(2)(7) := 0.000837359289079; COEF_LUMA(2)(8) := 0.004339775511970; COEF_LUMA(2)(9) := -0.002748487612157; COEF_LUMA(2)(10) := -0.005493871397935; COEF_LUMA(2)(11) := 0.005901221172047; COEF_LUMA(2)(12) := 0.005867877083064; COEF_LUMA(2)(13) := -0.010398551136743; COEF_LUMA(2)(14) := -0.004700313431359; COEF_LUMA(2)(15) := 0.016168537855106; COEF_LUMA(2)(16) := 0.000996271265860; COEF_LUMA(2)(17) := -0.022873065163034; COEF_LUMA(2)(18) := 0.006525448101508; COEF_LUMA(2)(19) := 0.029943224853548; COEF_LUMA(2)(20) := -0.019863029771262; COEF_LUMA(2)(21) := -0.036638196402791; COEF_LUMA(2)(22) := 0.043442742238313; COEF_LUMA(2)(23) := 0.042162116761687; COEF_LUMA(2)(24) := -0.093130721070173; COEF_LUMA(2)(25) := -0.045806024700724; COEF_LUMA(2)(26) := 0.313837898539408; COEF_LUMA(2)(27) := 0.547078955102741; COEF_LUMA(2)(28) := 0.313837898539408; COEF_LUMA(2)(29) := -0.045806024700724; COEF_LUMA(2)(30) := -0.093130721070173; COEF_LUMA(2)(31) := 0.042162116761687; COEF_LUMA(2)(32) := 0.043442742238313; COEF_LUMA(2)(33) := -0.036638196402791; COEF_LUMA(2)(34) := -0.019863029771262; COEF_LUMA(2)(35) := 0.029943224853548; COEF_LUMA(2)(36) := 0.006525448101508; COEF_LUMA(2)(37) := -0.022873065163034; COEF_LUMA(2)(38) := 0.000996271265860; COEF_LUMA(2)(39) := 0.016168537855106; COEF_LUMA(2)(40) := -0.004700313431359; COEF_LUMA(2)(41) := -0.010398551136743; COEF_LUMA(2)(42) := 0.005867877083064; COEF_LUMA(2)(43) := 0.005901221172047; COEF_LUMA(2)(44) := -0.005493871397935; COEF_LUMA(2)(45) := -0.002748487612157; COEF_LUMA(2)(46) := 0.004339775511970; COEF_LUMA(2)(47) := 0.000837359289079; COEF_LUMA(2)(48) := -0.003007871634237; COEF_LUMA(2)(49) := 0.000145839767996; COEF_LUMA(2)(50) := 0.001780119987020; COEF_LUMA(2)(51) := -0.000410899162044; COEF_LUMA(2)(52) := -0.000979139694666; COEF_LUMA(2)(53) := 0.000526390372827; COEF_LUMA(2)(54) := 0.000513530244839; -- Notch PAL COEF_LUMA(3)(0) := 0.001122956565695; COEF_LUMA(3)(1) := 0.002783401365579; COEF_LUMA(3)(2) := 0.000486978140414; COEF_LUMA(3)(3) := -0.002833093876437; COEF_LUMA(3)(4) := -0.000193653769925; COEF_LUMA(3)(5) := 0.004302093807851; COEF_LUMA(3)(6) := -0.000411302989207; COEF_LUMA(3)(7) := -0.006223060333062; COEF_LUMA(3)(8) := 0.001574584601330; COEF_LUMA(3)(9) := 0.008607289711253; COEF_LUMA(3)(10) := -0.003676714021736; COEF_LUMA(3)(11) := -0.011362964049129; COEF_LUMA(3)(12) := 0.007096735549183; COEF_LUMA(3)(13) := 0.014374308702031; COEF_LUMA(3)(14) := -0.012379696747861; COEF_LUMA(3)(15) := -0.017461614794737; COEF_LUMA(3)(16) := 0.020392450648779; COEF_LUMA(3)(17) := 0.020418770331952; COEF_LUMA(3)(18) := -0.032840327338366; COEF_LUMA(3)(19) := -0.023024116293046; COEF_LUMA(3)(20) := 0.054067104959899; COEF_LUMA(3)(21) := 0.025064923028126; COEF_LUMA(3)(22) := -0.100104752778464; COEF_LUMA(3)(23) := -0.026366792018769; COEF_LUMA(3)(24) := 0.316268856689536; COEF_LUMA(3)(25) := 0.526814461024176; COEF_LUMA(3)(26) := 0.316268856689536; COEF_LUMA(3)(27) := -0.026366792018769; COEF_LUMA(3)(28) := -0.100104752778464; COEF_LUMA(3)(29) := 0.025064923028126; COEF_LUMA(3)(30) := 0.054067104959899; COEF_LUMA(3)(31) := -0.023024116293046; COEF_LUMA(3)(32) := -0.032840327338366; COEF_LUMA(3)(33) := 0.020418770331952; COEF_LUMA(3)(34) := 0.020392450648779; COEF_LUMA(3)(35) := -0.017461614794737; COEF_LUMA(3)(36) := -0.012379696747861; COEF_LUMA(3)(37) := 0.014374308702031; COEF_LUMA(3)(38) := 0.007096735549183; COEF_LUMA(3)(39) := -0.011362964049129; COEF_LUMA(3)(40) := -0.003676714021736; COEF_LUMA(3)(41) := 0.008607289711253; COEF_LUMA(3)(42) := 0.001574584601330; COEF_LUMA(3)(43) := -0.006223060333062; COEF_LUMA(3)(44) := -0.000411302989207; COEF_LUMA(3)(45) := 0.004302093807851; COEF_LUMA(3)(46) := -0.000193653769925; COEF_LUMA(3)(47) := -0.002833093876437; COEF_LUMA(3)(48) := 0.000486978140414; COEF_LUMA(3)(49) := 0.002783401365579; COEF_LUMA(3)(50) := 0.001122956565695; -- Extended(SSAF) COEF_LUMA(4)(0) := -0.001547623581622; COEF_LUMA(4)(1) := -0.001175324095357; COEF_LUMA(4)(2) := 0.002073682933071; COEF_LUMA(4)(3) := 0.001421243242640; COEF_LUMA(4)(4) := -0.003582854905636; COEF_LUMA(4)(5) := -0.001895022661430; COEF_LUMA(4)(6) := 0.006006695616578; COEF_LUMA(4)(7) := 0.001957287530005; COEF_LUMA(4)(8) := -0.009263448731182; COEF_LUMA(4)(9) := -0.001555802742656; COEF_LUMA(4)(10) := 0.013826524084055; COEF_LUMA(4)(11) := 0.000037708009116; COEF_LUMA(4)(12) := -0.019812086721813; COEF_LUMA(4)(13) := 0.003062560963978; COEF_LUMA(4)(14) := 0.027967955990882; COEF_LUMA(4)(15) := -0.009035422260302; COEF_LUMA(4)(16) := -0.039498189420033; COEF_LUMA(4)(17) := 0.020277871483486; COEF_LUMA(4)(18) := 0.058448312080876; COEF_LUMA(4)(19) := -0.044816611261054; COEF_LUMA(4)(20) := -0.101897039908930; COEF_LUMA(4)(21) := 0.132463518718819; COEF_LUMA(4)(22) := 0.465151248875847; COEF_LUMA(4)(23) := 0.465151248875847; COEF_LUMA(4)(24) := 0.132463518718819; COEF_LUMA(4)(25) := -0.101897039908930; COEF_LUMA(4)(26) := -0.044816611261054; COEF_LUMA(4)(27) := 0.058448312080876; COEF_LUMA(4)(28) := 0.020277871483486; COEF_LUMA(4)(29) := -0.039498189420033; COEF_LUMA(4)(30) := -0.009035422260302; COEF_LUMA(4)(31) := 0.027967955990882; COEF_LUMA(4)(32) := 0.003062560963978; COEF_LUMA(4)(33) := -0.019812086721813; COEF_LUMA(4)(34) := 0.000037708009116; COEF_LUMA(4)(35) := 0.013826524084055; COEF_LUMA(4)(36) := -0.001555802742656; COEF_LUMA(4)(37) := -0.009263448731182; COEF_LUMA(4)(38) := 0.001957287530005; COEF_LUMA(4)(39) := 0.006006695616578; COEF_LUMA(4)(40) := -0.001895022661430; COEF_LUMA(4)(41) := -0.003582854905636; COEF_LUMA(4)(42) := 0.001421243242640; COEF_LUMA(4)(43) := 0.002073682933071; COEF_LUMA(4)(44) := -0.001175324095357; COEF_LUMA(4)(45) := -0.001547623581622; -- CIF COEF_LUMA(5)(0) := -0.000719998104291; COEF_LUMA(5)(1) := -0.004338805634890; COEF_LUMA(5)(2) := -0.003149201212884; COEF_LUMA(5)(3) := 0.008737966719944; COEF_LUMA(5)(4) := 0.019895633988800; COEF_LUMA(5)(5) := 0.003289773489902; COEF_LUMA(5)(6) := -0.041678087229050; COEF_LUMA(5)(7) := -0.057570854086815; COEF_LUMA(5)(8) := 0.026497265746452; COEF_LUMA(5)(9) := 0.200464329188177; COEF_LUMA(5)(10) := 0.347892188681230; COEF_LUMA(5)(11) := 0.347892188681230; COEF_LUMA(5)(12) := 0.200464329188177; COEF_LUMA(5)(13) := 0.026497265746452; COEF_LUMA(5)(14) := -0.057570854086815; COEF_LUMA(5)(15) := -0.041678087229050; COEF_LUMA(5)(16) := 0.003289773489902; COEF_LUMA(5)(17) := 0.019895633988800; COEF_LUMA(5)(18) := 0.008737966719944; COEF_LUMA(5)(19) := -0.003149201212884; COEF_LUMA(5)(20) := -0.004338805634890; COEF_LUMA(5)(21) := -0.000719998104291; -- QCIF COEF_LUMA(6)(0) := 0.001937576756200; COEF_LUMA(6)(1) := -0.015602918645651; COEF_LUMA(6)(2) := -0.032882526279072; COEF_LUMA(6)(3) := -0.000694655060374; COEF_LUMA(6)(4) := 0.115388125781478; COEF_LUMA(6)(5) := 0.264149129463121; COEF_LUMA(6)(6) := 0.333567285025970; COEF_LUMA(6)(7) := 0.264149129463121; COEF_LUMA(6)(8) := 0.115388125781478; COEF_LUMA(6)(9) := -0.000694655060374; COEF_LUMA(6)(10) := -0.032882526279072; COEF_LUMA(6)(11) := -0.015602918645651; COEF_LUMA(6)(12) := 0.001937576756200; --------------------------------- -- Chrominance Filter Order --------------------------------- N_CHROMA(0) := 38; N_CHROMA(1) := 24; N_CHROMA(2) := 24; N_CHROMA(3) := 21; N_CHROMA(4) := 1; N_CHROMA(5) := 27; N_CHROMA(6) := 18; --------------------------------- -- Chrominance Filter Coeffitients --------------------------------- -- 1.3MHz Low-Pass COEF_CHROMA(0)(0) := -0.003722043470114; COEF_CHROMA(0)(1) := 0.001159309335875; COEF_CHROMA(0)(2) := 0.003208470386713; COEF_CHROMA(0)(3) := 0.005812586167207; COEF_CHROMA(0)(4) := 0.007836898520244; COEF_CHROMA(0)(5) := 0.007946224752148; COEF_CHROMA(0)(6) := 0.005076131282231; COEF_CHROMA(0)(7) := -0.001106393114651; COEF_CHROMA(0)(8) := -0.009794412736841; COEF_CHROMA(0)(9) := -0.018894256460006; COEF_CHROMA(0)(10) := -0.025333779190322; COEF_CHROMA(0)(11) := -0.025680360956125; COEF_CHROMA(0)(12) := -0.017045207206490; COEF_CHROMA(0)(13) := 0.001965546812282; COEF_CHROMA(0)(14) := 0.030594710670943; COEF_CHROMA(0)(15) := 0.065740553629528; COEF_CHROMA(0)(16) := 0.102378590087966; COEF_CHROMA(0)(17) := 0.134525412849716; COEF_CHROMA(0)(18) := 0.156526287280546; COEF_CHROMA(0)(19) := 0.164345337003296; COEF_CHROMA(0)(20) := 0.156526287280546; COEF_CHROMA(0)(21) := 0.134525412849716; COEF_CHROMA(0)(22) := 0.102378590087966; COEF_CHROMA(0)(23) := 0.065740553629528; COEF_CHROMA(0)(24) := 0.030594710670943; COEF_CHROMA(0)(25) := 0.001965546812282; COEF_CHROMA(0)(26) := -0.017045207206490; COEF_CHROMA(0)(27) := -0.025680360956125; COEF_CHROMA(0)(28) := -0.025333779190322; COEF_CHROMA(0)(29) := -0.018894256460006; COEF_CHROMA(0)(30) := -0.009794412736841; COEF_CHROMA(0)(31) := -0.001106393114651; COEF_CHROMA(0)(32) := 0.005076131282231; COEF_CHROMA(0)(33) := 0.007946224752148; COEF_CHROMA(0)(34) := 0.007836898520244; COEF_CHROMA(0)(35) := 0.005812586167207; COEF_CHROMA(0)(36) := 0.003208470386713; COEF_CHROMA(0)(37) := 0.001159309335875; COEF_CHROMA(0)(38) := -0.003722043470114; -- 0.65MHz Low-Pass COEF_CHROMA(1)(0) := -0.002361147153011; COEF_CHROMA(1)(1) := -0.005191329852831; COEF_CHROMA(1)(2) := -0.008873661923564; COEF_CHROMA(1)(3) := -0.011638336849180; COEF_CHROMA(1)(4) := -0.011067993866724; COEF_CHROMA(1)(5) := -0.004479106965070; COEF_CHROMA(1)(6) := 0.010157564777977; COEF_CHROMA(1)(7) := 0.033253905306715; COEF_CHROMA(1)(8) := 0.062957708725283; COEF_CHROMA(1)(9) := 0.095157741845548; COEF_CHROMA(1)(10) := 0.124268046861551; COEF_CHROMA(1)(11) := 0.144591667784372; COEF_CHROMA(1)(12) := 0.151889910339019; COEF_CHROMA(1)(13) := 0.144591667784372; COEF_CHROMA(1)(14) := 0.124268046861551; COEF_CHROMA(1)(15) := 0.095157741845548; COEF_CHROMA(1)(16) := 0.062957708725283; COEF_CHROMA(1)(17) := 0.033253905306715; COEF_CHROMA(1)(18) := 0.010157564777977; COEF_CHROMA(1)(19) := -0.004479106965070; COEF_CHROMA(1)(20) := -0.011067993866724; COEF_CHROMA(1)(21) := -0.011638336849180; COEF_CHROMA(1)(22) := -0.008873661923564; COEF_CHROMA(1)(23) := -0.005191329852831; COEF_CHROMA(1)(24) := -0.002361147153011; -- 1MHz Low-Pass COEF_CHROMA(2)(0) := 0.000483584915901; COEF_CHROMA(2)(1) := -0.005477004326245; COEF_CHROMA(2)(2) := -0.010434486855713; COEF_CHROMA(2)(3) := -0.015699378341551; COEF_CHROMA(2)(4) := -0.017096242648751; COEF_CHROMA(2)(5) := -0.010385327807178; COEF_CHROMA(2)(6) := 0.007624712253086; COEF_CHROMA(2)(7) := 0.037415229890330; COEF_CHROMA(2)(8) := 0.075779965801425; COEF_CHROMA(2)(9) := 0.116056091282631; COEF_CHROMA(2)(10) := 0.149725337752434; COEF_CHROMA(2)(11) := 0.168915628363044; COEF_CHROMA(2)(12) := 0.168915628363044; COEF_CHROMA(2)(13) := 0.149725337752434; COEF_CHROMA(2)(14) := 0.116056091282631; COEF_CHROMA(2)(15) := 0.075779965801425; COEF_CHROMA(2)(16) := 0.037415229890330; COEF_CHROMA(2)(17) := 0.007624712253086; COEF_CHROMA(2)(18) := -0.010385327807178; COEF_CHROMA(2)(19) := -0.017096242648751; COEF_CHROMA(2)(20) := -0.015699378341551; COEF_CHROMA(2)(21) := -0.010434486855713; COEF_CHROMA(2)(22) := -0.005477004326245; COEF_CHROMA(2)(23) := 0.000483584915901; -- 2MHz Low-Pass COEF_CHROMA(3)(0) := -0.002245181031565; COEF_CHROMA(3)(1) := 0.010572821129204; COEF_CHROMA(3)(2) := 0.012484265589475; COEF_CHROMA(3)(3) := 0.004071200180002; COEF_CHROMA(3)(4) := -0.017657609596811; COEF_CHROMA(3)(5) := -0.039567570535448; COEF_CHROMA(3)(6) := -0.037109127038065; COEF_CHROMA(3)(7) := 0.009771751376987; COEF_CHROMA(3)(8) := 0.098568437781973; COEF_CHROMA(3)(9) := 0.198571792805873; COEF_CHROMA(3)(10) := 0.264924238603915; COEF_CHROMA(3)(11) := 0.264924238603915; COEF_CHROMA(3)(12) := 0.198571792805873; COEF_CHROMA(3)(13) := 0.098568437781973; COEF_CHROMA(3)(14) := 0.009771751376987; COEF_CHROMA(3)(15) := -0.037109127038065; COEF_CHROMA(3)(16) := -0.039567570535448; COEF_CHROMA(3)(17) := -0.017657609596811; COEF_CHROMA(3)(18) := 0.004071200180002; COEF_CHROMA(3)(19) := 0.012484265589475; COEF_CHROMA(3)(20) := 0.010572821129204; COEF_CHROMA(3)(21) := -0.002245181031565; -- CIF COEF_CHROMA(5)(0) := -0.001627438224515; COEF_CHROMA(5)(1) := -0.006751141203148; COEF_CHROMA(5)(2) := -0.008710568634491; COEF_CHROMA(5)(3) := -0.012236787791215; COEF_CHROMA(5)(4) := -0.012920768017098; COEF_CHROMA(5)(5) := -0.010004614148115; COEF_CHROMA(5)(6) := -0.001679093852106; COEF_CHROMA(5)(7) := 0.012705546317897; COEF_CHROMA(5)(8) := 0.032855012704045; COEF_CHROMA(5)(9) := 0.057161466036032; COEF_CHROMA(5)(10) := 0.082911248665062; COEF_CHROMA(5)(11) := 0.106672662815963; COEF_CHROMA(5)(12) := 0.124949875331351; COEF_CHROMA(5)(13) := 0.134887600256828; COEF_CHROMA(5)(14) := 0.134887600256828; COEF_CHROMA(5)(15) := 0.124949875331351; COEF_CHROMA(5)(16) := 0.106672662815963; COEF_CHROMA(5)(17) := 0.082911248665062; COEF_CHROMA(5)(18) := 0.057161466036032; COEF_CHROMA(5)(19) := 0.032855012704045; COEF_CHROMA(5)(20) := 0.012705546317897; COEF_CHROMA(5)(21) := -0.001679093852106; COEF_CHROMA(5)(22) := -0.010004614148115; COEF_CHROMA(5)(23) := -0.012920768017098; COEF_CHROMA(5)(24) := -0.012236787791215; COEF_CHROMA(5)(25) := -0.008710568634491; COEF_CHROMA(5)(26) := -0.006751141203148; COEF_CHROMA(5)(27) := -0.001627438224515; -- QCIF COEF_CHROMA(6)(0) := -0.006166687490960; COEF_CHROMA(6)(1) := -0.009528000035554; COEF_CHROMA(6)(2) := -0.010365594196096; COEF_CHROMA(6)(3) := -0.002932509377742; COEF_CHROMA(6)(4) := 0.016693961433087; COEF_CHROMA(6)(5) := 0.049056495041245; COEF_CHROMA(6)(6) := 0.089863919898842; COEF_CHROMA(6)(7) := 0.130500050532338; COEF_CHROMA(6)(8) := 0.160590940890318; COEF_CHROMA(6)(9) := 0.171702192911671; COEF_CHROMA(6)(10) := 0.160590940890318; COEF_CHROMA(6)(11) := 0.130500050532338; COEF_CHROMA(6)(12) := 0.089863919898842; COEF_CHROMA(6)(13) := 0.049056495041245; COEF_CHROMA(6)(14) := 0.016693961433087; COEF_CHROMA(6)(15) := -0.002932509377742; COEF_CHROMA(6)(16) := -0.010365594196096; COEF_CHROMA(6)(17) := -0.009528000035554; COEF_CHROMA(6)(18) := -0.006166687490960; WAIT; END PROCESS default; END BLOCK; END vhdl_behavioral;