------------------------------------------------------------------------------- -- File Name: sy89327l.vhd ------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 D.Vukicevic 05 Jun 17 Initial release ------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IF -- Technology: LVPECL -- Part: sy89327l -- Description: Any Input-to-LVPECL Differential Translator ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- SIMULATION RESOLUTION MUST BE 1 ps ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.ecl_utils.ALL; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY sy89327l IS GENERIC ( -- tipd delays: interconnect path delays tipd_VIN : VitalDelayType01 := VitalZeroDelay01; tipd_VINNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delay: propagation from input to output tpd_VIN_Q : VitalDelayType01 := UnitDelay01; -- tperiod_min - minimum clock period - 1/max freq tperiod_VIN : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( VIN : IN std_ulogic := 'U'; VINNeg : IN std_ulogic := 'U'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of sy89327l : ENTITY IS TRUE; END sy89327l; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of sy89327l IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "sy89327l"; SIGNAL VIN_ipd : std_ulogic := 'U'; SIGNAL VINNeg_ipd : std_ulogic := 'U'; BEGIN --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay(VIN_ipd,VIN,tipd_VIN); w_2 : VitalWireDelay(VINNeg_ipd,VINNeg,tipd_VINNeg); END BLOCK; Behavior : BLOCK PORT ( VIN : IN std_ulogic := 'U'; VINNeg : IN std_ulogic := 'U'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U' ); PORT MAP ( VIN => VIN_ipd, VINNeg => VINNeg_ipd, Q => Q, QNeg => QNeg ); CONSTANT diff_single_rec_tab : VitalStateTableType := ( ------INPUTS--|-PREV--|-OUTPUT---- -- IN INNeg| INint | INint' -- --------------|-------|----------- ( '\', '0', '1', '0'), -- single fall. - supplement to diff_rec_tab ( '0', '\', '0', '1'), -- single fall.7 - supplement to diff_rec_tab ( 'X', '-', '-', 'X'), -- A unknown ( '-', 'X', '-', 'X'), -- A unknown ( '1', '-', 'X', '1'), -- Recover from 'X' ( '0', '-', 'X', '0'), -- Recover from 'X' ( '/', '0', '0', '1'), -- valid diff. rising edge ( '1', '\', '0', '1'), -- valid diff. rising edge ( '\', '1', '1', '0'), -- valid diff. falling edge ( '0', '/', '1', '0'), -- valid diff. falling edge ( '-', '-', '-', 'S') -- default ); SIGNAL Qout_zd : std_ulogic := 'U'; SIGNAL Qout_tmp : std_logic := 'U'; SIGNAL viol : X01 := '0'; SIGNAL VINint : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Concurrent procedure calls ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qout_tmp, ResultMap => ECL_wired_or_rmap); a_2: VitalINV (q => QNeg, a => Qout_tmp, ResultMap => ECL_wired_or_rmap); --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck : PROCESS (VIN, VINNeg) VARIABLE Pviol_VIN : X01 := '0'; VARIABLE PD_VIN : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_VINNeg : X01 := '0'; VARIABLE PD_VINNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; VARIABLE PrevData : std_logic_vector(0 TO 1); BEGIN IF TimingChecksOn THEN -- Setup/Hold Checks Violation := '0'; VitalPeriodPulseCheck ( TestSignal => VIN, TestSignalName => "VIN", Period => tperiod_VIN, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_VIN, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_VIN ); VitalPeriodPulseCheck ( TestSignal => VINNeg, TestSignalName => "VINNeg", Period => tperiod_VIN, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_VINNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_VINNeg ); Violation := Pviol_VIN OR Pviol_VINNeg; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY Warning; viol <= violation; END IF; END PROCESS VITALTimingCheck; ---------------------------------------------------------------------------- -- Diff. Receiver Process ---------------------------------------------------------------------------- DiffRec : PROCESS (VIN_ipd, VINNeg_ipd, VINint) -- Functionality Results Variables VARIABLE VINint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 1); -- Glitch Detection Variables VARIABLE VIN_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ VitalStateTable ( StateTable => diff_single_rec_tab, DataIn => (VIN_ipd, VINNeg_ipd), Result => VINint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => VINint, OutSignalName => "VINint", OutTemp => VINint_zd, GlitchData => VIN_GlitchData, Paths => ( 0 => (InputChangeTime => VIN_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); Qout_zd <= VINint; END PROCESS; ------------------------------------------------ -- path delay ------------------------------------------------ Q_output: PROCESS(Qout_zd) VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01( OutSignal => Qout_tmp, OutSignalName => "Qout_tmp", OutTemp => Qout_zd, Mode => VitalTransport, GlitchData => Q_GlitchData, Paths => ( 0 => (InputChangeTime => Qout_zd'LAST_EVENT, PathDelay => tpd_VIN_Q, PathCondition => true)) ); END PROCESS Q_output; END BLOCK; END vhdl_behavioral;