-------------------------------------------------------------------------------- -- File Name: sii1161.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 S.Gmitrovic 05 Aug 31 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: MISC -- Technology: -- Part: SiI1161 -- Description: PanelLink Receiver -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY sii1161 IS GENERIC ( -- tipd delays: interconnect path delays tipd_RX0 : VitalDelayType01 := VitalZeroDelay01; tipd_RX0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RX1 : VitalDelayType01 := VitalZeroDelay01; tipd_RX1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RX2 : VitalDelayType01 := VitalZeroDelay01; tipd_RX2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RXC : VitalDelayType01 := VitalZeroDelay01; tipd_RXCNeg : VitalDelayType01 := VitalZeroDelay01; tipd_MODE : VitalDelayType01 := VitalZeroDelay01; tipd_PIXS : VitalDelayType01 := VitalZeroDelay01; tipd_I2CMODENeg : VitalDelayType01 := VitalZeroDelay01; tipd_HSDJTR : VitalDelayType01 := VitalZeroDelay01; tipd_PDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_PDONeg : VitalDelayType01 := VitalZeroDelay01; tipd_SCL : VitalDelayType01 := VitalZeroDelay01; tipd_SDA : VitalDelayType01 := VitalZeroDelay01; tpd_PDneg_DE :VitalDelayType01Z := UnitDelay01Z; --CKST =1 ST = 1 OCK_INV = 0 tpd_ODCK_QE_MODE1 :VitalDelayType01Z := UnitDelay01Z; --CKST =1 ST = 1 OCK_INV = 1 tpd_ODCK_QE_MODE2 :VitalDelayType01Z := UnitDelay01Z; --CKST =0 ST = 1 OCK_INV = 0 tpd_ODCK_QE_MODE3 :VitalDelayType01Z := UnitDelay01Z; --CKST =0 ST = 1 OCK_INV = 1 tpd_ODCK_QE_MODE4 :VitalDelayType01Z := UnitDelay01Z; --CKST =1 ST = 0 OCK_INV = 0 tpd_ODCK_QE_MODE5 :VitalDelayType01Z := UnitDelay01Z; --CKST =1 ST = 0 OCK_INV = 1 tpd_ODCK_QE_MODE6 :VitalDelayType01Z := UnitDelay01Z; --CKST =0 ST = 0 OCK_INV = 0 tpd_ODCK_QE_MODE7 :VitalDelayType01Z := UnitDelay01Z; --CKST =0 ST = 0 OCK_INV = 1 tpd_ODCK_QE_MODE8 :VitalDelayType01Z := UnitDelay01Z; --CKST =1 ST = 1 OCK_INV = 0 tpd_ODCK_DE_MODE1 :VitalDelayType01Z := UnitDelay01Z; --CKST =1 ST = 1 OCK_INV = 1 tpd_ODCK_DE_MODE2 :VitalDelayType01Z := UnitDelay01Z; --CKST =0 ST = 1 OCK_INV = 0 tpd_ODCK_DE_MODE3 :VitalDelayType01Z := UnitDelay01Z; --CKST =0 ST = 1 OCK_INV = 1 tpd_ODCK_DE_MODE4 :VitalDelayType01Z := UnitDelay01Z; --CKST =1 ST = 0 OCK_INV = 0 tpd_ODCK_DE_MODE5 :VitalDelayType01Z := UnitDelay01Z; --CKST =1 ST = 0 OCK_INV = 1 tpd_ODCK_DE_MODE6 :VitalDelayType01Z := UnitDelay01Z; --CKST =0 ST = 0 OCK_INV = 0 tpd_ODCK_DE_MODE7 :VitalDelayType01Z := UnitDelay01Z; --CKST =0 ST = 0 OCK_INV = 1 tpd_ODCK_DE_MODE8 :VitalDelayType01Z := UnitDelay01Z; --tskew values tskew_RXC_RXCNeg :VitalDelayType := UnitDelay; -- tpd values I2C tpd_SCL_SDA : VitalDelayType := UnitDelay; -- tSU:DAT I2C tsetup_SDA_SCL_FASTMODE_EQ_1_noedge_posedge : VitalDelayType := UnitDelay; tsetup_SDA_SCL_FASTMODE_EQ_0_noedge_posedge : VitalDelayType := UnitDelay; -- tSU:STA I2C tsetup_SCL_SDA_FASTMODE_EQ_1_noedge_negedge : VitalDelayType := UnitDelay; tsetup_SCL_SDA_FASTMODE_EQ_0_noedge_negedge : VitalDelayType := UnitDelay; -- tSU:STO I2C tsetup_SCL_SDA_FASTMODE_EQ_1_noedge_posedge : VitalDelayType := UnitDelay; tsetup_SCL_SDA_FASTMODE_EQ_0_noedge_posedge : VitalDelayType := UnitDelay; -- thold values: hold times I2C -- tHD:DAT thold_SDA_SCL_FASTMODE_EQ_1_noedge_negedge : VitalDelayType := UnitDelay; thold_SDA_SCL_FASTMODE_EQ_0_noedge_negedge : VitalDelayType := UnitDelay; -- tHD:STA thold_SCL_SDA_FASTMODE_EQ_1_noedge_negedge : VitalDelayType := UnitDelay; thold_SCL_SDA_FASTMODE_EQ_0_noedge_negedge : VitalDelayType := UnitDelay; -- tpw values: pulse widths I2C tpw_SCL_FASTMODE_EQ_1_posedge : VitalDelayType := UnitDelay; tpw_SCL_FASTMODE_EQ_0_posedge : VitalDelayType := UnitDelay; tpw_SCL_FASTMODE_EQ_1_negedge : VitalDelayType := UnitDelay; tpw_SCL_FASTMODE_EQ_0_negedge : VitalDelayType := UnitDelay; -- tperiod min (calculated as 1/max freq) I2C tperiod_SCL_FASTMODE_EQ_1 : VitalDelayType := UnitDelay; tperiod_SCL_FASTMODE_EQ_0 : VitalDelayType := UnitDelay; -- tdevice values: values for internal delays I2C tdevice_TBUF_S : VitalDelayType := 4.7 us;-- standard mode tdevice_TBUF_F : VitalDelayType := 1.3 us;-- fast mode tdevice_PROGTIME : VitalDelayType := UnitDelay; -- i2c specific generic : if device work in fast or standard mode standard_mode : BOOLEAN := TRUE; -- generic control parameters InstancePath : STRING:= DefaultInstancePath; TimingChecksOn : BOOLEAN:= DefaultTimingChecks; MsgOn : BOOLEAN:= DefaultMsgOn; XOn : BOOLEAN:= DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- For FMF SDF technology file usage TimingModel : STRING:= DefaultTimingModel ); PORT ( RX0 : IN std_ulogic := 'U'; RX0Neg : IN std_ulogic := 'U'; RX1 : IN std_ulogic := 'U'; RX1Neg : IN std_ulogic := 'U'; RX2 : IN std_ulogic := 'U'; RX2Neg : IN std_ulogic := 'U'; RXC : IN std_ulogic := 'U'; RXCNeg : IN std_ulogic := 'U'; MODE : IN std_ulogic := 'U'; PIXS : IN std_ulogic := 'U'; I2CMODENeg : IN std_ulogic := 'U'; HSDJTR : IN std_ulogic := 'U'; PDNeg : IN std_ulogic := 'U'; PDONeg : IN std_ulogic := 'U'; QE0 : OUT std_ulogic := 'U'; QE1 : OUT std_ulogic := 'U'; QE2 : OUT std_ulogic := 'U'; QE3 : OUT std_ulogic := 'U'; QE4 : OUT std_ulogic := 'U'; QE5 : OUT std_ulogic := 'U'; QE6 : OUT std_ulogic := 'U'; QE7 : OUT std_ulogic := 'U'; QE8 : OUT std_ulogic := 'U'; QE9 : OUT std_ulogic := 'U'; QE10 : OUT std_ulogic := 'U'; QE11 : OUT std_ulogic := 'U'; QE12 : OUT std_ulogic := 'U'; QE13 : OUT std_ulogic := 'U'; QE14 : OUT std_ulogic := 'U'; QE15 : OUT std_ulogic := 'U'; QE16 : OUT std_ulogic := 'U'; QE17 : OUT std_ulogic := 'U'; QE18 : OUT std_ulogic := 'U'; QE19 : OUT std_ulogic := 'U'; QE20 : OUT std_ulogic := 'U'; QE21 : OUT std_ulogic := 'U'; QE22 : OUT std_ulogic := 'U'; QE23 : OUT std_ulogic := 'U'; QO0 : OUT std_ulogic := 'U'; QO1 : OUT std_ulogic := 'U'; QO2 : OUT std_ulogic := 'U'; QO3 : OUT std_ulogic := 'U'; QO4 : OUT std_ulogic := 'U'; QO5 : OUT std_ulogic := 'U'; QO6 : OUT std_ulogic := 'U'; QO7 : OUT std_ulogic := 'U'; QO8 : OUT std_ulogic := 'U'; QO9 : OUT std_ulogic := 'U'; QO10 : OUT std_ulogic := 'U'; QO11 : OUT std_ulogic := 'U'; QO12 : OUT std_ulogic := 'U'; QO13 : OUT std_ulogic := 'U'; QO14 : OUT std_ulogic := 'U'; QO15 : OUT std_ulogic := 'U'; QO16 : OUT std_ulogic := 'U'; QO17 : OUT std_ulogic := 'U'; QO18 : OUT std_ulogic := 'U'; QO19 : OUT std_ulogic := 'U'; QO20 : OUT std_ulogic := 'U'; QO21 : OUT std_ulogic := 'U'; QO22 : OUT std_ulogic := 'U'; QO23 : OUT std_ulogic := 'U'; SCDT : OUT std_ulogic := 'U'; ODCK : OUT std_ulogic := 'U'; DE : OUT std_ulogic := 'U'; HSYNC : OUT std_ulogic := 'U'; VSYNC : OUT std_ulogic := 'U'; CTL1 : OUT std_ulogic := 'U'; CTL2 : OUT std_ulogic := 'U'; CTL3 : OUT std_ulogic := 'U'; SCL : IN std_ulogic := 'U'; SDA : INOUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of sii1161 : ENTITY IS TRUE; END sii1161; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of sii1161 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "sii1161"; SIGNAL RX0_ipd : std_ulogic := 'U'; SIGNAL RX0Neg_ipd : std_ulogic := 'U'; SIGNAL RX1_ipd : std_ulogic := 'U'; SIGNAL RX1Neg_ipd : std_ulogic := 'U'; SIGNAL RX2_ipd : std_ulogic := 'U'; SIGNAL RX2Neg_ipd : std_ulogic := 'U'; SIGNAL RXC_ipd : std_ulogic := 'U'; SIGNAL RXCNeg_ipd : std_ulogic := 'U'; SIGNAL MODE_ipd : std_ulogic := 'U'; SIGNAL PIXS_ipd : std_ulogic := 'U'; SIGNAL I2CMODENeg_ipd : std_ulogic := 'U'; SIGNAL HSDJTR_ipd : std_ulogic := 'U'; SIGNAL PDNeg_ipd : std_ulogic := 'U'; SIGNAL PDONeg_ipd : std_ulogic := 'U'; SIGNAL SCL_ipd : std_ulogic := 'U'; SIGNAL SDA_ipd : std_ulogic := 'U'; SIGNAL buf_in : std_logic := '0'; SIGNAL buf_out : std_logic := '0'; SIGNAL buf_fast_in : std_logic := '0'; SIGNAL buf_fast_out : std_logic := '0'; SIGNAL wr_in : std_logic := '0'; SIGNAL wr_out : std_logic := '0'; BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays TBUF_S: VitalBuf(buf_out, buf_in, (tdevice_TBUF_S,UnitDelay)); TBUF_F: VitalBuf(buf_fast_out, buf_fast_in,(tdevice_TBUF_F,UnitDelay)); WR: VitalBuf(wr_out, wr_in, (tdevice_PROGTIME ,UnitDelay)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (RX0_ipd, RX0, tipd_RX0); w_2 : VitalWireDelay (RX0Neg_ipd, RX0Neg, tipd_RX0Neg); w_3 : VitalWireDelay (RX1_ipd, RX1, tipd_RX1); w_4 : VitalWireDelay (RX1Neg_ipd, RX1Neg, tipd_RX1Neg); w_5 : VitalWireDelay (RX2_ipd, RX2, tipd_RX2); w_6 : VitalWireDelay (RX2Neg_ipd, RX2Neg, tipd_RX2Neg); w_7 : VitalWireDelay (RXC_ipd, RXC, tipd_RXC); w_8 : VitalWireDelay (RXCNeg_ipd, RXCNeg, tipd_RXCNeg); w_9 : VitalWireDelay (MODE_ipd, MODE, tipd_MODE); w_10 : VitalWireDelay (PIXS_ipd, PIXS, tipd_PIXS); w_11 : VitalWireDelay (I2CMODENeg_ipd, I2CMODENeg, tipd_I2CMODENeg); w_12 : VitalWireDelay (HSDJTR_ipd, HSDJTR, tipd_HSDJTR); w_13 : VitalWireDelay (PDNeg_ipd, PDNeg, tipd_PDNeg); w_14 : VitalWireDelay (PDONeg_ipd, PDONeg, tipd_PDONeg); w_15 : VitalWireDelay (SCL_ipd, SCL, tipd_SCL); w_16 : VitalWireDelay (SDA_ipd, SDA, tipd_SDA); END BLOCK; Behavior : BLOCK PORT ( RX0 : IN std_ulogic := 'U'; RX0Neg : IN std_ulogic := 'U'; RX1 : IN std_ulogic := 'U'; RX1Neg : IN std_ulogic := 'U'; RX2 : IN std_ulogic := 'U'; RX2Neg : IN std_ulogic := 'U'; RXC : IN std_ulogic := 'U'; RXCNeg : IN std_ulogic := 'U'; MODE : IN std_ulogic := 'U'; PIXS : IN std_ulogic := 'U'; I2CMODENeg : IN std_ulogic := 'U'; HSDJTR : IN std_ulogic := 'U'; PDNeg : IN std_ulogic := 'U'; PDONeg : IN std_ulogic := 'U'; QEOut : OUT std_logic_vector(23 DOWNTO 0) :=(OTHERS => 'Z'); QOOut : OUT std_logic_vector(23 DOWNTO 0) :=(OTHERS => 'Z'); ODCKOut : OUT std_ulogic := 'U'; SCDTOut : OUT std_ulogic := 'U'; DEOut : OUT std_ulogic := 'Z'; HSYNCOut : OUT std_ulogic := 'Z'; VSYNCOut : OUT std_ulogic := 'Z'; CTL1Out : OUT std_ulogic := 'Z'; CTL2Out : OUT std_ulogic := 'Z'; CTL3Out : OUT std_ulogic := 'Z'; SCLIn : IN std_ulogic := 'U'; SDAin : IN std_ulogic := 'U'; SDAout : OUT std_ulogic := 'U' ); PORT MAP ( RX0 => RX0_ipd, RX0Neg => RX0Neg_ipd, RX1 => RX1_ipd, RX1Neg => RX1Neg_ipd, RX2 => RX2_ipd, RX2Neg => RX2Neg_ipd, RXC => RXC_ipd, RXCNeg => RXCNeg_ipd, PIXS => PIXS_ipd, MODE => MODE_ipd, I2CMODENeg => I2CMODENeg_ipd, HSDJTR => HSDJTR_ipd, PDNeg => PDNeg_ipd, PDONeg => PDONeg_ipd, QEOut(0) => QE0, QEOut(1) => QE1, QEOut(2) => QE2, QEOut(3) => QE3, QEOut(4) => QE4, QEOut(5) => QE5, QEOut(6) => QE6, QEOut(7) => QE7, QEOut(8) => QE8, QEOut(9) => QE9, QEOut(10) => QE10, QEOut(11) => QE11, QEOut(12) => QE12, QEOut(13) => QE13, QEOut(14) => QE14, QEOut(15) => QE15, QEOut(16) => QE16, QEOut(17) => QE17, QEOut(18) => QE18, QEOut(19) => QE19, QEOut(20) => QE20, QEOut(21) => QE21, QEOut(22) => QE22, QEOut(23) => QE23, QOOut(0) => QO0, QOOut(1) => QO1, QOOut(2) => QO2, QOOut(3) => QO3, QOOut(4) => QO4, QOOut(5) => QO5, QOOut(6) => QO6, QOOut(7) => QO7, QOOut(8) => QO8, QOOut(9) => QO9, QOOut(10) => QO10, QOOut(11) => QO11, QOOut(12) => QO12, QOOut(13) => QO13, QOOut(14) => QO14, QOOut(15) => QO15, QOOut(16) => QO16, QOOut(17) => QO17, QOOut(18) => QO18, QOOut(19) => QO19, QOOut(20) => QO20, QOOut(21) => QO21, QOOut(22) => QO22, QOOut(23) => QO23, ODCKOut => ODCK, SCDTOut => SCDT, DEOut => DE, HSYNCOut => HSYNC, VSYNCOut => VSYNC, CTL1Out => CTL1, CTL2Out => CTL2, CTL3Out => CTL3, SCLIn => SCL_ipd, SDAIn => SDA_ipd, SDAOut => SDA ); TYPE state_type IS ( IDLE, CONTROL_BYTE, COMMAND, WRITE, READ ); SUBTYPE RegType IS std_logic_vector(7 downto 0); SIGNAL current_state : state_type; SIGNAL next_state : state_type; -- clock counter SIGNAL clk_cnt : INTEGER := 0; SIGNAL first_byte : std_logic_vector(9 downto 0) := (OTHERS => '0'); SIGNAL command_byte : std_logic_vector(9 downto 0) := (OTHERS => '0'); SIGNAL start : std_logic := '0'; SIGNAL stop : std_logic := '0'; SIGNAL stop_del : std_logic := '0'; SIGNAL busy : std_logic := '0'; SIGNAL busy_del : std_logic := '0'; SIGNAL Slave_ID : BOOLEAN := false; SIGNAL Firstbyte_sent : BOOLEAN := false; SIGNAL Release_SDA : BOOLEAN := false; SIGNAL Byte_received : BOOLEAN := false; SIGNAL SDA_zd : std_logic := 'Z'; SIGNAL DE_zd : std_logic := 'Z'; SIGNAL HSYNC_zd : std_logic := 'Z'; SIGNAL VSYNC_zd : std_logic := 'Z'; SIGNAL CTL1_zd : std_logic := 'Z'; SIGNAL CTL2_zd : std_logic := 'Z'; SIGNAL CTL3_zd : std_logic := 'Z'; SIGNAL QE_zd : std_logic_vector(23 DOWNTO 0):=(OTHERS =>'Z'); SIGNAL QO_zd : std_logic_vector(23 DOWNTO 0):=(OTHERS =>'Z'); SIGNAL FASTMODE : std_logic := '0'; SIGNAL PERIOD : time := 2 ns; SIGNAL clk : std_ulogic := '1'; SIGNAL ODCKzd : std_ulogic := '0'; SIGNAL TRG1 : std_ulogic:= '0'; SIGNAL TRG2 : std_ulogic:= '0'; SIGNAL TRG3 : std_ulogic:= '0'; SIGNAL TRG4 : std_ulogic:= '0'; SIGNAL RXCinactive : std_ulogic := '1'; SIGNAL DEactive : std_ulogic := '0'; SIGNAL DEtmp : std_ulogic := '1'; SHARED VARIABLE RXCactive : BOOLEAN := false; SHARED VARIABLE Previous : Time := 0 ns; SHARED VARIABLE TmpPer : Time := 0 ns; SHARED VARIABLE RX0_tmp : std_logic_vector(19 downto 0); SHARED VARIABLE RX1_tmp : std_logic_vector(19 downto 0); SHARED VARIABLE RX2_tmp : std_logic_vector(19 downto 0); SHARED VARIABLE RX0_data : std_logic_vector(19 downto 0); SHARED VARIABLE RX1_data : std_logic_vector(19 downto 0); SHARED VARIABLE RX2_data : std_logic_vector(19 downto 0); SHARED VARIABLE pixeldata : BOOLEAN := false; -- registers map SHARED VARIABLE VND_IDL : RegType := "00000001";--Read only SHARED VARIABLE VND_IDH : RegType := "00000000";--Read only SHARED VARIABLE DEV_IDL : RegType := "00000000";--Read only SHARED VARIABLE DEV_IDH : RegType := "00000000";--Read only SHARED VARIABLE DEV_REV : RegType := "00000000";--Read only SHARED VARIABLE EQ_DATA_R : RegType := "00001101";--Read/Write SHARED VARIABLE REG_A : RegType := "00100100";--Read/Write SHARED VARIABLE REG_B : RegType := "00000000";--Read/Write ALIAS EQ_DATA : std_logic_vector IS EQ_DATA_R(3 downto 0); ALIAS ST_BIT : std_logic IS REG_A(2); ALIAS CKST : std_logic IS REG_A(3); ALIAS OCKINV : std_logic IS REG_A(4); ALIAS STAG_OUT : std_logic IS REG_A(5); ALIAS ZONEO : std_logic IS REG_B(3); ALIAS LBW : std_logic_vector IS REG_B(1 downto 0); BEGIN FASTMODE <= '0' WHEN standard_mode = TRUE ELSE '1'; ODCKOut <= 'Z' AFTER tpd_PDNeg_DE(tr0z) WHEN PDNeg ='0' OR PDONeg ='0' ELSE ODCKzd WHEN (MODE = '1' AND SCLIn = '0') OR (MODE = '0' AND I2CMODENeg = '0' AND OCKINV ='0') ELSE not ODCKzd WHEN (MODE = '1' AND SCLIn = '1') OR (MODE = '0' AND I2CMODENeg = '0' AND OCKINV ='1'); SCDTOut <= 'Z' AFTER tpd_PDNeg_DE(tr0z) WHEN PDNeg ='0' ELSE '1' WHEN DEactive = '1' ELSE '0' WHEN DEactive = '0'; --Intra pair differential input skew check SkewCheck : PROCESS (RXC, RXCNeg, RX0, RX0Neg, RX1, RX1Neg,RX2, RX2Neg, TRG1, TRG2, TRG3, TRG4) VARIABLE Tviol_RXC_RXCNeg : X01 := '0'; VARIABLE SD_RXC_RXCNeg : VitalSkewDataType := VitalSkewDataInit; VARIABLE Tviol_RX0_RX0Neg : X01 := '0'; VARIABLE SD_RX0_RX0Neg : VitalSkewDataType := VitalSkewDataInit; VARIABLE Tviol_RX1_RX1Neg : X01 := '0'; VARIABLE SD_RX1_RX1Neg : VitalSkewDataType := VitalSkewDataInit; VARIABLE Tviol_RX2_RX2Neg : X01 := '0'; VARIABLE SD_RX2_RX2Neg : VitalSkewDataType := VitalSkewDataInit; VARIABLE Violation : X01; BEGIN IF (TimingChecksOn) THEN VitalOutPhaseSkewCheck ( Signal1 => RXC, Signal1Name => "RXC", Signal2 => RXCNeg, Signal2Name => "RXCNeg", SkewS1S2RiseFall => tskew_RXC_RXCNeg, SkewS1S2FallRise => tskew_RXC_RXCNeg, SkewS2S1RiseFall => tskew_RXC_RXCNeg, SkewS2S1FallRise => tskew_RXC_RXCNeg, SkewData => SD_RXC_RXCNeg, CheckEnabled => TRUE, Violation => Tviol_RXC_RXCNeg, Trigger => TRG1); VitalOutPhaseSkewCheck ( Signal1 => RX0, Signal1Name => "RX0", Signal2 => RX0Neg, Signal2Name => "RX0Neg", SkewS1S2RiseFall => tskew_RXC_RXCNeg, SkewS1S2FallRise => tskew_RXC_RXCNeg, SkewS2S1RiseFall => tskew_RXC_RXCNeg, SkewS2S1FallRise => tskew_RXC_RXCNeg, SkewData => SD_RX0_RX0Neg, CheckEnabled => TRUE, Violation => Tviol_RX0_RX0Neg, Trigger => TRG2); VitalOutPhaseSkewCheck ( Signal1 => RX1, Signal1Name => "RX1", Signal2 => RX1Neg, Signal2Name => "RX1Neg", SkewS1S2RiseFall => tskew_RXC_RXCNeg, SkewS1S2FallRise => tskew_RXC_RXCNeg, SkewS2S1RiseFall => tskew_RXC_RXCNeg, SkewS2S1FallRise => tskew_RXC_RXCNeg, SkewData => SD_RX1_RX1Neg, CheckEnabled => TRUE, Violation => Tviol_RX1_RX1Neg, Trigger => TRG3); VitalOutPhaseSkewCheck ( Signal1 => RX2, Signal1Name => "RX2", Signal2 => RX2Neg, Signal2Name => "RX2Neg", SkewS1S2RiseFall => tskew_RXC_RXCNeg, SkewS1S2FallRise => tskew_RXC_RXCNeg, SkewS2S1RiseFall => tskew_RXC_RXCNeg, SkewS2S1FallRise => tskew_RXC_RXCNeg, SkewData => SD_RX2_RX2Neg, CheckEnabled => TRUE, Violation => Tviol_RX2_RX2Neg, Trigger => TRG4); Violation := Tviol_RXC_RXCNeg OR Tviol_RX0_RX0Neg OR Tviol_RX1_RX1Neg OR Tviol_RX2_RX2Neg ; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS; CLOCKTIME: PROCESS(RXC) BEGIN IF rising_edge(RXC) THEN RXCactive := TRUE; TmpPer := NOW - Previous; IF TmpPer > 0 ns THEN IF PIXS = '0' THEN PERIOD <= TmpPer/20; ELSE PERIOD <= TmpPer/40; END IF; END IF; Previous := NOW; END IF; END PROCESS; RXC_inactive: PROCESS BEGIN WAIT FOR 1 ns; IF ((NOW - Previous) >= 10 us) AND RXCinactive = '0' THEN RXCinactive <= '1'; RXCactive := false; WAIT UNTIL RXC'event; ELSIF RXCinactive = '1' AND RXCactive = true THEN WAIT FOR 100 us; RXCinactive <= '0'; END IF; END PROCESS; PLL : PROCESS BEGIN IF ((NOW-Previous) <= TmpPer) THEN WAIT FOR PERIOD; clk <= not(clk); ELSE WAIT until rising_edge(RXC); END IF; END PROCESS PLL; ODCKint : PROCESS(RXC) BEGIN ODCKzd <= RXC; END PROCESS ODCKint; DEact1: PROCESS (DE_zd) BEGIN IF falling_edge(DE_zd) THEN DEtmp <= '0'; ELSIF rising_edge(DE_zd) THEN DEtmp <= '1','0' AFTER 50 ms; END IF; END PROCESS DEact1; DEact: PROCESS (DEtmp, DE_zd, PDNeg) VARIABLE DEcount : NATURAL := 0; BEGIN if falling_edge(DE_zd) THEN DEcount := DEcount +1; IF DEcount = 10 THEN DEactive <= '1'; DEcount := 0; END IF; END IF; IF falling_edge(DEtmp) AND DE_zd = '1' THEN DEactive <= '0'; END IF; IF falling_edge(PDNeg) THEN DEcount := 0; DEactive <= '0'; END IF; END PROCESS DEact; DeserializedecodeRX0 : PROCESS (clk, ODCKzd) VARIABLE i : NATURAL := 0; BEGIN IF rising_edge(ODCKzd) THEN i := 0; END IF; IF rising_edge(clk) THEN RX0_data(i) := RX0; i := i+1; IF (i = 10 AND PIXS = '0') OR (i = 20 AND PIXS = '1') THEN i := 0; IF RX0_data(9 downto 0) = "0010101011" THEN RX0_tmp(9 downto 8) := "00"; pixeldata := false; ELSIF RX0_data(9 downto 0) = "1101010100" THEN RX0_tmp(9 downto 8) := "01"; pixeldata := false; ELSIF RX0_data(9 downto 0) = "0010101010" THEN RX0_tmp(9 downto 8) := "10"; pixeldata := false; ELSIF RX0_data(9 downto 0) = "1101010101" THEN RX0_tmp(9 downto 8) := "11"; pixeldata := false; ELSE pixeldata := TRUE; IF RX0_data(9) = '1' THEN RX0_data(7 downto 0) := not(RX0_data(7 downto 0)); END IF; IF RX0_data(8) = '1' THEN RX0_tmp(0) := RX0_data(0); RX0_tmp(1) := RX0_data(0) XOR RX0_data(1); RX0_tmp(2) := RX0_data(1) XOR RX0_data(2); RX0_tmp(3) := RX0_data(2) XOR RX0_data(3); RX0_tmp(4) := RX0_data(3) XOR RX0_data(4); RX0_tmp(5) := RX0_data(4) XOR RX0_data(5); RX0_tmp(6) := RX0_data(5) XOR RX0_data(6); RX0_tmp(7) := RX0_data(6) XOR RX0_data(7); ELSE RX0_tmp(0) := RX0_data(0); RX0_tmp(1) := RX0_data(0) XNOR RX0_data(1); RX0_tmp(2) := RX0_data(1) XNOR RX0_data(2); RX0_tmp(3) := RX0_data(2) XNOR RX0_data(3); RX0_tmp(4) := RX0_data(3) XNOR RX0_data(4); RX0_tmp(5) := RX0_data(4) XNOR RX0_data(5); RX0_tmp(6) := RX0_data(5) XNOR RX0_data(6); RX0_tmp(7) := RX0_data(6) XNOR RX0_data(7); END IF; pixeldata := TRUE; IF PIXS = '1' THEN IF RX0_data(19) = '1' THEN RX0_data(17 downto 10) := not(RX0_data(17 downto 10)); END IF; IF RX0_data(18) = '1' THEN RX0_tmp(10) := RX0_data(10); RX0_tmp(11) := RX0_data(10) XOR RX0_data(11); RX0_tmp(12) := RX0_data(11) XOR RX0_data(12); RX0_tmp(13) := RX0_data(12) XOR RX0_data(13); RX0_tmp(14) := RX0_data(13) XOR RX0_data(14); RX0_tmp(15) := RX0_data(14) XOR RX0_data(15); RX0_tmp(16) := RX0_data(15) XOR RX0_data(16); RX0_tmp(17) := RX0_data(16) XOR RX0_data(17); ELSE RX0_tmp(10) := RX0_data(10); RX0_tmp(11) := RX0_data(10) XNOR RX0_data(1); RX0_tmp(12) := RX0_data(11) XNOR RX0_data(2); RX0_tmp(13) := RX0_data(12) XNOR RX0_data(3); RX0_tmp(14) := RX0_data(13) XNOR RX0_data(4); RX0_tmp(15) := RX0_data(14) XNOR RX0_data(5); RX0_tmp(16) := RX0_data(15) XNOR RX0_data(6); RX0_tmp(17) := RX0_data(16) XNOR RX0_data(7); END IF; END IF; END IF; END IF; END IF; END PROCESS; DeserializedecodeRX1 : PROCESS(clk, ODCKzd) VARIABLE i : NATURAL := 0; BEGIN IF rising_edge(ODCKzd) THEN i := 0; END IF; IF rising_edge(clk) THEN RX1_data(i) := RX1; i := i+1; IF (i = 10 AND PIXS = '0') OR (i = 20 AND PIXS = '1') THEN i := 0; IF (RX1_data(9 downto 0) = "0010101011") OR (RX1_data(9 downto 0) = "0010101010") THEN RX1_tmp(8) := '0'; pixeldata := false; ELSIF (RX1_data(9 downto 0) = "1101010100") OR (RX1_data(9 downto 0) = "1101010101") THEN RX1_tmp(8) := '1'; pixeldata := false; ELSE pixeldata := true; IF RX1_data(9) = '1' THEN RX1_data(7 downto 0) := not(RX1_data(7 downto 0)); END IF; IF RX1_data(8) = '1' THEN RX1_tmp(0) := RX1_data(0); RX1_tmp(1) := RX1_data(0) XOR RX1_data(1); RX1_tmp(2) := RX1_data(1) XOR RX1_data(2); RX1_tmp(3) := RX1_data(2) XOR RX1_data(3); RX1_tmp(4) := RX1_data(3) XOR RX1_data(4); RX1_tmp(5) := RX1_data(4) XOR RX1_data(5); RX1_tmp(6) := RX1_data(5) XOR RX1_data(6); RX1_tmp(7) := RX1_data(6) XOR RX1_data(7); ELSE RX1_tmp(0) := RX1_data(0); RX1_tmp(1) := RX1_data(0) XNOR RX1_data(1); RX1_tmp(2) := RX1_data(1) XNOR RX1_data(2); RX1_tmp(3) := RX1_data(2) XNOR RX1_data(3); RX1_tmp(4) := RX1_data(3) XNOR RX1_data(4); RX1_tmp(5) := RX1_data(4) XNOR RX1_data(5); RX1_tmp(6) := RX1_data(5) XNOR RX1_data(6); RX1_tmp(7) := RX1_data(6) XNOR RX1_data(7); END IF; IF PIXS = '1' THEN IF RX1_data(19) = '1' THEN RX1_data(17 downto 10) := not(RX1_data(17 downto 10)); END IF; IF RX1_data(18) = '1' THEN RX1_tmp(10) := RX1_data(10); RX1_tmp(11) := RX1_data(10) XOR RX1_data(11); RX1_tmp(12) := RX1_data(11) XOR RX1_data(12); RX1_tmp(13) := RX1_data(12) XOR RX1_data(13); RX1_tmp(14) := RX1_data(13) XOR RX1_data(14); RX1_tmp(15) := RX1_data(14) XOR RX1_data(15); RX1_tmp(16) := RX1_data(15) XOR RX1_data(16); RX1_tmp(17) := RX1_data(16) XOR RX1_data(17); ELSE RX1_tmp(10) := RX1_data(10); RX1_tmp(11) := RX1_data(10) XNOR RX1_data(1); RX1_tmp(12) := RX1_data(11) XNOR RX1_data(2); RX1_tmp(13) := RX1_data(12) XNOR RX1_data(3); RX1_tmp(14) := RX1_data(13) XNOR RX1_data(4); RX1_tmp(15) := RX1_data(14) XNOR RX1_data(5); RX1_tmp(16) := RX1_data(15) XNOR RX1_data(6); RX1_tmp(17) := RX1_data(16) XNOR RX1_data(7); END IF; END IF; END IF; END IF; END IF; END PROCESS; DeserializedecodeRX2 : PROCESS(clk, ODCKzd) VARIABLE i : NATURAL := 0; BEGIN IF rising_edge(ODCKzd) THEN i := 0; END IF; IF rising_edge(clk) THEN RX2_data(i) := RX2; i := i+1; IF (i = 10 AND PIXS = '0') OR (i = 20 AND PIXS = '1') THEN i := 0; IF RX2_data(9 downto 0) = "0010101011" THEN RX2_tmp(9 downto 8) := "00"; pixeldata := false; ELSIF RX2_data(9 downto 0) = "1101010100" THEN RX2_tmp(9 downto 8) := "01"; pixeldata := false; ELSIF RX2_data(9 downto 0) = "0010101010" THEN RX2_tmp(9 downto 8) := "10"; pixeldata := false; ELSIF RX2_data(9 downto 0) = "1101010101" THEN RX2_tmp(9 downto 8) := "11"; pixeldata := false; ELSE pixeldata := true; IF RX2_data(9) = '1' THEN RX2_data(7 downto 0) := not(RX2_data(7 downto 0)); END IF; IF RX2_data(8) = '1' THEN RX2_tmp(0) := RX2_data(0); RX2_tmp(1) := RX2_data(0) XOR RX2_data(1); RX2_tmp(2) := RX2_data(1) XOR RX2_data(2); RX2_tmp(3) := RX2_data(2) XOR RX2_data(3); RX2_tmp(4) := RX2_data(3) XOR RX2_data(4); RX2_tmp(5) := RX2_data(4) XOR RX2_data(5); RX2_tmp(6) := RX2_data(5) XOR RX2_data(6); RX2_tmp(7) := RX2_data(6) XOR RX2_data(7); ELSE RX2_tmp(0) := RX2_data(0); RX2_tmp(1) := RX2_data(0) XNOR RX2_data(1); RX2_tmp(2) := RX2_data(1) XNOR RX2_data(2); RX2_tmp(3) := RX2_data(2) XNOR RX2_data(3); RX2_tmp(4) := RX2_data(3) XNOR RX2_data(4); RX2_tmp(5) := RX2_data(4) XNOR RX2_data(5); RX2_tmp(6) := RX2_data(5) XNOR RX2_data(6); RX2_tmp(7) := RX2_data(6) XNOR RX2_data(7); END IF; IF PIXS = '1' THEN IF RX2_data(19) = '1' THEN RX2_data(17 downto 10) := not(RX2_data(17 downto 10)); END IF; IF RX2_data(18) = '1' THEN RX2_tmp(10) := RX2_data(10); RX2_tmp(11) := RX2_data(10) XOR RX2_data(11); RX2_tmp(12) := RX2_data(11) XOR RX2_data(12); RX2_tmp(13) := RX2_data(12) XOR RX2_data(13); RX2_tmp(14) := RX2_data(13) XOR RX2_data(14); RX2_tmp(15) := RX2_data(14) XOR RX2_data(15); RX2_tmp(16) := RX2_data(15) XOR RX2_data(16); RX2_tmp(17) := RX2_data(16) XOR RX2_data(17); ELSE RX2_tmp(10) := RX2_data(10); RX2_tmp(11) := RX2_data(10) XNOR RX2_data(1); RX2_tmp(12) := RX2_data(11) XNOR RX2_data(2); RX2_tmp(13) := RX2_data(12) XNOR RX2_data(3); RX2_tmp(14) := RX2_data(13) XNOR RX2_data(4); RX2_tmp(15) := RX2_data(14) XNOR RX2_data(5); RX2_tmp(16) := RX2_data(15) XNOR RX2_data(6); RX2_tmp(17) := RX2_data(16) XNOR RX2_data(7); END IF; END IF; END IF; END IF; END IF; END PROCESS; GENERATE_OUTPUTS: PROCESS(ODCKzd, RXCinactive, PDNeg, PDONeg) VARIABLE hsync_count : NATURAL := 0; BEGIN IF rising_edge(ODCKzd) AND RXCinactive = '0' AND PDNeg = '1' AND PDONeg = '1' THEN IF pixeldata THEN hsync_count := 0; QE_zd(23 downto 0) <= RX2_tmp(7 downto 0)& RX1_tmp(7 downto 0) & RX0_tmp(7 downto 0); IF PIXS = '1' THEN QO_zd(23 downto 0) <= RX2_tmp(17 downto 10)& RX1_tmp(17 downto 10) & RX0_tmp(17 downto 10); END IF; DE_zd <= '1'; VSYNC_zd <= '0'; HSYNC_zd <= '0'; CTL1_zd <= '0'; CTL2_zd <= '0'; CTL3_zd <= '0'; ELSE DE_zd <= '0'; VSYNC_zd <= RX0_tmp(9); IF RX0_tmp(8) = '1' THEN IF HSDJTR = '0' THEN HSYNC_zd <= RX0_tmp(8); hsync_count := 0; ELSE HSYNC_zd <= RX0_tmp(8); hsync_count := hsync_count+1; END IF; ELSE IF hsync_count > 3 AND HSDJTR = '1' THEN HSYNC_zd <= RX0_tmp(8); hsync_count := 0; ELSIF hsync_count <= 3 AND hsync_count >0 AND HSDJTR='1' THEN HSYNC_zd <= not RX0_tmp(8); hsync_count := hsync_count+1; ELSE HSYNC_zd <= RX0_tmp(8); hsync_count := 0; END IF; END IF; CTL1_zd <= RX1_tmp(8); CTL2_zd <= RX2_tmp(9); CTL3_zd <= RX2_tmp(8); END IF; END IF; IF falling_edge(PDNeg) OR falling_edge(PDONeg) OR rising_edge(RXCinactive) THEN DE_zd <= 'Z'; VSYNC_zd <= 'Z'; HSYNC_zd <= 'Z'; QE_zd(23 downto 0) <= (OTHERS => 'Z'); QO_zd(23 downto 0) <= (OTHERS => 'Z'); IF NOT PDONeg'event THEN CTL1_zd <= 'Z'; END IF; CTL2_zd <= 'Z'; CTL3_zd <= 'Z'; END IF; END PROCESS; ----------------------------------------------------------------------- -- Path Delay Section ----------------------------------------------------------------------- DE_OUT: PROCESS(DE_zd, RXCinactive) VARIABLE tpd_ODCK_DE_MODE1_st : VitalDelayType01Z; VARIABLE tpd_ODCK_DE_MODE2_st : VitalDelayType01Z; VARIABLE tpd_ODCK_DE_MODE3_st : VitalDelayType01Z; VARIABLE tpd_ODCK_DE_MODE4_st : VitalDelayType01Z; VARIABLE tpd_ODCK_DE_MODE5_st : VitalDelayType01Z; VARIABLE tpd_ODCK_DE_MODE6_st : VitalDelayType01Z; VARIABLE tpd_ODCK_DE_MODE7_st : VitalDelayType01Z; VARIABLE tpd_ODCK_DE_MODE8_st : VitalDelayType01Z; VARIABLE DE_GlitchData : VitalGlitchDataType; VARIABLE DEData : std_logic; BEGIN IF ((MODE = '0' AND STAG_OUT = '0') OR (MODE ='1' AND I2CMODENeg = '0')) AND PIXS = '1' THEN tpd_ODCK_DE_MODE1_st(tr01) := tpd_ODCK_DE_MODE1(tr01)+PERIOD*10; tpd_ODCK_DE_MODE1_st(tr10) := tpd_ODCK_DE_MODE1(tr10)+PERIOD*10; tpd_ODCK_DE_MODE2_st(tr01) := tpd_ODCK_DE_MODE2(tr01)+PERIOD*10; tpd_ODCK_DE_MODE2_st(tr10) := tpd_ODCK_DE_MODE2(tr10)+PERIOD*10; tpd_ODCK_DE_MODE3_st(tr01) := tpd_ODCK_DE_MODE3(tr01)+PERIOD*10; tpd_ODCK_DE_MODE3_st(tr10) := tpd_ODCK_DE_MODE3(tr10)+PERIOD*10; tpd_ODCK_DE_MODE4_st(tr01) := tpd_ODCK_DE_MODE4(tr01)+PERIOD*10; tpd_ODCK_DE_MODE4_st(tr10) := tpd_ODCK_DE_MODE4(tr10)+PERIOD*10; tpd_ODCK_DE_MODE5_st(tr01) := tpd_ODCK_DE_MODE5(tr01)+PERIOD*10; tpd_ODCK_DE_MODE5_st(tr10) := tpd_ODCK_DE_MODE5(tr10)+PERIOD*10; tpd_ODCK_DE_MODE6_st(tr01) := tpd_ODCK_DE_MODE6(tr01)+PERIOD*10; tpd_ODCK_DE_MODE6_st(tr10) := tpd_ODCK_DE_MODE6(tr10)+PERIOD*10; tpd_ODCK_DE_MODE7_st(tr01) := tpd_ODCK_DE_MODE7(tr01)+PERIOD*10; tpd_ODCK_DE_MODE7_st(tr10) := tpd_ODCK_DE_MODE7(tr10)+PERIOD*10; tpd_ODCK_DE_MODE8_st(tr01) := tpd_ODCK_DE_MODE8(tr01)+PERIOD*10; tpd_ODCK_DE_MODE8_st(tr10) := tpd_ODCK_DE_MODE8(tr10)+PERIOD*10; ELSE tpd_ODCK_DE_MODE1_st(tr01) := tpd_ODCK_DE_MODE1(tr01); tpd_ODCK_DE_MODE1_st(tr10) := tpd_ODCK_DE_MODE1(tr10); tpd_ODCK_DE_MODE2_st(tr01) := tpd_ODCK_DE_MODE2(tr01); tpd_ODCK_DE_MODE2_st(tr10) := tpd_ODCK_DE_MODE2(tr10); tpd_ODCK_DE_MODE3_st(tr01) := tpd_ODCK_DE_MODE3(tr01); tpd_ODCK_DE_MODE3_st(tr10) := tpd_ODCK_DE_MODE3(tr10); tpd_ODCK_DE_MODE4_st(tr01) := tpd_ODCK_DE_MODE4(tr01); tpd_ODCK_DE_MODE4_st(tr10) := tpd_ODCK_DE_MODE4(tr10); tpd_ODCK_DE_MODE5_st(tr01) := tpd_ODCK_DE_MODE5(tr01); tpd_ODCK_DE_MODE5_st(tr10) := tpd_ODCK_DE_MODE5(tr10); tpd_ODCK_DE_MODE6_st(tr01) := tpd_ODCK_DE_MODE6(tr01); tpd_ODCK_DE_MODE6_st(tr10) := tpd_ODCK_DE_MODE6(tr10); tpd_ODCK_DE_MODE7_st(tr01) := tpd_ODCK_DE_MODE7(tr01); tpd_ODCK_DE_MODE7_st(tr10) := tpd_ODCK_DE_MODE7(tr10); tpd_ODCK_DE_MODE8_st(tr01) := tpd_ODCK_DE_MODE8(tr01); tpd_ODCK_DE_MODE8_st(tr10) := tpd_ODCK_DE_MODE8(tr10); END IF; IF rising_edge(RXCinactive) THEN DEOut <= DE_zd; ELSE VitalPathDelay01Z( OutSignal => DEOut, OutSignalName => "DE", OutTemp => DE_zd, Mode => VitalTransport, IgnoreDefaultDelay => TRUE, GlitchData => DE_GlitchData, Paths => ( 0 => (InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE1_st, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='1' AND OCKINV = '0' ) OR (MODE = '1' AND SDAIn = '1' AND SCLIn = '0' )) AND (PDNeg = '1' AND PDONeg = '1')), 1 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE2_st, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='1' AND OCKINV = '1' ) OR (MODE = '1' AND SdaIn = '1' AND SCLIn = '1' ))AND (PDNeg = '1' AND PDONeg = '1')), 2 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE3_st, PathCondition => (MODE = '0' AND ST_BIT = '1' AND CKST ='0' AND OCKINV = '0' )AND (PDNeg = '1' AND PDONeg = '1') ), 3 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE4_st, PathCondition => (MODE = '0' AND ST_BIT = '1' AND CKST ='0' AND OCKINV = '1' )AND (PDNeg = '1' AND PDONeg = '1') ), 4 => (InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE5_st, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='1' AND OCKINV = '0' ) OR (MODE = '1' AND SDAIn = '0' AND SCLIn = '0' ))AND (PDNeg = '1' AND PDONeg = '1')), 5 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE6_st, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='1' AND OCKINV = '1' ) OR (MODE = '1' AND SDAIn = '0' AND SCLIn = '1' )) AND (PDNeg = '1' AND PDONeg = '1') ), 6 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE7_st, PathCondition => (MODE = '0' AND ST_BIT = '0' AND CKST ='0' AND OCKINV = '0' ) AND (PDNeg = '1' AND PDONeg = '1')), 7 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE8_st, PathCondition => (MODE = '0' AND ST_BIT = '0' AND CKST ='0' AND OCKINV = '1' ) AND (PDNeg = '1' AND PDONeg = '1') ), 8 =>(InputChangeTime => PDNeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => PDNeg = '0' OR PDONeg = '0' ), 9 =>(InputChangeTime => PDONeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => PDNeg = '0' OR PDONeg = '0' ) ) ); END IF; END PROCESS DE_Out; HSYNC_OUT: PROCESS(HSYNC_zd, RXCinactive) VARIABLE HSYNC_GlitchData : VitalGlitchDataType; VARIABLE HSYNCData : std_logic; BEGIN IF rising_edge(RXCinactive) THEN HSYNCOut <= HSYNC_zd; ELSE VitalPathDelay01Z( OutSignal => HSYNCOut, OutSignalName => "HSYNC", OutTemp => HSYNC_zd, Mode => VitalTransport, IgnoreDefaultDelay => TRUE, GlitchData => HSYNC_GlitchData, Paths => ( 0 => (InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE1, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='1' AND OCKINV = '0' ) OR (MODE = '1' AND SDAIn = '1' AND SCLIn = '0' ))AND (PDNeg = '1' AND PDONeg = '1') ), 1 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE2, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='1' AND OCKINV = '1' ) OR (MODE = '1' AND SDAIn = '1' AND SCLIn = '1' )) AND (PDNeg = '1' AND PDONeg = '1')), 2 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE3, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='0' AND OCKINV = '0' )) AND (PDNeg = '1' AND PDONeg = '1') ), 3 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE4, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='0' AND OCKINV = '1' ))AND (PDNeg = '1' AND PDONeg = '1') ), 4 => (InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE5, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='1' AND OCKINV = '0' ) OR (MODE = '1' AND SDAIn = '0' AND SCLIn = '0' )) AND (PDNeg = '1' AND PDONeg = '1')), 5 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE6, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='1' AND OCKINV = '1' ) OR (MODE = '1' AND SDAIn = '0' AND SCLIn = '1' )) AND (PDNeg = '1' AND PDONeg = '1') ), 6 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE7, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='0' AND OCKINV = '0' )) AND (PDNeg = '1' AND PDONeg = '1') ), 7 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE8, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='0' AND OCKINV = '1' )) AND (PDNeg = '1' AND PDONeg = '1') ), 8 =>(InputChangeTime => PDNeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ), 9 =>(InputChangeTime => PDONeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ) ) ); END IF; END PROCESS HSYNC_Out; VSYNC_OUT: PROCESS(VSYNC_zd, RXCinactive) VARIABLE VSYNC_GlitchData : VitalGlitchDataType; VARIABLE VSYNCData : std_logic; BEGIN IF rising_edge(RXCinactive) THEN VSYNCOut <= VSYNC_zd; ELSE VitalPathDelay01Z( OutSignal => VSYNCOut, OutSignalName => "VSYNC", OutTemp => VSYNC_zd, Mode => VitalTransport, IgnoreDefaultDelay => TRUE, GlitchData => VSYNC_GlitchData, Paths => ( 0 => (InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE1, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='1' AND OCKINV = '0' ) OR (MODE = '1' AND SDAIn = '1' AND SCLIn = '0' ))AND (PDNeg = '1' AND PDONeg = '1') ), 1 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE2, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='1' AND OCKINV = '1' ) OR (MODE = '1' AND SDAIn = '1' AND SCLIn = '1' )) AND (PDNeg = '1' AND PDONeg = '1')), 2 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE3, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='0' AND OCKINV = '0' )) AND (PDNeg = '1' AND PDONeg = '1') ), 3 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE4, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='0' AND OCKINV = '1' ))AND (PDNeg = '1' AND PDONeg = '1') ), 4 => (InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE5, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='1' AND OCKINV = '0' ) OR (MODE = '1' AND SDAIn = '0' AND SCLIn = '0' )) AND (PDNeg = '1' AND PDONeg = '1')), 5 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE6, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='1' AND OCKINV = '1' ) OR (MODE = '1' AND SDAIn = '0' AND SCLIn = '1' )) AND (PDNeg = '1' AND PDONeg = '1') ), 6 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE7, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='0' AND OCKINV = '0' )) AND (PDNeg = '1' AND PDONeg = '1') ), 7 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_DE_MODE8, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='0' AND OCKINV = '1' )) AND (PDNeg = '1' AND PDONeg = '1') ), 8 =>(InputChangeTime => PDNeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ), 9 =>(InputChangeTime => PDONeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ) ) ); END IF; END PROCESS VSYNC_Out; QE_Out_PathDelay_Gen : FOR i IN 0 TO 23 GENERATE PROCESS(QE_zd(i), RXCinactive) VARIABLE tpd_ODCK_QE_MODE1_st : VitalDelayType01Z; VARIABLE tpd_ODCK_QE_MODE2_st : VitalDelayType01Z; VARIABLE tpd_ODCK_QE_MODE3_st : VitalDelayType01Z; VARIABLE tpd_ODCK_QE_MODE4_st : VitalDelayType01Z; VARIABLE tpd_ODCK_QE_MODE5_st : VitalDelayType01Z; VARIABLE tpd_ODCK_QE_MODE6_st : VitalDelayType01Z; VARIABLE tpd_ODCK_QE_MODE7_st : VitalDelayType01Z; VARIABLE tpd_ODCK_QE_MODE8_st : VitalDelayType01Z; VARIABLE QE_GlitchData : VitalGlitchDataType; VARIABLE QEData : std_logic; BEGIN IF ((MODE = '0' AND STAG_OUT = '0') OR (MODE ='1' AND I2CMODENeg = '0')) AND PIXS = '1' THEN tpd_ODCK_QE_MODE1_st(tr01) := tpd_ODCK_QE_MODE1(tr01)+PERIOD*10; tpd_ODCK_QE_MODE1_st(tr10) := tpd_ODCK_QE_MODE1(tr10)+PERIOD*10; tpd_ODCK_QE_MODE2_st(tr01) := tpd_ODCK_QE_MODE2(tr01)+PERIOD*10; tpd_ODCK_QE_MODE2_st(tr10) := tpd_ODCK_QE_MODE2(tr10)+PERIOD*10; tpd_ODCK_QE_MODE3_st(tr01) := tpd_ODCK_QE_MODE3(tr01)+PERIOD*10; tpd_ODCK_QE_MODE3_st(tr10) := tpd_ODCK_QE_MODE3(tr10)+PERIOD*10; tpd_ODCK_QE_MODE4_st(tr01) := tpd_ODCK_QE_MODE4(tr01)+PERIOD*10; tpd_ODCK_QE_MODE4_st(tr10) := tpd_ODCK_QE_MODE4(tr10)+PERIOD*10; tpd_ODCK_QE_MODE5_st(tr01) := tpd_ODCK_QE_MODE5(tr01)+PERIOD*10; tpd_ODCK_QE_MODE5_st(tr10) := tpd_ODCK_QE_MODE5(tr10)+PERIOD*10; tpd_ODCK_QE_MODE6_st(tr01) := tpd_ODCK_QE_MODE6(tr01)+PERIOD*10; tpd_ODCK_QE_MODE6_st(tr10) := tpd_ODCK_QE_MODE6(tr10)+PERIOD*10; tpd_ODCK_QE_MODE7_st(tr01) := tpd_ODCK_QE_MODE7(tr01)+PERIOD*10; tpd_ODCK_QE_MODE7_st(tr10) := tpd_ODCK_QE_MODE7(tr10)+PERIOD*10; tpd_ODCK_QE_MODE8_st(tr01) := tpd_ODCK_QE_MODE8(tr01)+PERIOD*10; tpd_ODCK_QE_MODE8_st(tr10) := tpd_ODCK_QE_MODE8(tr10)+PERIOD*10; ELSE tpd_ODCK_QE_MODE1_st(tr01) := tpd_ODCK_QE_MODE1(tr01); tpd_ODCK_QE_MODE1_st(tr10) := tpd_ODCK_QE_MODE1(tr10); tpd_ODCK_QE_MODE2_st(tr01) := tpd_ODCK_QE_MODE2(tr01); tpd_ODCK_QE_MODE2_st(tr10) := tpd_ODCK_QE_MODE2(tr10); tpd_ODCK_QE_MODE3_st(tr01) := tpd_ODCK_QE_MODE3(tr01); tpd_ODCK_QE_MODE3_st(tr10) := tpd_ODCK_QE_MODE3(tr10); tpd_ODCK_QE_MODE4_st(tr01) := tpd_ODCK_QE_MODE4(tr01); tpd_ODCK_QE_MODE4_st(tr10) := tpd_ODCK_QE_MODE4(tr10); tpd_ODCK_QE_MODE5_st(tr01) := tpd_ODCK_QE_MODE5(tr01); tpd_ODCK_QE_MODE5_st(tr10) := tpd_ODCK_QE_MODE5(tr10); tpd_ODCK_QE_MODE6_st(tr01) := tpd_ODCK_QE_MODE6(tr01); tpd_ODCK_QE_MODE6_st(tr10) := tpd_ODCK_QE_MODE6(tr10); tpd_ODCK_QE_MODE7_st(tr01) := tpd_ODCK_QE_MODE7(tr01); tpd_ODCK_QE_MODE7_st(tr10) := tpd_ODCK_QE_MODE7(tr10); tpd_ODCK_QE_MODE8_st(tr01) := tpd_ODCK_QE_MODE8(tr01); tpd_ODCK_QE_MODE8_st(tr10) := tpd_ODCK_QE_MODE8(tr10); END IF; IF rising_edge(RXCinactive) THEN QEOut(i) <= QE_zd(i); ELSE VitalPathDelay01Z( OutSignal => QEOut(i), OutSignalName => "QE", OutTemp => QE_zd(i), Mode => VitalTransport, IgnoreDefaultDelay => TRUE, GlitchData => QE_GlitchData, Paths => ( 0 => (InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE1_st, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='1' AND OCKINV = '0') OR (MODE ='1' AND SDAIn = '1' AND SCLIn = '0' ))AND (PDNeg = '1' AND PDONeg = '1')), 1 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE2_st, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='1' AND OCKINV = '1') OR (MODE ='1'AND SDAIn = '1' AND SCLIn = '1' )) AND (PDNeg = '1' AND PDONeg = '1')), 2 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE3_st, PathCondition => (MODE = '0' AND ST_BIT = '1' AND CKST ='0' AND OCKINV = '0') AND (PDNeg = '1' AND PDONeg = '1') ), 3 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE4_st, PathCondition => (MODE = '0' AND ST_BIT = '1' AND CKST ='0' AND OCKINV = '1') AND (PDNeg = '1' AND PDONeg = '1') ), 4 => (InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE5_st, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='1' AND OCKINV = '0') OR (MODE = '1' AND SDAIn = '0' AND SCLIn = '0')) AND (PDNeg = '1' AND PDONeg = '1')), 5 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE6_st, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='1' AND OCKINV = '1') OR (MODE = '1' AND SDAIn = '0' AND SCLIn = '1' ))AND (PDNeg = '1' AND PDONeg = '1') ), 6 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE7_st, PathCondition => (MODE = '0' AND ST_BIT = '0' AND CKST ='0' AND OCKINV = '0')AND (PDNeg = '1' AND PDONeg = '1') ), 7 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE8_st, PathCondition => (MODE = '0' AND ST_BIT = '0' AND CKST ='0' AND OCKINV = '1')AND (PDNeg = '1' AND PDONeg = '1') ), 8 =>(InputChangeTime => PDNeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ), 9 =>(InputChangeTime => PDONeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ) ) ); END IF; END PROCESS; END GENERATE QE_Out_PathDelay_Gen; QO_Out_PathDelay_Gen : FOR i IN 0 TO 23 GENERATE PROCESS(QO_zd(i), RXCinactive) VARIABLE QO_GlitchData : VitalGlitchDataType; VARIABLE QOData : std_logic; BEGIN IF rising_edge(RXCinactive) THEN QOOut(i) <= QO_zd(i); ELSE VitalPathDelay01Z( OutSignal => QOOut(i), OutSignalName => "QO", OutTemp => QO_zd(i), Mode => VitalTransport, IgnoreDefaultDelay => TRUE, GlitchData => QO_GlitchData, Paths => ( 0 => (InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE1, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='1' AND OCKINV = '0' ) OR (MODE = '1' AND SDAIn = '1' AND SCLIn = '0' ))AND (PDNeg = '1' AND PDONeg = '1') ), 1 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE2, PathCondition => ((MODE = '0' AND ST_BIT = '1' AND CKST ='1' AND OCKINV = '1' ) OR (MODE = '1' AND SdaIn = '1' AND SCLIn = '1' )) AND (PDNeg = '1' AND PDONeg = '1')), 2 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE3, PathCondition => (MODE = '0' AND ST_BIT = '1' AND CKST ='0' AND OCKINV = '0' ) AND (PDNeg = '1' AND PDONeg = '1') ), 3 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE4, PathCondition => (MODE = '0' AND ST_BIT = '1' AND CKST ='0' AND OCKINV = '1' ) AND (PDNeg = '1' AND PDONeg = '1') ), 4 => (InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE5, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='1' AND OCKINV = '0' ) OR (MODE = '1' AND SDAIn = '0' AND SCLIn = '0' )) AND (PDNeg = '1' AND PDONeg = '1')), 5 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE6, PathCondition => ((MODE = '0' AND ST_BIT = '0' AND CKST ='1' AND OCKINV = '1' ) OR (MODE = '1' AND SDAIn = '0' AND SCLIn = '1' )) AND (PDNeg = '1' AND PDONeg = '1') ), 6 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE7, PathCondition => (MODE = '0' AND ST_BIT = '0' AND CKST ='0' AND OCKINV = '0' ) AND (PDNeg = '1' AND PDONeg = '1') ), 7 =>(InputChangeTime => ODCKzd'LAST_EVENT, PathDelay => tpd_ODCK_QE_MODE8, PathCondition => (MODE = '0' AND ST_BIT = '0' AND CKST ='0' AND OCKINV = '1' ) AND (PDNeg = '1' AND PDONeg = '1') ), 8 =>(InputChangeTime => PDNeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ), 9 =>(InputChangeTime => PDONeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ) ) ); END IF; END PROCESS; END GENERATE QO_Out_PathDelay_Gen; CTL1_OUT: PROCESS(CTL1_zd, RXCinactive) VARIABLE CTL1_GlitchData : VitalGlitchDataType; BEGIN IF rising_edge(RXCinactive) THEN CTL1Out <= CTL1_zd; ELSE VitalPathDelay01Z( OutSignal => CTL1Out, OutSignalName => "CTL1", OutTemp => CTL1_zd, Mode => VitalTransport, IgnoreDefaultDelay => TRUE, GlitchData => CTL1_GlitchData, Paths => ( 1 =>(InputChangeTime => PDNeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ) ) ); END IF; END PROCESS CTL1_Out; CTL2_OUT: PROCESS(CTL2_zd, RXCinactive) VARIABLE CTL2_GlitchData : VitalGlitchDataType; BEGIN IF rising_edge(RXCinactive) THEN CTL2Out <= CTL2_zd; ELSE VitalPathDelay01Z( OutSignal => CTL2Out, OutSignalName => "CTL2", OutTemp => CTL2_zd, Mode => VitalTransport, IgnoreDefaultDelay => TRUE, GlitchData => CTL2_GlitchData, Paths => ( 1 =>(InputChangeTime => PDNeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ), 2 =>(InputChangeTime => PDONeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ) ) ); END IF; END PROCESS CTL2_Out; CTL3_OUT: PROCESS(CTL3_zd, RXCinactive) VARIABLE CTL3_GlitchData : VitalGlitchDataType; BEGIN IF rising_edge(RXCinactive) THEN CTL3Out <= CTL3_zd; ELSE VitalPathDelay01Z( OutSignal => CTL3Out, OutSignalName => "CTL3", OutTemp => CTL3_zd, Mode => VitalTransport, IgnoreDefaultDelay => TRUE, GlitchData => CTL3_GlitchData, Paths => ( 1 =>(InputChangeTime => PDNeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ), 2 =>(InputChangeTime => PDONeg'LAST_EVENT, PathDelay => tpd_PDNeg_DE, PathCondition => TRUE ) ) ); END IF; END PROCESS CTL3_Out; --------------------------------------- -------------I2C----------------------- --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS(SCLIn, SDAIn) -- Timing Check Variables VARIABLE Tviol_SDAS_SCL : X01 := '0'; VARIABLE TD_SDAS_SCL : VitalTimingDataType; VARIABLE Tviol_SDAS_SCL_FAST : X01 := '0'; VARIABLE TD_SDAS_SCL_FAST : VitalTimingDataType; VARIABLE Tviol_SDAH_SCL : X01 := '0'; VARIABLE TD_SDAH_SCL : VitalTimingDataType; VARIABLE Tviol_SDAH_SCL_FAST : X01 := '0'; VARIABLE TD_SDAH_SCL_FAST : VitalTimingDataType; VARIABLE Tviol_SCL_SDAS : X01 := '0'; VARIABLE TD_SCL_SDAS : VitalTimingDataType; VARIABLE Tviol_SCL_SDAS_FAST : X01 := '0'; VARIABLE TD_SCL_SDAS_FAST : VitalTimingDataType; VARIABLE Tviol_SCL_SDAP : X01 := '0'; VARIABLE TD_SCL_SDAP : VitalTimingDataType; VARIABLE Tviol_SCL_SDAP_FAST : X01 := '0'; VARIABLE TD_SCL_SDAP_FAST : VitalTimingDataType; VARIABLE Pviol_SCL : X01 := '0'; VARIABLE PD_SCL : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_SCL_FAST : X01 := '0'; VARIABLE PD_SCL_FAST : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Data setup time, standard mode VitalSetupHoldCheck ( TestSignal => SDAIn, TestSignalName => "SDA", RefSignal => SCLIn, RefSignalName => "SCL", SetupHigh => tsetup_SDA_SCL_FASTMODE_EQ_0_noedge_posedge, SetupLow => tsetup_SDA_SCL_FASTMODE_EQ_0_noedge_posedge, CheckEnabled => FASTMODE = '0' AND MODE = '0' AND I2CMODENeg ='0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SDAS_SCL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDAS_SCL ); -- Data setup time, fast mode VitalSetupHoldCheck ( TestSignal => SDAIn, TestSignalName => "SDA", RefSignal => SCLIn, RefSignalName => "SCL", SetupHigh => tsetup_SDA_SCL_FASTMODE_EQ_1_noedge_posedge, SetupLow => tsetup_SDA_SCL_FASTMODE_EQ_1_noedge_posedge, CheckEnabled => FASTMODE = '1' AND MODE = '0' AND I2CMODENeg ='0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SDAS_SCL_FAST, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDAS_SCL_FAST ); -- Data Hold Time, standard mode VitalSetupHoldCheck ( TestSignal => SDAIn, TestSignalName => "SDA", RefSignal => SCLIn, RefSignalName => "SCL", HoldHigh => thold_SDA_SCL_FASTMODE_EQ_0_noedge_negedge, HoldLow => thold_SDA_SCL_FASTMODE_EQ_0_noedge_negedge, CheckEnabled => FASTMODE = '0' AND MODE = '0' AND I2CMODENeg ='0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SDAH_SCL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDAH_SCL ); -- Data Hold Time, fast mode VitalSetupHoldCheck ( TestSignal => SDAIn, TestSignalName => "SDA", RefSignal => SCLIn, RefSignalName => "SCL", HoldHigh => thold_SDA_SCL_FASTMODE_EQ_1_noedge_negedge, HoldLow => thold_SDA_SCL_FASTMODE_EQ_1_noedge_negedge, CheckEnabled => FASTMODE = '1' AND MODE = '0' AND I2CMODENeg ='0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SDAH_SCL_FAST, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDAH_SCL_FAST ); VitalSetupHoldCheck ( TestSignal => SCLIn, TestSignalName => "SCL", RefSignal => SDAIn, RefSignalName => "SDA", SetupHigh => tsetup_SCL_SDA_FASTMODE_EQ_0_noedge_negedge, HoldHigh => thold_SCL_SDA_FASTMODE_EQ_0_noedge_negedge, CheckEnabled => FASTMODE = '0' AND MODE = '0' AND I2CMODENeg ='0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SCL_SDAS, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SCL_SDAS ); VitalSetupHoldCheck ( TestSignal => SCLIn, TestSignalName => "SCL", RefSignal => SDAIn, RefSignalName => "SDA", SetupHigh => tsetup_SCL_SDA_FASTMODE_EQ_1_noedge_negedge, HoldHigh => thold_SCL_SDA_FASTMODE_EQ_1_noedge_negedge, CheckEnabled => FASTMODE = '1' AND MODE = '0' AND I2CMODENeg ='0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SCL_SDAS_FAST, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SCL_SDAS_FAST ); -- Set up time for a STOP, standard mode VitalSetupHoldCheck ( TestSignal => SCLIn, TestSignalName => "SCL", RefSignal => SDAIn, RefSignalName => "SDA", SetupHigh => tsetup_SCL_SDA_FASTMODE_EQ_0_noedge_posedge, CheckEnabled => FASTMODE = '0' AND MODE = '0' AND I2CMODENeg ='0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SCL_SDAP, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SCL_SDAP ); -- Set up time for a STOP, fast mode VitalSetupHoldCheck ( TestSignal => SCLIn, TestSignalName => "SCL", RefSignal => SDAIn, RefSignalName => "SDA", SetupHigh => tsetup_SCL_SDA_FASTMODE_EQ_1_noedge_posedge, CheckEnabled => FASTMODE = '1' AND MODE = '0' AND I2CMODENeg ='0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SCL_SDAP_FAST, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SCL_SDAP_FAST ); -- standard mode VitalPeriodPulseCheck ( TestSignal => SCLIn, TestSignalName => "SCL", Period => tperiod_SCL_FASTMODE_EQ_0, PulseWidthLow => tpw_SCL_FASTMODE_EQ_0_negedge, PulseWidthHigh => tpw_SCL_FASTMODE_EQ_0_posedge, PeriodData => PD_SCL, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCL, HeaderMsg => InstancePath & PartID, CheckEnabled => FASTMODE = '0' AND MODE = '0' AND I2CMODENeg = '0'); -- fast mode VitalPeriodPulseCheck ( TestSignal => SCLIn, TestSignalName => "SCL", Period => tperiod_SCL_FASTMODE_EQ_1, PulseWidthLow => tpw_SCL_FASTMODE_EQ_1_negedge, PulseWidthHigh => tpw_SCL_FASTMODE_EQ_1_posedge, PeriodData => PD_SCL_FAST, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCL_FAST, HeaderMsg => InstancePath & PartID, CheckEnabled => FASTMODE = '1' AND MODE = '0' AND I2CMODENeg = '0'); Violation := Tviol_SDAS_SCL OR Tviol_SDAH_SCL OR Tviol_SCL_SDAS OR Tviol_SCL_SDAP OR Pviol_SCL OR Tviol_SDAS_SCL_FAST OR Tviol_SDAH_SCL_FAST OR Tviol_SCL_SDAS_FAST OR Tviol_SCL_SDAP_FAST OR Pviol_SCL_FAST; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS VITALTimingCheck; --------------------------------- -- detects START condition --------------------------------- start_proc: PROCESS(SDAIn, SCLIn) BEGIN IF falling_edge(SDAIn) AND SCLIn /= '0' THEN start <= '1', '0' AFTER 1 ns; END IF; END PROCESS start_proc; --------------------------------- -- detects STOP condition --------------------------------- stop_proc: PROCESS(SDAIn, SCLIn) BEGIN IF rising_edge(SDAIn) AND SCLIn /= '0' THEN IF standard_mode = TRUE THEN stop_del <= '1' AFTER tdevice_TBUF_S, '0' AFTER tdevice_TBUF_S + 1 ns; ELSE stop_del <= '1' AFTER tdevice_TBUF_F, '0' AFTER tdevice_TBUF_F + 1 ns; END IF; stop <= '1', '0' AFTER 1 ns; END IF; END PROCESS stop_proc; --------------------------------- -- bus busy --------------------------------- bus_busy_del_proc: PROCESS(start, stop_del) BEGIN IF start = '1' THEN busy_del <= '1'; ELSIF stop_del = '1' THEN busy_del <= '0'; END IF; END PROCESS bus_busy_del_proc; --------------------------------- -- bus busy --------------------------------- bus_busy_proc: PROCESS(start, stop) BEGIN IF start = '1' THEN busy <= '1'; ELSIF stop = '1' THEN busy <= '0'; END IF; END PROCESS bus_busy_proc; invalid_stop_start: PROCESS(busy_del, busy) BEGIN IF busy'EVENT AND busy = '1' AND NOT(busy_del'EVENT) AND busy = busy_del THEN REPORT("INVALID START CONDITION"); END IF; END PROCESS invalid_stop_start; clk_cnt_proc: PROCESS(Start, stop_del, SCLIn) BEGIN IF Start = '1' OR stop_del = '1' THEN clk_cnt <= 0 AFTER 1 ns; ELSIF rising_edge(SCLIn) THEN clk_cnt <= (clk_cnt + 1) MOD 9 AFTER 1 ns; END IF; END PROCESS clk_cnt_proc; ---------------------------------------------------------------------------- -- sequential process for reset control and FSM state transition ---------------------------------------------------------------------------- StateTransition : PROCESS(SCLIn, stop_del, PDNeg, MODE, I2CMODENeg) BEGIN IF falling_edge(PDNeg) OR rising_edge(MODE) THEN VND_IDL := "00000001"; VND_IDH := "00000000"; DEV_IDL := "00000000"; DEV_IDH := "00000000"; DEV_REV := "00000000"; EQ_DATA_r := "00001101"; REG_A := "00100100"; REG_B := "00000000"; END IF; IF (MODE = '0' AND I2CMODENeg = '0') THEN IF stop_del = '1' AND Byte_received = FALSE THEN current_state <= IDLE; ELSIF rising_edge(SCLIn) THEN current_state <= next_state; END IF; END IF; END PROCESS StateTransition; --------------------------------------------------------------------------- -- Main Behavior Process -- combinational process for next state generation --------------------------------------------------------------------------- StateGen :PROCESS(Start, stop_del, stop, clk_cnt, wr_out) BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- CASE current_state IS WHEN IDLE => IF Start = '1' AND Start'EVENT THEN next_state <= CONTROL_BYTE; END IF; WHEN CONTROL_BYTE => IF (rising_edge(stop_del)) THEN next_state <= IDLE; ELSE IF (clk_cnt = 8 AND clk_cnt'EVENT) THEN IF Slave_ID = TRUE THEN IF SDAIn = '1' THEN next_state <= READ;--read ELSE next_state <= COMMAND;--write END IF; ELSE next_state <= IDLE; END IF; END IF; END IF; WHEN COMMAND => IF (rising_edge(stop_del)) THEN next_state <= IDLE; ELSE IF (clk_cnt = 8 AND clk_cnt'EVENT) THEN IF to_nat(command_byte(6 downto 0) & SDAIn) <15 THEN next_state <= WRITE; ELSE next_state <= IDLE; END IF; END IF; END IF; WHEN WRITE => IF (Start'EVENT AND Start = '1' AND wr_in = '0') THEN next_state <= CONTROL_BYTE; ELSIF (stop'EVENT AND stop = '1') THEN IF (Byte_received = TRUE and clk_cnt = 1) THEN next_state <= WRITE; ELSE next_state <= IDLE; END IF; ELSIF (wr_out = '1') THEN next_state <= IDLE; END IF; WHEN READ => IF (clk_cnt'EVENT ) THEN --first bit after ACK IF (clk_cnt = 0 AND Firstbyte_sent = TRUE) THEN --not acknowladge from MASTER IF SDAIn = '1' THEN next_state <= IDLE; END IF; END IF; END IF; END CASE; END PROCESS StateGen; --------------------------------------------------------------------------- --FSM Output generation and general funcionality --------------------------------------------------------------------------- Functional : PROCESS(current_state, stop, clk_cnt, wr_out, SCLIn) VARIABLE command_byte_tmp : std_logic_vector(7 downto 0); VARIABLE data_byte_tmp : std_logic_vector(7 downto 0); VARIABLE data_byte : std_logic_vector(7 downto 0); VARIABLE Address_byte : INTEGER := 0; VARIABLE num : INTEGER := 7; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- CASE current_state IS WHEN IDLE => Slave_ID <= FALSE; Firstbyte_sent <= FALSE; Release_SDA <= FALSE; Byte_received <= FALSE; num := 7; IF falling_edge(SCLIn) THEN SDA_zd <= 'Z'; END IF; WHEN CONTROL_BYTE => Byte_received <= FALSE; Firstbyte_sent <= FALSE; Release_SDA <= FALSE; IF (clk_cnt /= 0 AND clk_cnt'EVENT) THEN first_byte <= first_byte(8 downto 0) & SDAIn; END IF; IF (clk_cnt = 7 AND clk_cnt'EVENT) THEN IF (first_byte(5 downto 0) & SDAIn = "1110110") THEN --0x76 Slave_ID <= TRUE; ELSE Slave_ID <= FALSE; END IF; END IF; IF falling_edge(SCLIn) THEN IF clk_cnt /= 8 THEN SDA_zd <= 'Z'; ELSE IF Slave_ID THEN SDA_zd <= '0'; ELSE SDA_zd <= 'Z'; END IF; END IF; END IF; WHEN COMMAND => IF (clk_cnt /= 0 AND clk_cnt'EVENT) THEN command_byte <= command_byte(8 downto 0) & SDAIn; command_byte_tmp := command_byte_tmp(6 downto 0) & SDAIn; END IF; IF (clk_cnt = 8 AND clk_cnt'EVENT) THEN Address_byte := to_nat(command_byte_tmp); IF (to_nat(command_byte_tmp) > 15) THEN REPORT "invalid register address"; END IF; END IF; IF falling_edge(SCLIn) THEN IF clk_cnt /= 8 THEN SDA_zd <= 'Z'; ELSE SDA_zd <= '0'; END IF; END IF; WHEN WRITE => IF (clk_cnt /= 0 AND clk_cnt'EVENT AND wr_in= '0') THEN data_byte := data_byte(6 downto 0)& SDAIn; END IF; IF (clk_cnt = 8 AND clk_cnt'EVENT AND wr_in= '0') THEN Byte_received <= TRUE; data_byte_tmp := data_byte; END IF; IF (stop'EVENT AND stop = '1' AND clk_cnt = 1 AND Byte_received = TRUE) THEN wr_in <= '1'; END IF; IF (wr_out = '1') THEN wr_in <= '0'; IF Address_byte = 9 THEN EQ_DATA_R := data_byte_tmp(7 downto 0); ELSIF Address_byte = 10 THEN REG_A := data_byte_tmp(7 downto 0); ELSIF Address_byte = 11 THEN REG_B := data_byte_tmp(7 downto 0); END IF; END IF; IF falling_edge(SCLIn) THEN IF wr_in = '0' THEN IF clk_cnt /= 8 THEN SDA_zd <= 'Z'; ELSE SDA_zd <= '0'; END IF; ELSE SDA_zd <= 'Z'; END IF; END IF; WHEN READ => IF (clk_cnt'EVENT AND clk_cnt = 8) THEN Firstbyte_sent <= TRUE; END IF; IF (clk_cnt'EVENT ) THEN --first bit after ACK IF (clk_cnt = 0 AND Firstbyte_sent = TRUE) THEN --not acknowladge from MASTER IF SDAIn = '1' THEN Release_SDA <= TRUE; -- release SDA END IF; ELSE Release_SDA <= FALSE; END IF; END IF; IF falling_edge(SCLIn) THEN IF Release_SDA = TRUE THEN SDA_zd <= 'Z'; ELSIF clk_cnt /= 8 THEN CASE Address_byte IS WHEN 0 => SDA_zd <= VND_IDL(num); WHEN 1 => SDA_zd <= VND_IDH(num); WHEN 2 => SDA_zd <= DEV_IDL(num); WHEN 3 => SDA_zd <= DEV_IDH(num); WHEN 4 => SDA_zd <= DEV_REV(num); WHEN 9 => SDA_zd <= EQ_DATA_R(num); WHEN 10 => SDA_zd <= REG_A(num); WHEN 11 => SDA_zd <= REG_B(num); WHEN others => null; END CASE; num := (num+7) MOD 8; ELSE SDA_zd <= 'Z'; END IF; END IF; END CASE; END PROCESS Functional; delay_SDA: PROCESS(SDA_zd) VARIABLE SDA_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay ( OutSignal => SDAOut, OutSignalName => "SDAOut", OutTemp => SDA_zd, GlitchData => SDA_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SCLIn'LAST_EVENT, PathDelay => tpd_SCL_SDA, PathCondition => FASTMODE = '1' AND SCLIn = '0'), 1 => (InputChangeTime => SCLIn'LAST_EVENT, PathDelay => tpd_SCL_SDA, PathCondition => FASTMODE = '0' AND SCLIn = '0') ) ); END PROCESS delay_SDA; END BLOCK; END vhdl_behavioral;