-------------------------------------------------------------------------------- -- File Name: sii1160.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2005-2008 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 S.Gmitrovic 05 Aug 17 Initial release -- V1.1 R. Munden 08 Sep 28 Corrected timing generic names -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IF -- Technology: -- Part: SiI1160 -- Description: PanelLink Transmitter -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY sii1160 IS GENERIC ( -- tipd delays: interconnect path delays tipd_DIE0 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE1 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE2 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE3 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE4 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE5 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE6 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE7 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE8 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE9 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE10 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE11 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE12 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE13 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE14 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE15 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE16 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE17 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE18 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE19 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE20 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE21 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE22 : VitalDelayType01 := VitalZeroDelay01; tipd_DIE23 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO0 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO1 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO2 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO3 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO4 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO5 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO6 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO7 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO8 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO9 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO10 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO11 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO12 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO13 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO14 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO15 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO16 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO17 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO18 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO19 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO20 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO21 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO22 : VitalDelayType01 := VitalZeroDelay01; tipd_DIO23 : VitalDelayType01 := VitalZeroDelay01; tipd_PDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_IDCK : VitalDelayType01 := VitalZeroDelay01; tipd_DE : VitalDelayType01 := VitalZeroDelay01; tipd_HSYNC : VitalDelayType01 := VitalZeroDelay01; tipd_VSYNC : VitalDelayType01 := VitalZeroDelay01; tipd_EDGE : VitalDelayType01 := VitalZeroDelay01; tipd_PIXS : VitalDelayType01 := VitalZeroDelay01; tipd_CTL1 : VitalDelayType01 := VitalZeroDelay01; tipd_CTL2 : VitalDelayType01 := VitalZeroDelay01; tipd_CTL3 : VitalDelayType01 := VitalZeroDelay01; tipd_ISELNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SCL : VitalDelayType01 := VitalZeroDelay01; tipd_SDA : VitalDelayType01 := VitalZeroDelay01; -- tsetup values: setup times tsetup_DIE0_IDCK : VitalDelayType := UnitDelay; -- thold values: hold times thold_DIE0_IDCK : VitalDelayType := UnitDelay; -- tperiod pulse width values tpw_IDCK_negedge : VitalDelayType := UnitDelay; tpw_IDCK_posedge : VitalDelayType := UnitDelay; tperiod_IDCK_PIXS_EQ_1 : VitalDelayType := UnitDelay; tperiod_IDCK_PIXS_EQ_0 : VitalDelayType := UnitDelay; -- tpd values I2C tpd_SCL_SDA : VitalDelayType := UnitDelay; -- tSU:DAT I2C tsetup_SDA_SCL_FASTMODE_EQ_1_noedge_posedge : VitalDelayType := UnitDelay; tsetup_SDA_SCL_FASTMODE_EQ_0_noedge_posedge : VitalDelayType := UnitDelay; -- tSU:STA I2C tsetup_SCL_SDA_FASTMODE_EQ_1_noedge_negedge : VitalDelayType := UnitDelay; tsetup_SCL_SDA_FASTMODE_EQ_0_noedge_negedge : VitalDelayType := UnitDelay; -- tSU:STO I2C tsetup_SCL_SDA_FASTMODE_EQ_1_noedge_posedge : VitalDelayType := UnitDelay; tsetup_SCL_SDA_FASTMODE_EQ_0_noedge_posedge : VitalDelayType := UnitDelay; -- thold values: hold times I2C -- tHD:DAT thold_SDA_SCL_FASTMODE_EQ_1_noedge_negedge : VitalDelayType := UnitDelay; thold_SDA_SCL_FASTMODE_EQ_0_noedge_negedge : VitalDelayType := UnitDelay; -- tHD:STA thold_SCL_SDA_FASTMODE_EQ_1_noedge_negedge : VitalDelayType := UnitDelay; thold_SCL_SDA_FASTMODE_EQ_0_noedge_negedge : VitalDelayType := UnitDelay; -- tpw values: pulse widths I2C tpw_SCL_FASTMODE_EQ_1_posedge : VitalDelayType := UnitDelay; tpw_SCL_FASTMODE_EQ_0_posedge : VitalDelayType := UnitDelay; tpw_SCL_FASTMODE_EQ_1_negedge : VitalDelayType := UnitDelay; tpw_SCL_FASTMODE_EQ_0_negedge : VitalDelayType := UnitDelay; -- tperiod min (calculated as 1/max freq) I2C tperiod_SCL_FASTMODE_EQ_1 : VitalDelayType := UnitDelay; tperiod_SCL_FASTMODE_EQ_0 : VitalDelayType := UnitDelay; -- tdevice values: values for internal delays I2C tdevice_TBUF_S : VitalDelayType := 4.7 us;-- standard mode tdevice_TBUF_F : VitalDelayType := 1.3 us;-- fast mode tdevice_PROGTIME : VitalDelayType := UnitDelay; -- i2c specific generic : if device work in fast or standard mode standard_mode : BOOLEAN := TRUE; -- generic control parameters InstancePath : STRING:= DefaultInstancePath; TimingChecksOn : BOOLEAN:= DefaultTimingChecks; MsgOn : BOOLEAN:= DefaultMsgOn; XOn : BOOLEAN:= DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- For FMF SDF technology file usage TimingModel : STRING:= DefaultTimingModel ); PORT ( DIE0 : IN std_ulogic := 'U'; DIE1 : IN std_ulogic := 'U'; DIE2 : IN std_ulogic := 'U'; DIE3 : IN std_ulogic := 'U'; DIE4 : IN std_ulogic := 'U'; DIE5 : IN std_ulogic := 'U'; DIE6 : IN std_ulogic := 'U'; DIE7 : IN std_ulogic := 'U'; DIE8 : IN std_ulogic := 'U'; DIE9 : IN std_ulogic := 'U'; DIE10 : IN std_ulogic := 'U'; DIE11 : IN std_ulogic := 'U'; DIE12 : IN std_ulogic := 'U'; DIE13 : IN std_ulogic := 'U'; DIE14 : IN std_ulogic := 'U'; DIE15 : IN std_ulogic := 'U'; DIE16 : IN std_ulogic := 'U'; DIE17 : IN std_ulogic := 'U'; DIE18 : IN std_ulogic := 'U'; DIE19 : IN std_ulogic := 'U'; DIE20 : IN std_ulogic := 'U'; DIE21 : IN std_ulogic := 'U'; DIE22 : IN std_ulogic := 'U'; DIE23 : IN std_ulogic := 'U'; DIO0 : IN std_ulogic := 'U'; DIO1 : IN std_ulogic := 'U'; DIO2 : IN std_ulogic := 'U'; DIO3 : IN std_ulogic := 'U'; DIO4 : IN std_ulogic := 'U'; DIO5 : IN std_ulogic := 'U'; DIO6 : IN std_ulogic := 'U'; DIO7 : IN std_ulogic := 'U'; DIO8 : IN std_ulogic := 'U'; DIO9 : IN std_ulogic := 'U'; DIO10 : IN std_ulogic := 'U'; DIO11 : IN std_ulogic := 'U'; DIO12 : IN std_ulogic := 'U'; DIO13 : IN std_ulogic := 'U'; DIO14 : IN std_ulogic := 'U'; DIO15 : IN std_ulogic := 'U'; DIO16 : IN std_ulogic := 'U'; DIO17 : IN std_ulogic := 'U'; DIO18 : IN std_ulogic := 'U'; DIO19 : IN std_ulogic := 'U'; DIO20 : IN std_ulogic := 'U'; DIO21 : IN std_ulogic := 'U'; DIO22 : IN std_ulogic := 'U'; DIO23 : IN std_ulogic := 'U'; IDCK : IN std_ulogic := 'U'; DE : IN std_ulogic := 'U'; HSYNC : IN std_ulogic := 'U'; VSYNC : IN std_ulogic := 'U'; EDGE : IN std_ulogic := 'U'; PIXS : IN std_ulogic := 'U'; CTL1 : IN std_ulogic := 'U'; CTL2 : IN std_ulogic := 'U'; CTL3 : IN std_ulogic := 'U'; PDNeg : IN std_ulogic := 'U'; TX0 : OUT std_ulogic := 'U'; TX0Neg : OUT std_ulogic := 'U'; TX1 : OUT std_ulogic := 'U'; TX1Neg : OUT std_ulogic := 'U'; TX2 : OUT std_ulogic := 'U'; TX2Neg : OUT std_ulogic := 'U'; TXC : OUT std_ulogic := 'U'; TXCNeg : OUT std_ulogic := 'U'; ISELNeg : IN std_ulogic := 'U'; MSEN : OUT std_ulogic := 'U'; SCL : IN std_ulogic := 'U'; SDA : INOUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of sii1160 : ENTITY IS TRUE; END sii1160; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of sii1160 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "SiI1160"; SIGNAL DIE0_ipd : std_ulogic := 'U'; SIGNAL DIE1_ipd : std_ulogic := 'U'; SIGNAL DIE2_ipd : std_ulogic := 'U'; SIGNAL DIE3_ipd : std_ulogic := 'U'; SIGNAL DIE4_ipd : std_ulogic := 'U'; SIGNAL DIE5_ipd : std_ulogic := 'U'; SIGNAL DIE6_ipd : std_ulogic := 'U'; SIGNAL DIE7_ipd : std_ulogic := 'U'; SIGNAL DIE8_ipd : std_ulogic := 'U'; SIGNAL DIE9_ipd : std_ulogic := 'U'; SIGNAL DIE10_ipd : std_ulogic := 'U'; SIGNAL DIE11_ipd : std_ulogic := 'U'; SIGNAL DIE12_ipd : std_ulogic := 'U'; SIGNAL DIE13_ipd : std_ulogic := 'U'; SIGNAL DIE14_ipd : std_ulogic := 'U'; SIGNAL DIE15_ipd : std_ulogic := 'U'; SIGNAL DIE16_ipd : std_ulogic := 'U'; SIGNAL DIE17_ipd : std_ulogic := 'U'; SIGNAL DIE18_ipd : std_ulogic := 'U'; SIGNAL DIE19_ipd : std_ulogic := 'U'; SIGNAL DIE20_ipd : std_ulogic := 'U'; SIGNAL DIE21_ipd : std_ulogic := 'U'; SIGNAL DIE22_ipd : std_ulogic := 'U'; SIGNAL DIE23_ipd : std_ulogic := 'U'; SIGNAL DIO0_ipd : std_ulogic := 'U'; SIGNAL DIO1_ipd : std_ulogic := 'U'; SIGNAL DIO2_ipd : std_ulogic := 'U'; SIGNAL DIO3_ipd : std_ulogic := 'U'; SIGNAL DIO4_ipd : std_ulogic := 'U'; SIGNAL DIO5_ipd : std_ulogic := 'U'; SIGNAL DIO6_ipd : std_ulogic := 'U'; SIGNAL DIO7_ipd : std_ulogic := 'U'; SIGNAL DIO8_ipd : std_ulogic := 'U'; SIGNAL DIO9_ipd : std_ulogic := 'U'; SIGNAL DIO10_ipd : std_ulogic := 'U'; SIGNAL DIO11_ipd : std_ulogic := 'U'; SIGNAL DIO12_ipd : std_ulogic := 'U'; SIGNAL DIO13_ipd : std_ulogic := 'U'; SIGNAL DIO14_ipd : std_ulogic := 'U'; SIGNAL DIO15_ipd : std_ulogic := 'U'; SIGNAL DIO16_ipd : std_ulogic := 'U'; SIGNAL DIO17_ipd : std_ulogic := 'U'; SIGNAL DIO18_ipd : std_ulogic := 'U'; SIGNAL DIO19_ipd : std_ulogic := 'U'; SIGNAL DIO20_ipd : std_ulogic := 'U'; SIGNAL DIO21_ipd : std_ulogic := 'U'; SIGNAL DIO22_ipd : std_ulogic := 'U'; SIGNAL DIO23_ipd : std_ulogic := 'U'; SIGNAL IDCK_ipd : std_ulogic := 'U'; SIGNAL DE_ipd : std_ulogic := 'U'; SIGNAL HSYNC_ipd : std_ulogic := 'U'; SIGNAL VSYNC_ipd : std_ulogic := 'U'; SIGNAL EDGE_ipd : std_ulogic := 'U'; SIGNAL PIXS_ipd : std_ulogic := '0'; SIGNAL CTL1_ipd : std_ulogic := 'U'; SIGNAL CTL2_ipd : std_ulogic := 'U'; SIGNAL CTL3_ipd : std_ulogic := 'U'; SIGNAL PDNeg_ipd : std_ulogic := 'U'; SIGNAL ISELNeg_ipd : std_ulogic := 'U'; SIGNAL SCL_ipd : std_ulogic := 'U'; SIGNAL SDA_ipd : std_ulogic := 'U'; SIGNAL buf_in : std_logic := '0'; SIGNAL buf_out : std_logic := '0'; SIGNAL buf_fast_in : std_logic := '0'; SIGNAL buf_fast_out : std_logic := '0'; SIGNAL wr_in : std_logic := '0'; SIGNAL wr_out : std_logic := '0'; BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays TBUF_S: VitalBuf(buf_out, buf_in, (tdevice_TBUF_S,UnitDelay)); TBUF_F: VitalBuf(buf_fast_out, buf_fast_in,(tdevice_TBUF_F,UnitDelay)); WR: VitalBuf(wr_out, wr_in, (tdevice_PROGTIME ,UnitDelay)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (DIE0_ipd, DIE0, tipd_DIE0); w_2 : VitalWireDelay (DIE1_ipd, DIE1, tipd_DIE1); w_3 : VitalWireDelay (DIE2_ipd, DIE2, tipd_DIE2); w_4 : VitalWireDelay (DIE3_ipd, DIE3, tipd_DIE3); w_5 : VitalWireDelay (DIE4_ipd, DIE4, tipd_DIE4); w_6 : VitalWireDelay (DIE5_ipd, DIE5, tipd_DIE5); w_7 : VitalWireDelay (DIE6_ipd, DIE6, tipd_DIE6); w_9 : VitalWireDelay (DIE7_ipd, DIE7, tipd_DIE7); w_10 : VitalWireDelay (DIE8_ipd, DIE8, tipd_DIE8); w_11 : VitalWireDelay (DIE9_ipd, DIE9, tipd_DIE9); w_12 : VitalWireDelay (DIE10_ipd, DIE10, tipd_DIE10); w_13 : VitalWireDelay (DIE11_ipd, DIE11, tipd_DIE11); w_14 : VitalWireDelay (DIE12_ipd, DIE12, tipd_DIE12); w_15 : VitalWireDelay (DIE13_ipd, DIE13, tipd_DIE13); w_16 : VitalWireDelay (DIE14_ipd, DIE14, tipd_DIE14); w_17 : VitalWireDelay (DIE15_ipd, DIE15, tipd_DIE15); w_18 : VitalWireDelay (DIE16_ipd, DIE16, tipd_DIE16); w_19 : VitalWireDelay (DIE17_ipd, DIE17, tipd_DIE17); w_20 : VitalWireDelay (DIE18_ipd, DIE18, tipd_DIE18); w_21 : VitalWireDelay (DIE19_ipd, DIE19, tipd_DIE19); w_22 : VitalWireDelay (DIE20_ipd, DIE20, tipd_DIE20); w_23 : VitalWireDelay (DIE21_ipd, DIE21, tipd_DIE21); w_24 : VitalWireDelay (DIE22_ipd, DIE22, tipd_DIE22); w_25 : VitalWireDelay (DIE23_ipd, DIE23, tipd_DIE23); w_26 : VitalWireDelay (DIO0_ipd, DIO0, tipd_DIE0); w_27 : VitalWireDelay (DIO1_ipd, DIO1, tipd_DIE1); w_28 : VitalWireDelay (DIO2_ipd, DIO2, tipd_DIE2); w_29 : VitalWireDelay (DIO3_ipd, DIO3, tipd_DIE3); w_30 : VitalWireDelay (DIO4_ipd, DIO4, tipd_DIE4); w_31 : VitalWireDelay (DIO5_ipd, DIO5, tipd_DIE5); w_32 : VitalWireDelay (DIO6_ipd, DIO6, tipd_DIE6); w_34 : VitalWireDelay (DIO7_ipd, DIO7, tipd_DIE7); w_35 : VitalWireDelay (DIO8_ipd, DIO8, tipd_DIE8); w_36 : VitalWireDelay (DIO9_ipd, DIO9, tipd_DIE9); w_37 : VitalWireDelay (DIO10_ipd, DIO10, tipd_DIE10); w_38 : VitalWireDelay (DIO11_ipd, DIO11, tipd_DIE11); w_39 : VitalWireDelay (DIO12_ipd, DIO12, tipd_DIE12); w_40 : VitalWireDelay (DIO13_ipd, DIO13, tipd_DIE13); w_41 : VitalWireDelay (DIO14_ipd, DIO14, tipd_DIE14); w_42 : VitalWireDelay (DIO15_ipd, DIO15, tipd_DIE15); w_43 : VitalWireDelay (DIO16_ipd, DIO16, tipd_DIE16); w_44 : VitalWireDelay (DIO17_ipd, DIO17, tipd_DIE17); w_45 : VitalWireDelay (DIO18_ipd, DIO18, tipd_DIE18); w_46 : VitalWireDelay (DIO19_ipd, DIO19, tipd_DIE19); w_47 : VitalWireDelay (DIO20_ipd, DIO20, tipd_DIE20); w_48 : VitalWireDelay (DIO21_ipd, DIO21, tipd_DIE21); w_49 : VitalWireDelay (DIO22_ipd, DIO22, tipd_DIE22); w_50 : VitalWireDelay (DIO23_ipd, DIO23, tipd_DIE23); w_51 : VitalWireDelay (IDCK_ipd, IDCK, tipd_IDCK); w_52 : VitalWireDelay (DE_ipd, DE, tipd_DE); w_53 : VitalWireDelay (HSYNC_ipd, HSYNC, tipd_HSYNC); w_54 : VitalWireDelay (VSYNC_ipd, VSYNC, tipd_VSYNC); w_55 : VitalWireDelay (EDGE_ipd, EDGE, tipd_EDGE); w_56 : VitalWireDelay (PIXS_ipd, PIXS, tipd_PIXS); w_57 : VitalWireDelay (CTL1_ipd, CTL1, tipd_CTL1); w_58 : VitalWireDelay (CTL2_ipd, CTL2, tipd_CTL2); w_59 : VitalWireDelay (CTL3_ipd, CTL3, tipd_CTL3); w_60 : VitalWireDelay (PDNeg_ipd, PDNeg, tipd_PDNeg); w_61 : VitalWireDelay (ISELNeg_ipd, ISELNeg, tipd_ISELNeg); w_62 : VitalWireDelay (SCL_ipd, SCL, tipd_SCL); w_63 : VitalWireDelay (SDA_ipd, SDA, tipd_SDA); END BLOCK; Behavior : BLOCK PORT ( DIE : IN std_logic_vector(23 DOWNTO 0) :=(OTHERS => 'U'); DIO : IN std_logic_vector(23 DOWNTO 0) :=(OTHERS => 'U'); IDCK : IN std_ulogic := 'U'; DE : IN std_ulogic := 'U'; HSYNC : IN std_ulogic := 'U'; VSYNC : IN std_ulogic := 'U'; EDGE : IN std_ulogic := 'U'; PIXS : IN std_ulogic := 'U'; CTL1 : IN std_ulogic := 'U'; CTL2 : IN std_ulogic := 'U'; CTL3 : IN std_ulogic := 'U'; PDNeg : IN std_ulogic := 'U'; TX0 : OUT std_ulogic := 'U'; TX0Neg : OUT std_ulogic := 'U'; TX1 : OUT std_ulogic := 'U'; TX1Neg : OUT std_ulogic := 'U'; TX2 : OUT std_ulogic := 'U'; TX2Neg : OUT std_ulogic := 'U'; TXC : OUT std_ulogic := 'U'; TXCNeg : OUT std_ulogic := 'U'; ISELNeg : IN std_ulogic := 'U'; MSEN : OUT std_ulogic := 'U'; SCLIn : IN std_ulogic := 'U'; SDAin : IN std_ulogic := 'U'; SDAout : OUT std_ulogic := 'U' ); PORT MAP ( DIE(0) => DIE0_ipd, DIE(1) => DIE1_ipd, DIE(2) => DIE2_ipd, DIE(3) => DIE3_ipd, DIE(4) => DIE4_ipd, DIE(5) => DIE5_ipd, DIE(6) => DIE6_ipd, DIE(7) => DIE7_ipd, DIE(8) => DIE8_ipd, DIE(9) => DIE9_ipd, DIE(10) => DIE10_ipd, DIE(11) => DIE11_ipd, DIE(12) => DIE12_ipd, DIE(13) => DIE13_ipd, DIE(14) => DIE14_ipd, DIE(15) => DIE15_ipd, DIE(16) => DIE16_ipd, DIE(17) => DIE17_ipd, DIE(18) => DIE18_ipd, DIE(19) => DIE19_ipd, DIE(20) => DIE20_ipd, DIE(21) => DIE21_ipd, DIE(22) => DIE22_ipd, DIE(23) => DIE23_ipd, DIO(0) => DIO0_ipd, DIO(1) => DIO1_ipd, DIO(2) => DIO2_ipd, DIO(3) => DIO3_ipd, DIO(4) => DIO4_ipd, DIO(5) => DIO5_ipd, DIO(6) => DIO6_ipd, DIO(7) => DIO7_ipd, DIO(8) => DIO8_ipd, DIO(9) => DIO9_ipd, DIO(10) => DIO10_ipd, DIO(11) => DIO11_ipd, DIO(12) => DIO12_ipd, DIO(13) => DIO13_ipd, DIO(14) => DIO14_ipd, DIO(15) => DIO15_ipd, DIO(16) => DIO16_ipd, DIO(17) => DIO17_ipd, DIO(18) => DIO18_ipd, DIO(19) => DIO19_ipd, DIO(20) => DIO20_ipd, DIO(21) => DIO21_ipd, DIO(22) => DIO22_ipd, DIO(23) => DIO23_ipd, IDCK => IDCK_ipd, DE => DE_ipd, HSYNC => HSYNC_ipd, VSYNC => VSYNC_ipd, EDGE => EDGE_ipd, PIXS => PIXS_ipd, CTL1 => CTL1_ipd, CTL2 => CTL2_ipd, CTL3 => CTL3_ipd, PDNeg => PDNeg_ipd, TX0 => TX0, TX0Neg => TX0Neg, TX1 => TX1, TX1Neg => TX1Neg, TX2 => TX2, TX2Neg => TX2Neg, TXC => TXC, TXCNeg => TXCNeg, ISELNeg => ISELNeg_ipd, MSEN => MSEN, SCLIn => SCL_ipd, SDAIn => SDA_ipd, SDAOut => SDA ); TYPE state_type IS ( IDLE, CONTROL_BYTE, COMMAND, WRITE, READ ); SUBTYPE RegType IS std_logic_vector(7 downto 0); SIGNAL current_state : state_type; SIGNAL next_state : state_type; -- clock counter SIGNAL clk_cnt : INTEGER := 0; SIGNAL first_byte : std_logic_vector(9 downto 0) := (OTHERS => '0'); SIGNAL command_byte : std_logic_vector(9 downto 0) := (OTHERS => '0'); SIGNAL Config_reg : std_logic_vector(7 downto 0) := "11001010"; SIGNAL start : std_logic := '0'; SIGNAL stop : std_logic := '0'; SIGNAL stop_del : std_logic := '0'; SIGNAL busy : std_logic := '0'; SIGNAL busy_del : std_logic := '0'; SIGNAL Slave_ID : BOOLEAN := false; SIGNAL Firstbyte_sent : BOOLEAN := false; SIGNAL Release_SDA : BOOLEAN := false; SIGNAL Byte_received : BOOLEAN := false; SIGNAL SDA_zd : std_logic := 'Z'; SIGNAL FASTMODE : std_logic := '0'; SHARED VARIABLE Previous : Time := 0 ns; SHARED VARIABLE TmpPer : Time := 0 ns; SHARED VARIABLE DATA_BLUE : std_logic_vector(15 downto 0); SHARED VARIABLE DATA_RED : std_logic_vector(15 downto 0); SHARED VARIABLE DATA_GREEN : std_logic_vector(15 downto 0); SIGNAL D_VSYNC : std_logic; SIGNAL D_HSYNC : std_logic; SIGNAL D_CTL1 : std_logic; SIGNAL D_CTL2 : std_logic; SIGNAL D_CTL3 : std_logic; SIGNAL q_blue : std_logic_vector(19 downto 0); SIGNAL q_red : std_logic_vector(19 downto 0); SIGNAL q_green : std_logic_vector(19 downto 0); SIGNAL update_blue : std_logic := '0'; SIGNAL update_red : std_logic := '0'; SIGNAL update_green : std_logic := '0'; SIGNAL change_red : std_logic := '0'; SIGNAL change_blue : std_logic := '0'; SIGNAL change_green : std_logic := '0'; SIGNAL PERIOD : time := 1000 us; SIGNAL clk : std_ulogic := '1'; -- registers map SHARED VARIABLE VND_IDL : RegType := "00000001"; --Read only SHARED VARIABLE VND_IDH : RegType := "00000000"; --Read only SHARED VARIABLE DEV_IDL : RegType := "00000110";---Read only SHARED VARIABLE DEV_IDH : RegType := "00000000";--Read only SHARED VARIABLE DEV_REV : RegType := "00000000";--Read only SHARED VARIABLE FRQ_LOW : RegType := "00011001";--Read/Write SHARED VARIABLE FRQ_HIGH : RegType := "01100100";--Read/Write SHARED VARIABLE REG_8 : RegType := "00110100";--Read/Write SHARED VARIABLE RSEN_R : RegType := "00000000";--Read only ???? SHARED VARIABLE CTL0 : RegType := "10000001";--Read/Write SHARED VARIABLE REG_E : RegType := "00000001";--Read/Write ALIAS VEN_BIT : std_logic IS REG_8(5); ALIAS HEN_BIT : std_logic IS REG_8(5); ALIAS EDGE_BIT : std_logic IS REG_8(1); ALIAS PD_BIT : std_logic IS REG_8(0); ALIAS RSEN_BIT : std_logic IS RSEN_R(2); ALIAS EZONE_BIT : std_logic IS REG_E(5); ALIAS ZONEF_BIT : std_logic IS REG_E(4); ALIAS ZONEO_BIT : std_logic IS REG_E(3); ALIAS CTL0_BIT : std_logic IS CTL0(0); SIGNAL RST : std_logic; BEGIN FASTMODE <= '0' WHEN standard_mode = TRUE ELSE '1'; RST <= ISELNeg AFTER 49999 ns; TXC <= IDCK WHEN ((ISELNeg = '1' AND PDNeg = '1' ) OR (ISELNeg = '0' AND PD_BIT = '1')) ELSE 'Z'; TXCNeg <= not IDCK WHEN ((ISELNeg = '1' AND PDNeg = '1' ) OR (ISELNeg = '0' AND PD_BIT = '1')) ELSE 'Z'; MSEN <= RSEN_BIT; ---------------------------------------------------------------------------- -- Behavior Process --------------------------------------------------------------------------- PIXELBUS : PROCESS(IDCK, DIE, DIO, DE, VSYNC, HSYNC, CTL1, CTL2, CTL3) -- Timing Check Variables VARIABLE Tviol_DIE_IDCKfall : X01 := '0'; VARIABLE TD_DIE_IDCKfall : VitalTimingDataType; VARIABLE Tviol_DIO_IDCKfall : X01 := '0'; VARIABLE TD_DIO_IDCKfall : VitalTimingDataType; VARIABLE Tviol_DE_IDCKfall : X01 := '0'; VARIABLE TD_DE_IDCKfall : VitalTimingDataType; VARIABLE Tviol_VSYNC_IDCKfall : X01 := '0'; VARIABLE TD_VSYNC_IDCKfall : VitalTimingDataType; VARIABLE Tviol_HSYNC_IDCKfall : X01 := '0'; VARIABLE TD_HSYNC_IDCKfall : VitalTimingDataType; VARIABLE Tviol_DIE_IDCKrise : X01 := '0'; VARIABLE TD_DIE_IDCKrise : VitalTimingDataType; VARIABLE Tviol_DIO_IDCKrise : X01 := '0'; VARIABLE TD_DIO_IDCKrise : VitalTimingDataType; VARIABLE Tviol_DE_IDCKrise : X01 := '0'; VARIABLE TD_DE_IDCKrise : VitalTimingDataType; VARIABLE Tviol_VSYNC_IDCKrise : X01 := '0'; VARIABLE TD_VSYNC_IDCKrise : VitalTimingDataType; VARIABLE Tviol_HSYNC_IDCKrise : X01 := '0'; VARIABLE TD_HSYNC_IDCKrise : VitalTimingDataType; VARIABLE Tviol_VSYNC_DE_PIXS_0 : X01 := '0'; VARIABLE TD_VSYNC_DE_PIXS_0 : VitalTimingDataType; VARIABLE Tviol_VSYNC_DE_PIXS_1 : X01 := '0'; VARIABLE TD_VSYNC_DE_PIXS_1 : VitalTimingDataType; VARIABLE Tviol_HSYNC_DE_PIXS_0 : X01 := '0'; VARIABLE TD_HSYNC_DE_PIXS_0 : VitalTimingDataType; VARIABLE Tviol_HSYNC_DE_PIXS_1 : X01 := '0'; VARIABLE TD_HSYNC_DE_PIXS_1 : VitalTimingDataType; VARIABLE Tviol_CTL1_DE_PIXS_0 : X01 := '0'; VARIABLE TD_CTL1_DE_PIXS_0 : VitalTimingDataType; VARIABLE Tviol_CTL1_DE_PIXS_1 : X01 := '0'; VARIABLE TD_CTL1_DE_PIXS_1 : VitalTimingDataType; VARIABLE Tviol_CTL2_DE_PIXS_0 : X01 := '0'; VARIABLE TD_CTL2_DE_PIXS_0 : VitalTimingDataType; VARIABLE Tviol_CTL2_DE_PIXS_1 : X01 := '0'; VARIABLE TD_CTL2_DE_PIXS_1 : VitalTimingDataType; VARIABLE Tviol_CTL3_DE_PIXS_0 : X01 := '0'; VARIABLE TD_CTL3_DE_PIXS_0 : VitalTimingDataType; VARIABLE Tviol_CTL3_DE_PIXS_1 : X01 := '0'; VARIABLE TD_CTL3_DE_PIXS_1 : VitalTimingDataType; VARIABLE Tviol_DE_VSYNC_PIXS_0 : X01 := '0'; VARIABLE TD_DE_VSYNC_PIXS_0 : VitalTimingDataType; VARIABLE Tviol_DE_VSYNC_PIXS_1 : X01 := '0'; VARIABLE TD_DE_VSYNC_PIXS_1 : VitalTimingDataType; VARIABLE Tviol_DE_HSYNC_PIXS_0 : X01 := '0'; VARIABLE TD_DE_HSYNC_PIXS_0 : VitalTimingDataType; VARIABLE Tviol_DE_HSYNC_PIXS_1 : X01 := '0'; VARIABLE TD_DE_HSYNC_PIXS_1 : VitalTimingDataType; VARIABLE Tviol_DE_CTL1_PIXS_0 : X01 := '0'; VARIABLE TD_DE_CTL1_PIXS_0 : VitalTimingDataType; VARIABLE Tviol_DE_CTL1_PIXS_1 : X01 := '0'; VARIABLE TD_DE_CTL1_PIXS_1 : VitalTimingDataType; VARIABLE Tviol_DE_CTL2_PIXS_0 : X01 := '0'; VARIABLE TD_DE_CTL2_PIXS_0 : VitalTimingDataType; VARIABLE Tviol_DE_CTL2_PIXS_1 : X01 := '0'; VARIABLE TD_DE_CTL2_PIXS_1 : VitalTimingDataType; VARIABLE Tviol_DE_CTL3_PIXS_0 : X01 := '0'; VARIABLE TD_DE_CTL3_PIXS_0 : VitalTimingDataType; VARIABLE Tviol_DE_CTL3_PIXS_1 : X01 := '0'; VARIABLE TD_DE_CTL3_PIXS_1 : VitalTimingDataType; VARIABLE Pviol_IDCK_PIXS_0 : X01 := '0'; VARIABLE PD_IDCK_PIXS_0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_IDCK_PIXS_1 : X01 := '0'; VARIABLE PD_IDCK_PIXS_1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DIE, TestSignalName => "DIE", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DIE0_IDCK, SetupLow => tsetup_DIE0_IDCK, HoldHigh => thold_DIE0_IDCK, HoldLow => thold_DIE0_IDCK, CheckEnabled => EDGE = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DIE_IDCKfall, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DIE_IDCKfall ); VitalSetupHoldCheck ( TestSignal => DIO, TestSignalName => "DIO", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DIE0_IDCK, SetupLow => tsetup_DIE0_IDCK, HoldHigh => thold_DIE0_IDCK, HoldLow => thold_DIE0_IDCK, CheckEnabled => EDGE = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DIO_IDCKfall, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DIO_IDCKfall ); VitalSetupHoldCheck ( TestSignal => DE, TestSignalName => "DE", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DIE0_IDCK, SetupLow => tsetup_DIE0_IDCK, HoldHigh => thold_DIE0_IDCK, HoldLow => thold_DIE0_IDCK, CheckEnabled => EDGE = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_IDCKfall, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_IDCKfall ); VitalSetupHoldCheck ( TestSignal => VSYNC, TestSignalName => "VSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DIE0_IDCK, SetupLow => tsetup_DIE0_IDCK, HoldHigh => thold_DIE0_IDCK, HoldLow => thold_DIE0_IDCK, CheckEnabled => EDGE = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_VSYNC_IDCKfall, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_VSYNC_IDCKfall ); VitalSetupHoldCheck ( TestSignal => HSYNC, TestSignalName => "HSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DIE0_IDCK, SetupLow => tsetup_DIE0_IDCK, HoldHigh => thold_DIE0_IDCK, HoldLow => thold_DIE0_IDCK, CheckEnabled => EDGE = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_HSYNC_IDCKfall, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSYNC_IDCKfall ); VitalSetupHoldCheck ( TestSignal => DIE, TestSignalName => "DIE", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DIE0_IDCK, SetupLow => tsetup_DIE0_IDCK, HoldHigh => thold_DIE0_IDCK, HoldLow => thold_DIE0_IDCK, CheckEnabled => EDGE = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DIE_IDCKrise, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DIE_IDCKrise ); VitalSetupHoldCheck ( TestSignal => DIO, TestSignalName => "DIO", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DIE0_IDCK, SetupLow => tsetup_DIE0_IDCK, HoldHigh => thold_DIE0_IDCK, HoldLow => thold_DIE0_IDCK, CheckEnabled => EDGE = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DIO_IDCKrise, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DIO_IDCKrise ); VitalSetupHoldCheck ( TestSignal => DE, TestSignalName => "DE", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DIE0_IDCK, SetupLow => tsetup_DIE0_IDCK, HoldHigh => thold_DIE0_IDCK, HoldLow => thold_DIE0_IDCK, CheckEnabled => EDGE = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_IDCKrise, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_IDCKrise ); VitalSetupHoldCheck ( TestSignal => VSYNC, TestSignalName => "VSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DIE0_IDCK, SetupLow => tsetup_DIE0_IDCK, HoldHigh => thold_DIE0_IDCK, HoldLow => thold_DIE0_IDCK, CheckEnabled => EDGE = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_VSYNC_IDCKrise, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_VSYNC_IDCKrise ); VitalSetupHoldCheck ( TestSignal => HSYNC, TestSignalName => "HSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DIE0_IDCK, SetupLow => tsetup_DIE0_IDCK, HoldHigh => thold_DIE0_IDCK, HoldLow => thold_DIE0_IDCK, CheckEnabled => EDGE = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_HSYNC_IDCKrise, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSYNC_IDCKrise ); VitalSetupHoldCheck ( TestSignal => VSYNC, TestSignalName => "VSYNC", RefSignal => DE, RefSignalName => "DE", SetupHigh => tperiod_IDCK_PIXS_EQ_0, SetupLow => tperiod_IDCK_PIXS_EQ_0, CheckEnabled => PIXS = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_VSYNC_DE_PIXS_0, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_VSYNC_DE_PIXS_0 ); VitalSetupHoldCheck ( TestSignal => VSYNC, TestSignalName => "VSYNC", RefSignal => DE, RefSignalName => "DE", SetupHigh => tperiod_IDCK_PIXS_EQ_1, SetupLow => tperiod_IDCK_PIXS_EQ_1, CheckEnabled => PIXS = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_VSYNC_DE_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_VSYNC_DE_PIXS_1 ); VitalSetupHoldCheck ( TestSignal => HSYNC, TestSignalName => "HSYNC", RefSignal => DE, RefSignalName => "DE", SetupHigh => tperiod_IDCK_PIXS_EQ_0, SetupLow => tperiod_IDCK_PIXS_EQ_0, CheckEnabled => PIXS = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_HSYNC_DE_PIXS_0, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSYNC_DE_PIXS_0 ); VitalSetupHoldCheck ( TestSignal => HSYNC, TestSignalName => "HSYNC", RefSignal => DE, RefSignalName => "DE", SetupHigh => tperiod_IDCK_PIXS_EQ_1, SetupLow => tperiod_IDCK_PIXS_EQ_1, CheckEnabled => PIXS = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_HSYNC_DE_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSYNC_DE_PIXS_1 ); VitalSetupHoldCheck ( TestSignal => CTL1, TestSignalName => "CTL1", RefSignal => DE, RefSignalName => "DE", SetupHigh => tperiod_IDCK_PIXS_EQ_0, SetupLow => tperiod_IDCK_PIXS_EQ_0, CheckEnabled => PIXS = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CTL1_DE_PIXS_0, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CTL1_DE_PIXS_0 ); VitalSetupHoldCheck ( TestSignal => CTL1, TestSignalName => "CTL1", RefSignal => DE, RefSignalName => "DE", SetupHigh => tperiod_IDCK_PIXS_EQ_1, SetupLow => tperiod_IDCK_PIXS_EQ_1, CheckEnabled => PIXS = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CTL1_DE_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CTL1_DE_PIXS_1 ); VitalSetupHoldCheck ( TestSignal => CTL2, TestSignalName => "CTL2", RefSignal => DE, RefSignalName => "DE", SetupHigh => tperiod_IDCK_PIXS_EQ_0, SetupLow => tperiod_IDCK_PIXS_EQ_0, CheckEnabled => PIXS = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CTL2_DE_PIXS_0, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CTL2_DE_PIXS_0 ); VitalSetupHoldCheck ( TestSignal => CTL2, TestSignalName => "CTL2", RefSignal => DE, RefSignalName => "DE", SetupHigh => tperiod_IDCK_PIXS_EQ_1, SetupLow => tperiod_IDCK_PIXS_EQ_1, CheckEnabled => PIXS = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CTL2_DE_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CTL2_DE_PIXS_1 ); VitalSetupHoldCheck ( TestSignal => CTL3, TestSignalName => "CTL3", RefSignal => DE, RefSignalName => "DE", SetupHigh => tperiod_IDCK_PIXS_EQ_0, SetupLow => tperiod_IDCK_PIXS_EQ_0, CheckEnabled => PIXS = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CTL3_DE_PIXS_0, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CTL3_DE_PIXS_0 ); VitalSetupHoldCheck ( TestSignal => CTL3, TestSignalName => "CTL3", RefSignal => DE, RefSignalName => "DE", SetupHigh => tperiod_IDCK_PIXS_EQ_1, SetupLow => tperiod_IDCK_PIXS_EQ_1, CheckEnabled => PIXS = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CTL3_DE_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CTL3_DE_PIXS_1 ); VitalSetupHoldCheck ( TestSignal => VSYNC, TestSignalName => "VSYNC", RefSignal => DE, RefSignalName => "DE", HoldHigh => tperiod_IDCK_PIXS_EQ_0, HoldLow => tperiod_IDCK_PIXS_EQ_0, CheckEnabled => PIXS = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_VSYNC_PIXS_0, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_VSYNC_PIXS_0 ); VitalSetupHoldCheck ( TestSignal => VSYNC, TestSignalName => "VSYNC", RefSignal => DE, RefSignalName => "DE", HoldHigh => tperiod_IDCK_PIXS_EQ_1, HoldLow => tperiod_IDCK_PIXS_EQ_1, CheckEnabled => PIXS = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_VSYNC_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_VSYNC_PIXS_1 ); VitalSetupHoldCheck ( TestSignal => HSYNC, TestSignalName => "HSYNC", RefSignal => DE, RefSignalName => "DE", HoldHigh => tperiod_IDCK_PIXS_EQ_0, HoldLow => tperiod_IDCK_PIXS_EQ_0, CheckEnabled => PIXS = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_HSYNC_PIXS_0, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_HSYNC_PIXS_0 ); VitalSetupHoldCheck ( TestSignal => HSYNC, TestSignalName => "HSYNC", RefSignal => DE, RefSignalName => "DE", HoldHigh => tperiod_IDCK_PIXS_EQ_1, HoldLow => tperiod_IDCK_PIXS_EQ_1, CheckEnabled => PIXS = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_HSYNC_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_HSYNC_PIXS_1 ); VitalSetupHoldCheck ( TestSignal => CTL1, TestSignalName => "CTL1", RefSignal => DE, RefSignalName => "DE", HoldHigh => tperiod_IDCK_PIXS_EQ_0, HoldLow => tperiod_IDCK_PIXS_EQ_0, CheckEnabled => PIXS = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_CTL1_PIXS_0, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_CTL1_PIXS_0 ); VitalSetupHoldCheck ( TestSignal => CTL1, TestSignalName => "CTL1", RefSignal => DE, RefSignalName => "DE", HoldHigh => tperiod_IDCK_PIXS_EQ_1, HoldLow => tperiod_IDCK_PIXS_EQ_1, CheckEnabled => PIXS = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_CTL1_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_CTL1_PIXS_1 ); VitalSetupHoldCheck ( TestSignal => CTL2, TestSignalName => "CTL2", RefSignal => DE, RefSignalName => "DE", HoldHigh => tperiod_IDCK_PIXS_EQ_0, HoldLow => tperiod_IDCK_PIXS_EQ_0, CheckEnabled => PIXS = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_CTL2_PIXS_0, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_CTL2_PIXS_0 ); VitalSetupHoldCheck ( TestSignal => CTL2, TestSignalName => "CTL2", RefSignal => DE, RefSignalName => "DE", HoldHigh => tperiod_IDCK_PIXS_EQ_1, HoldLow => tperiod_IDCK_PIXS_EQ_1, CheckEnabled => PIXS = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_CTL2_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_CTL2_PIXS_1 ); VitalSetupHoldCheck ( TestSignal => CTL3, TestSignalName => "CTL3", RefSignal => DE, RefSignalName => "DE", HoldHigh => tperiod_IDCK_PIXS_EQ_0, HoldLow => tperiod_IDCK_PIXS_EQ_0, CheckEnabled => PIXS = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_CTL3_PIXS_0, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_CTL3_PIXS_0 ); VitalSetupHoldCheck ( TestSignal => CTL3, TestSignalName => "CTL3", RefSignal => DE, RefSignalName => "DE", HoldHigh => tperiod_IDCK_PIXS_EQ_1, HoldLow => tperiod_IDCK_PIXS_EQ_1, CheckEnabled => PIXS = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_CTL3_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_CTL3_PIXS_1 ); VitalPeriodPulseCheck ( TestSignal => IDCK, TestSignalName => "IDCK", Period => tperiod_IDCK_PIXS_EQ_0, PeriodData => PD_IDCK_PIXS_0, PulseWidthHigh => tpw_IDCK_posedge, PulseWidthLow => tpw_IDCK_negedge, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_IDCK_PIXS_0, HeaderMsg => InstancePath & PartID, CheckEnabled => PIXS = '0' ); VitalPeriodPulseCheck ( TestSignal => IDCK, TestSignalName => "IDCK", Period => tperiod_IDCK_PIXS_EQ_1, PeriodData => PD_IDCK_PIXS_1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_IDCK_PIXS_1, HeaderMsg => InstancePath & PartID, CheckEnabled => PIXS = '1' ); Violation := Tviol_DIE_IDCKfall OR Tviol_DIO_IDCKfall OR Tviol_DE_IDCKfall OR Tviol_VSYNC_IDCKfall OR Tviol_HSYNC_IDCKfall OR Tviol_DIE_IDCKrise OR Tviol_DIO_IDCKrise OR Tviol_DE_IDCKrise OR Tviol_VSYNC_IDCKrise OR Tviol_HSYNC_IDCKrise OR Tviol_VSYNC_DE_PIXS_1 OR Tviol_VSYNC_DE_PIXS_0 OR Tviol_HSYNC_DE_PIXS_1 OR Tviol_HSYNC_DE_PIXS_0 OR Tviol_CTL1_DE_PIXS_1 OR Tviol_CTL1_DE_PIXS_0 OR Tviol_CTL2_DE_PIXS_1 OR Tviol_CTL2_DE_PIXS_0 OR Tviol_CTL3_DE_PIXS_1 OR Tviol_CTL3_DE_PIXS_0 OR Tviol_DE_VSYNC_PIXS_1 OR Tviol_DE_VSYNC_PIXS_0 OR Tviol_DE_HSYNC_PIXS_1 OR Tviol_DE_HSYNC_PIXS_0 OR Tviol_DE_CTL2_PIXS_1 OR Tviol_DE_CTL2_PIXS_0 OR Tviol_DE_CTL2_PIXS_1 OR Tviol_DE_CTL2_PIXS_0 OR Tviol_DE_CTL3_PIXS_1 OR Tviol_DE_CTL3_PIXS_0 OR Pviol_IDCK_PIXS_0 OR Pviol_IDCK_PIXS_1; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY SeverityMode; END IF; IF (ISELNeg = '1' AND EDGE = '0') OR (ISELNeg = '0' AND EDGE_BIT = '0') THEN --latch on falling edge of IDCK IF falling_edge(IDCK) THEN IF (DE = '1')THEN DATA_RED(7 downto 0) := DIE(23 downto 16); DATA_GREEN(7 downto 0) := DIE(15 downto 8); DATA_BLUE(7 downto 0) := DIE(7 downto 0); change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); IF PIXS = '1' THEN DATA_RED(15 downto 8) := DIO(23 downto 16); DATA_GREEN(15 downto 8) := DIO(15 downto 8); DATA_BLUE(15 downto 8) := DIO(7 downto 0); change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); END IF; ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); END IF; END IF; ELSE --latch on rising edge of IDCK IF rising_edge(IDCK) THEN IF (DE = '1') THEN DATA_RED(7 downto 0) := DIE(23 downto 16); DATA_GREEN(7 downto 0) := DIE(15 downto 8); DATA_BLUE(7 downto 0) := DIE(7 downto 0); change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); IF PIXS = '1' THEN DATA_RED(15 downto 8) := DIO(23 downto 16); DATA_GREEN(15 downto 8) := DIO(15 downto 8); DATA_BLUE(15 downto 8) := DIO(7 downto 0); change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); END IF; ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); END IF; END IF; END IF; END PROCESS; CLOCKTIME: PROCESS(IDCK) BEGIN IF rising_edge(IDCK) THEN TmpPer := NOW - Previous; IF TmpPer > 0 ns THEN IF PIXS = '0' THEN PERIOD <= TmpPer/20; ELSE PERIOD <= TmpPer/40; END IF; END IF; Previous := NOW; END IF; END PROCESS; PLL : PROCESS BEGIN IF ((NOW-Previous) <= TmpPer) THEN WAIT FOR PERIOD; clk <= not(clk); ELSE WAIT until rising_edge(IDCK); END IF; END PROCESS PLL; BLUEENCODER : PROCESS(change_blue) VARIABLE q_m : std_logic_vector(9 downto 0) := (others => '0'); VARIABLE q_out : std_logic_vector(9 downto 0); VARIABLE q_out_temp : std_logic_vector(19 downto 0); VARIABLE N1 : NATURAL := 0; VARIABLE N0 : NATURAL := 0; VARIABLE disparity : INTEGER := 0; VARIABLE vsynch : std_logic; VARIABLE hsynch : std_logic; VARIABLE selection : std_logic_vector(1 downto 0); BEGIN FOR k IN 0 TO (to_nat(PIXS)) LOOP DATA_BLUE(7 downto 0) := DATA_BLUE((7+k*8) downto (0+ k*8)); N1 := 0; FOR I IN 0 TO 7 LOOP IF DATA_BLUE(i) = '1' THEN N1 := N1 + 1; END IF; END LOOP; IF (N1 > 4 OR ( N1 = 4 AND DATA_BLUE(0) = '0')) THEN q_m(0) := DATA_BLUE(0); q_m(1) := q_m(0) XNOR DATA_BLUE(1); q_m(2) := q_m(1) XNOR DATA_BLUE(2); q_m(3) := q_m(2) XNOR DATA_BLUE(3); q_m(4) := q_m(3) XNOR DATA_BLUE(4); q_m(5) := q_m(4) XNOR DATA_BLUE(5); q_m(6) := q_m(5) XNOR DATA_BLUE(6); q_m(7) := q_m(6) XNOR DATA_BLUE(7); q_m(8) := '0'; ELSE q_m(0) := DATA_BLUE(0); q_m(1) := q_m(0) XOR DATA_BLUE(1); q_m(2) := q_m(1) XOR DATA_BLUE(2); q_m(3) := q_m(2) XOR DATA_BLUE(3); q_m(4) := q_m(3) XOR DATA_BLUE(4); q_m(5) := q_m(4) XOR DATA_BLUE(5); q_m(6) := q_m(5) XOR DATA_BLUE(6); q_m(7) := q_m(6) XOR DATA_BLUE(7); q_m(8) := '1'; END IF; IF DE = '1' THEN N1 := 0; N0 := 0; FOR I IN 0 TO 7 LOOP IF q_m(i) = '1' THEN N1 := N1 + 1; ELSIF q_m(i) = '0' THEN N0 := N0 + 1; END IF; END LOOP; IF (disparity = 0 OR N1 = N0) THEN q_out(9) := not(q_m(8)); q_out(8) := q_m(8); IF q_out(8) = '1' THEN q_out(7 downto 0) := q_m(7 downto 0); ELSE q_out(7 downto 0) := not(q_m(7 downto 0)); END IF; IF q_m(8) = '0' THEN disparity := disparity + (N0 - N1); ELSE disparity := disparity + (N1 - N0); END IF; ELSE IF (disparity > 0 AND N1 > N0) OR (disparity < 0 AND N0 > N1) THEN q_out(9) := '1'; q_out(8) := q_m(8); q_out(7 downto 0) := not(q_m(7 downto 0)); disparity := disparity + 2 * to_nat(q_m(8)) + (N0 - N1); ELSE q_out(9) := '0'; q_out(8) := q_m(8); q_out(7 downto 0) := q_m(7 downto 0); disparity := disparity + 2 * to_nat(not(q_m(8))) + (N0 - N1); END IF; END IF; ELSE disparity := 0; vsynch := D_VSYNC; hsynch := D_HSYNC; selection := vsynch & hsynch; CASE selection IS WHEN "00" => q_out := "0010101011"; WHEN "01" => q_out := "1101010100"; WHEN "10" => q_out := "0010101010"; WHEN "11" => q_out := "1101010101"; WHEN others => null; END CASE; END IF; q_out_temp((9+k*10) downto (0+ k*10)) := q_out(9 downto 0); END LOOP; q_blue <= q_out_temp; update_blue <= not update_blue; END PROCESS; REDENCODER : PROCESS(change_red) VARIABLE q_m : std_logic_vector(9 downto 0) := (others => '0'); VARIABLE q_out : std_logic_vector(9 downto 0); VARIABLE q_out_temp : std_logic_vector(19 downto 0); VARIABLE N1 : NATURAL := 0; VARIABLE N0 : NATURAL := 0; VARIABLE disparity : INTEGER := 0; VARIABLE selection : std_logic_vector(1 downto 0); BEGIN FOR k IN 0 TO (to_nat(PIXS)) LOOP DATA_RED(7 downto 0) := DATA_RED((7+k*8) downto (0+ k*8)); N1 := 0; FOR I IN 0 TO 7 LOOP IF DATA_RED(i) = '1' THEN N1 := N1 + 1; END IF; END LOOP; IF (N1 > 4 OR ( N1 = 4 AND DATA_RED(0) = '0')) THEN q_m(0) := DATA_RED(0); q_m(1) := q_m(0) XNOR DATA_RED(1); q_m(2) := q_m(1) XNOR DATA_RED(2); q_m(3) := q_m(2) XNOR DATA_RED(3); q_m(4) := q_m(3) XNOR DATA_RED(4); q_m(5) := q_m(4) XNOR DATA_RED(5); q_m(6) := q_m(5) XNOR DATA_RED(6); q_m(7) := q_m(6) XNOR DATA_RED(7); q_m(8) := '0'; ELSE q_m(0) := DATA_RED(0); q_m(1) := q_m(0) XOR DATA_RED(1); q_m(2) := q_m(1) XOR DATA_RED(2); q_m(3) := q_m(2) XOR DATA_RED(3); q_m(4) := q_m(3) XOR DATA_RED(4); q_m(5) := q_m(4) XOR DATA_RED(5); q_m(6) := q_m(5) XOR DATA_RED(6); q_m(7) := q_m(6) XOR DATA_RED(7); q_m(8) := '1'; END IF; IF DE = '1' THEN N1 := 0; N0 := 0; FOR I IN 0 TO 7 LOOP IF q_m(i) = '1' THEN N1 := N1 + 1; ELSIF q_m(i) = '0' THEN N0 := N0 + 1; END IF; END LOOP; IF (disparity = 0 OR N1 = N0) THEN q_out(9) := not(q_m(8)); q_out(8) := q_m(8); IF q_out(8) = '1' THEN q_out(7 downto 0) := q_m(7 downto 0); ELSE q_out(7 downto 0) := not(q_m(7 downto 0)); END IF; IF q_m(8) = '0' THEN disparity := disparity + (N0 - N1); ELSE disparity := disparity + (N1 - N0); END IF; ELSE IF (disparity > 0 AND N1 > N0) OR (disparity < 0 AND N0 > N1) THEN q_out(9) := '1'; q_out(8) := q_m(8); q_out(7 downto 0) := not(q_m(7 downto 0)); disparity := disparity + 2 * to_nat(q_m(8)) + (N0 - N1); ELSE q_out(9) := '0'; q_out(8) := q_m(8); q_out(7 downto 0) := q_m(7 downto 0); disparity := disparity + 2 * to_nat(not(q_m(8))) + (N0 - N1); END IF; END IF; ELSE disparity := 0; selection := D_CTL2 & D_CTL3; CASE selection IS WHEN "00" => q_out := "0010101011"; WHEN "01" => q_out := "1101010100"; WHEN "10" => q_out := "0010101010"; WHEN "11" => q_out := "1101010101"; WHEN others => null; END CASE; END IF; q_out_temp((9+k*10) downto (0+ k*10)) := q_out(9 downto 0); END LOOP; q_red <= q_out_temp; update_red <= not update_red; END PROCESS; GREENENCODER : PROCESS( change_green) VARIABLE q_m : std_logic_vector(9 downto 0) := (others => '0'); VARIABLE q_out : std_logic_vector(9 downto 0); VARIABLE q_out_temp : std_logic_vector(19 downto 0); VARIABLE N1 : NATURAL := 0; VARIABLE N0 : NATURAL := 0; VARIABLE disparity : INTEGER := 0; VARIABLE selection : std_logic_vector(1 downto 0); BEGIN FOR k IN 0 TO (to_nat(PIXS)) LOOP DATA_GREEN(7 downto 0) := DATA_GREEN((7+k*8) downto (0+ k*8)); N1 := 0; FOR I IN 0 TO 7 LOOP IF DATA_GREEN(i) = '1' THEN N1 := N1 + 1; END IF; END LOOP; IF (N1 > 4 OR ( N1 = 4 AND DATA_GREEN(0) = '0')) THEN q_m(0) := DATA_GREEN(0); q_m(1) := q_m(0) XNOR DATA_GREEN(1); q_m(2) := q_m(1) XNOR DATA_GREEN(2); q_m(3) := q_m(2) XNOR DATA_GREEN(3); q_m(4) := q_m(3) XNOR DATA_GREEN(4); q_m(5) := q_m(4) XNOR DATA_GREEN(5); q_m(6) := q_m(5) XNOR DATA_GREEN(6); q_m(7) := q_m(6) XNOR DATA_GREEN(7); q_m(8) := '0'; ELSE q_m(0) := DATA_GREEN(0); q_m(1) := q_m(0) XOR DATA_GREEN(1); q_m(2) := q_m(1) XOR DATA_GREEN(2); q_m(3) := q_m(2) XOR DATA_GREEN(3); q_m(4) := q_m(3) XOR DATA_GREEN(4); q_m(5) := q_m(4) XOR DATA_GREEN(5); q_m(6) := q_m(5) XOR DATA_GREEN(6); q_m(7) := q_m(6) XOR DATA_GREEN(7); q_m(8) := '1'; END IF; IF DE = '1' THEN N1 := 0; N0 := 0; FOR I IN 0 TO 7 LOOP IF q_m(i) = '1' THEN N1 := N1 + 1; ELSIF q_m(i) = '0' THEN N0 := N0 + 1; END IF; END LOOP; IF (disparity = 0 OR N1 = N0) THEN q_out(9) := not(q_m(8)); q_out(8) := q_m(8); IF q_out(8) = '1' THEN q_out(7 downto 0) := q_m(7 downto 0); ELSE q_out(7 downto 0) := not(q_m(7 downto 0)); END IF; IF q_m(8) = '0' THEN disparity := disparity + (N0 - N1); ELSE disparity := disparity + (N1 - N0); END IF; ELSE IF (disparity > 0 AND N1 > N0) OR (disparity < 0 AND N0 > N1) THEN q_out(9) := '1'; q_out(8) := q_m(8); q_out(7 downto 0) := not(q_m(7 downto 0)); disparity := disparity + 2 * to_nat(q_m(8)) + (N0 - N1); ELSE q_out(9) := '0'; q_out(8) := q_m(8); q_out(7 downto 0) := q_m(7 downto 0); disparity := disparity + 2 * to_nat(not(q_m(8))) + (N0 - N1); END IF; END IF; ELSE disparity := 0; IF ISELNeg = '0' THEN selection := CTL0_BIT & D_CTL1; ELSE selection := '1' & D_CTL1; END IF; CASE selection IS WHEN "00" => q_out := "0010101011"; WHEN "01" => q_out := "1101010100"; WHEN "10" => q_out := "0010101010"; WHEN "11" => q_out := "1101010101"; WHEN others => null; END CASE; END IF; q_out_temp((9+k*10) downto (0+ k*10)) := q_out(9 downto 0); END LOOP; q_green <= q_out_temp; update_green <= not update_green; END PROCESS; TDMS : PROCESS(clk, update_blue, update_red, update_green, PDNeg ) VARIABLE Temp_blue : std_logic_vector(19 downto 0); VARIABLE Temp_red : std_logic_vector(19 downto 0); VARIABLE Temp_green : std_logic_vector(19 downto 0); VARIABLE shift : std_logic; BEGIN IF (PDNeg'event AND PDNeg = '0' AND ISELNeg = '1') OR (ISELNeg = '0' AND PD_BIT = '0') THEN TX0 <= 'Z'; TX0Neg <= 'Z'; TX1 <= 'Z'; TX1Neg <= 'Z'; TX2 <= 'Z'; TX2Neg <= 'Z'; END IF; IF not clk'event THEN Temp_blue := q_blue; Temp_red := q_red; Temp_green := q_green; ELSE IF (ISELNeg = '0' AND PD_BIT = '1') OR (ISELNeg = '1' AND PDNeg = '1') THEN IF falling_edge(clk) THEN TX0 <= Temp_blue(0); TX0Neg <= not(Temp_blue(0)); TX1 <= Temp_green(0); TX1Neg <= not(Temp_green(0)); TX2 <= Temp_red(0); TX2Neg <= not(Temp_red(0)); IF PIXS = '0' THEN shift := Temp_blue(0); Temp_blue(8 downto 0) := Temp_blue(9 downto 1); Temp_blue(9) := shift; shift := Temp_red(0); Temp_red(8 downto 0) := Temp_red(9 downto 1); Temp_red(9) := shift; shift := Temp_green(0); Temp_green(8 downto 0) := Temp_green(9 downto 1); Temp_green(9) := shift; ELSE shift := Temp_blue(0); Temp_blue(18 downto 0) := Temp_blue(19 downto 1); Temp_blue(19) := shift; shift := Temp_red(0); Temp_red(18 downto 0) := Temp_red(19 downto 1); Temp_red(19) := shift; shift := Temp_green(0); Temp_green(18 downto 0) := Temp_green(19 downto 1); Temp_green(19) := shift; END IF; END IF; END IF; END IF; END PROCESS; --------------------------------------- -------------I2C----------------------- --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS(SCLIn, SDAIn) -- Timing Check Variables VARIABLE Tviol_SDAS_SCL : X01 := '0'; VARIABLE TD_SDAS_SCL : VitalTimingDataType; VARIABLE Tviol_SDAS_SCL_FAST : X01 := '0'; VARIABLE TD_SDAS_SCL_FAST : VitalTimingDataType; VARIABLE Tviol_SDAH_SCL : X01 := '0'; VARIABLE TD_SDAH_SCL : VitalTimingDataType; VARIABLE Tviol_SDAH_SCL_FAST : X01 := '0'; VARIABLE TD_SDAH_SCL_FAST : VitalTimingDataType; VARIABLE Tviol_SCL_SDAS : X01 := '0'; VARIABLE TD_SCL_SDAS : VitalTimingDataType; VARIABLE Tviol_SCL_SDAS_FAST : X01 := '0'; VARIABLE TD_SCL_SDAS_FAST : VitalTimingDataType; VARIABLE Tviol_SCL_SDAP : X01 := '0'; VARIABLE TD_SCL_SDAP : VitalTimingDataType; VARIABLE Tviol_SCL_SDAP_FAST : X01 := '0'; VARIABLE TD_SCL_SDAP_FAST : VitalTimingDataType; VARIABLE Pviol_SCL : X01 := '0'; VARIABLE PD_SCL : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_SCL_FAST : X01 := '0'; VARIABLE PD_SCL_FAST : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Data setup time, standard mode VitalSetupHoldCheck ( TestSignal => SDAIn, TestSignalName => "SDA", RefSignal => SCLIn, RefSignalName => "SCL", SetupHigh => tsetup_SDA_SCL_FASTMODE_EQ_0_noedge_posedge, SetupLow => tsetup_SDA_SCL_FASTMODE_EQ_0_noedge_posedge, CheckEnabled => FASTMODE = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SDAS_SCL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDAS_SCL ); -- Data setup time, fast mode VitalSetupHoldCheck ( TestSignal => SDAIn, TestSignalName => "SDA", RefSignal => SCLIn, RefSignalName => "SCL", SetupHigh => tsetup_SDA_SCL_FASTMODE_EQ_1_noedge_posedge, SetupLow => tsetup_SDA_SCL_FASTMODE_EQ_1_noedge_posedge, CheckEnabled => FASTMODE = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SDAS_SCL_FAST, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDAS_SCL_FAST ); -- Data Hold Time, standard mode VitalSetupHoldCheck ( TestSignal => SDAIn, TestSignalName => "SDA", RefSignal => SCLIn, RefSignalName => "SCL", HoldHigh => thold_SDA_SCL_FASTMODE_EQ_0_noedge_negedge, HoldLow => thold_SDA_SCL_FASTMODE_EQ_0_noedge_negedge, CheckEnabled => FASTMODE = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SDAH_SCL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDAH_SCL ); -- Data Hold Time, fast mode VitalSetupHoldCheck ( TestSignal => SDAIn, TestSignalName => "SDA", RefSignal => SCLIn, RefSignalName => "SCL", HoldHigh => thold_SDA_SCL_FASTMODE_EQ_1_noedge_negedge, HoldLow => thold_SDA_SCL_FASTMODE_EQ_1_noedge_negedge, CheckEnabled => FASTMODE = '1', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SDAH_SCL_FAST, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SDAH_SCL_FAST ); VitalSetupHoldCheck ( TestSignal => SCLIn, TestSignalName => "SCL", RefSignal => SDAIn, RefSignalName => "SDA", SetupHigh => tsetup_SCL_SDA_FASTMODE_EQ_0_noedge_negedge, HoldHigh => thold_SCL_SDA_FASTMODE_EQ_0_noedge_negedge, CheckEnabled => FASTMODE = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SCL_SDAS, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SCL_SDAS ); VitalSetupHoldCheck ( TestSignal => SCLIn, TestSignalName => "SCL", RefSignal => SDAIn, RefSignalName => "SDA", SetupHigh => tsetup_SCL_SDA_FASTMODE_EQ_1_noedge_negedge, HoldHigh => thold_SCL_SDA_FASTMODE_EQ_1_noedge_negedge, CheckEnabled => FASTMODE = '1', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SCL_SDAS_FAST, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SCL_SDAS_FAST ); -- Set up time for a STOP, standard mode VitalSetupHoldCheck ( TestSignal => SCLIn, TestSignalName => "SCL", RefSignal => SDAIn, RefSignalName => "SDA", SetupHigh => tsetup_SCL_SDA_FASTMODE_EQ_0_noedge_posedge, CheckEnabled => FASTMODE = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SCL_SDAP, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SCL_SDAP ); -- Set up time for a STOP, fast mode VitalSetupHoldCheck ( TestSignal => SCLIn, TestSignalName => "SCL", RefSignal => SDAIn, RefSignalName => "SDA", SetupHigh => tsetup_SCL_SDA_FASTMODE_EQ_1_noedge_posedge, CheckEnabled => FASTMODE = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SCL_SDAP_FAST, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SCL_SDAP_FAST ); -- standard mode VitalPeriodPulseCheck ( TestSignal => SCLIn, TestSignalName => "SCL", Period => tperiod_SCL_FASTMODE_EQ_0, PulseWidthLow => tpw_SCL_FASTMODE_EQ_0_negedge, PulseWidthHigh => tpw_SCL_FASTMODE_EQ_0_posedge, PeriodData => PD_SCL, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCL, HeaderMsg => InstancePath & PartID, CheckEnabled => FASTMODE = '0' ); -- fast mode VitalPeriodPulseCheck ( TestSignal => SCLIn, TestSignalName => "SCL", Period => tperiod_SCL_FASTMODE_EQ_1, PulseWidthLow => tpw_SCL_FASTMODE_EQ_1_negedge, PulseWidthHigh => tpw_SCL_FASTMODE_EQ_1_posedge, PeriodData => PD_SCL_FAST, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCL_FAST, HeaderMsg => InstancePath & PartID, CheckEnabled => FASTMODE = '1' ); Violation := Tviol_SDAS_SCL OR Tviol_SDAH_SCL OR Tviol_SCL_SDAS OR Tviol_SCL_SDAP OR Pviol_SCL OR Tviol_SDAS_SCL_FAST OR Tviol_SDAH_SCL_FAST OR Tviol_SCL_SDAS_FAST OR Tviol_SCL_SDAP_FAST OR Pviol_SCL_FAST; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS VITALTimingCheck; --------------------------------- -- detects START condition --------------------------------- start_proc: PROCESS(SDAIn, SCLIn) BEGIN IF falling_edge(SDAIn) AND SCLIn /= '0' THEN start <= '1', '0' AFTER 1 ns; END IF; END PROCESS start_proc; --------------------------------- -- detects STOP condition --------------------------------- stop_proc: PROCESS(SDAIn, SCLIn) BEGIN IF rising_edge(SDAIn) AND SCLIn /= '0' THEN IF standard_mode = TRUE THEN stop_del <= '1' AFTER tdevice_TBUF_S, '0' AFTER tdevice_TBUF_S + 1 ns; ELSE stop_del <= '1' AFTER tdevice_TBUF_F, '0' AFTER tdevice_TBUF_F + 1 ns; END IF; stop <= '1', '0' AFTER 1 ns; END IF; END PROCESS stop_proc; --------------------------------- -- bus busy --------------------------------- bus_busy_del_proc: PROCESS(start, stop_del) BEGIN IF start = '1' THEN busy_del <= '1'; ELSIF stop_del = '1' THEN busy_del <= '0'; END IF; END PROCESS bus_busy_del_proc; --------------------------------- -- bus busy --------------------------------- bus_busy_proc: PROCESS(start, stop) BEGIN IF start = '1' THEN busy <= '1'; ELSIF stop = '1' THEN busy <= '0'; END IF; END PROCESS bus_busy_proc; invalid_stop_start: PROCESS(busy_del, busy) BEGIN IF busy'EVENT AND busy = '1' AND NOT(busy_del'EVENT) AND busy = busy_del THEN REPORT("INVALID START CONDITION"); END IF; END PROCESS invalid_stop_start; clk_cnt_proc: PROCESS(Start, stop_del, SCLIn) BEGIN IF Start = '1' OR stop_del = '1' THEN clk_cnt <= 0 AFTER 1 ns; ELSIF rising_edge(SCLIn) THEN clk_cnt <= (clk_cnt + 1) MOD 9 AFTER 1 ns; END IF; END PROCESS clk_cnt_proc; ---------------------------------------------------------------------------- -- sequential process for reset control and FSM state transition ---------------------------------------------------------------------------- StateTransition : PROCESS(SCLIn, stop_del, ISELNeg) BEGIN IF falling_edge(ISELNeg) AND RST = '1' THEN current_state <= IDLE; VND_IDL := "00000001"; VND_IDH := "00000000"; DEV_IDL := "00000110"; DEV_IDH := "00000000"; DEV_REV := "00000000"; FRQ_LOW := "00011001"; FRQ_HIGH := "01100100"; REG_8 := "00110100"; RSEN_R := "00000000"; CTL0 := "10000001"; REG_E := "00000001"; ELSIF falling_edge(ISELNeg) AND RST = '0' THEN --reset pulse < trp, I2c logic not reseted VND_IDL := "00000001"; VND_IDH := "00000000"; DEV_IDL := "00000110"; DEV_IDH := "00000000"; DEV_REV := "00000000"; FRQ_LOW := "00011001"; FRQ_HIGH := "01100100"; REG_8 := "00110100"; RSEN_R := "00000000"; CTL0 := "10000001"; REG_E := "00000001"; END IF; IF ISELNeg = '0' THEN IF stop_del = '1' AND Byte_received = FALSE THEN current_state <= IDLE; ELSIF rising_edge(SCLIn) THEN current_state <= next_state; END IF; END IF; END PROCESS StateTransition; --------------------------------------------------------------------------- -- Main Behavior Process -- combinational process for next state generation --------------------------------------------------------------------------- StateGen :PROCESS(Start, stop_del, stop, clk_cnt, wr_out) BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- CASE current_state IS WHEN IDLE => IF Start = '1' AND Start'EVENT THEN next_state <= CONTROL_BYTE; END IF; WHEN CONTROL_BYTE => IF (rising_edge(stop_del)) THEN next_state <= IDLE; ELSE IF (clk_cnt = 8 AND clk_cnt'EVENT) THEN IF Slave_ID = TRUE THEN IF SDAIn = '1' THEN next_state <= READ;--read ELSE next_state <= COMMAND;--write END IF; ELSE next_state <= IDLE; END IF; END IF; END IF; WHEN COMMAND => IF (rising_edge(stop_del)) THEN next_state <= IDLE; ELSE IF (clk_cnt = 8 AND clk_cnt'EVENT) THEN IF to_nat(command_byte(6 downto 0) & SDAIn) <15 THEN next_state <= WRITE; ELSE next_state <= IDLE; END IF; END IF; END IF; WHEN WRITE => IF (Start'EVENT AND Start = '1' AND wr_in = '0') THEN next_state <= CONTROL_BYTE; ELSIF (stop'EVENT AND stop = '1') THEN IF (Byte_received = TRUE and clk_cnt = 1) THEN next_state <= WRITE; ELSE next_state <= IDLE; END IF; ELSIF (wr_out = '1') THEN next_state <= IDLE; END IF; WHEN READ => IF (clk_cnt'EVENT ) THEN --first bit after ACK IF (clk_cnt = 0 AND Firstbyte_sent = TRUE) THEN --not acknowladge from MASTER IF SDAIn = '1' THEN next_state <= IDLE; END IF; END IF; END IF; END CASE; END PROCESS StateGen; --------------------------------------------------------------------------- --FSM Output generation and general funcionality --------------------------------------------------------------------------- Functional : PROCESS(current_state, stop, clk_cnt, wr_out, SCLIn) VARIABLE command_byte_tmp : std_logic_vector(7 downto 0); VARIABLE data_byte_tmp : std_logic_vector(7 downto 0); VARIABLE data_byte : std_logic_vector(7 downto 0); VARIABLE Address_byte : INTEGER := 0; VARIABLE num : INTEGER := 7; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- CASE current_state IS WHEN IDLE => Slave_ID <= FALSE; Firstbyte_sent <= FALSE; Release_SDA <= FALSE; Byte_received <= FALSE; num := 7; IF falling_edge(SCLIn) THEN SDA_zd <= 'Z'; END IF; WHEN CONTROL_BYTE => Byte_received <= FALSE; Firstbyte_sent <= FALSE; Release_SDA <= FALSE; IF (clk_cnt /= 0 AND clk_cnt'EVENT) THEN first_byte <= first_byte(8 downto 0) & SDAIn; END IF; IF (clk_cnt = 7 AND clk_cnt'EVENT) THEN IF (first_byte(5 downto 0) & SDAIn = "1110000") THEN Slave_ID <= TRUE; ELSE Slave_ID <= FALSE; END IF; END IF; IF falling_edge(SCLIn) THEN IF clk_cnt /= 8 THEN SDA_zd <= 'Z'; ELSE IF Slave_ID THEN SDA_zd <= '0'; ELSE SDA_zd <= 'Z'; END IF; END IF; END IF; WHEN COMMAND => IF (clk_cnt /= 0 AND clk_cnt'EVENT) THEN command_byte <= command_byte(8 downto 0) & SDAIn; command_byte_tmp := command_byte_tmp(6 downto 0) & SDAIn; END IF; IF (clk_cnt = 8 AND clk_cnt'EVENT) THEN Address_byte := to_nat(command_byte_tmp); IF (to_nat(command_byte_tmp) > 15) THEN REPORT "invalid register address"; END IF; END IF; IF falling_edge(SCLIn) THEN IF clk_cnt /= 8 THEN SDA_zd <= 'Z'; ELSE SDA_zd <= '0'; END IF; END IF; WHEN WRITE => IF (clk_cnt /= 0 AND clk_cnt'EVENT AND wr_in= '0') THEN data_byte := data_byte(6 downto 0)& SDAIn; END IF; IF (clk_cnt = 8 AND clk_cnt'EVENT AND wr_in= '0') THEN Byte_received <= TRUE; data_byte_tmp := data_byte; END IF; IF (stop'EVENT AND stop = '1' AND clk_cnt = 1 AND Byte_received = TRUE) THEN wr_in <= '1'; END IF; IF (wr_out = '1') THEN wr_in <= '0'; IF Address_byte = 8 THEN REG_8 := data_byte_tmp(7 downto 0); ELSIF Address_byte = 10 THEN CTL0 := data_byte_tmp(7 downto 0); ELSIF Address_byte = 14 THEN REG_E := data_byte_tmp(7 downto 0); END IF; END IF; IF falling_edge(SCLIn) THEN IF wr_in = '0' THEN IF clk_cnt /= 8 THEN SDA_zd <= 'Z'; ELSE SDA_zd <= '0'; END IF; ELSE SDA_zd <= 'Z'; END IF; END IF; WHEN READ => IF (clk_cnt'EVENT AND clk_cnt = 8) THEN Firstbyte_sent <= TRUE; END IF; IF (clk_cnt'EVENT ) THEN --first bit after ACK IF (clk_cnt = 0 AND Firstbyte_sent = TRUE) THEN --not acknowladge from MASTER IF SDAIn = '1' THEN Release_SDA <= TRUE; -- release SDA END IF; ELSE Release_SDA <= FALSE; END IF; END IF; IF falling_edge(SCLIn) THEN IF Release_SDA = TRUE THEN SDA_zd <= 'Z'; ELSIF clk_cnt /= 8 THEN SDA_zd <= Config_reg(num); CASE Address_byte IS WHEN 0 => SDA_zd <= VND_IDL(num); WHEN 1 => SDA_zd <= VND_IDH(num); WHEN 2 => SDA_zd <= DEV_IDL(num); WHEN 3 => SDA_zd <= DEV_IDH(num); WHEN 4 => SDA_zd <= DEV_REV(num); WHEN 6 => SDA_zd <= FRQ_LOW(num); WHEN 7 => SDA_zd <= FRQ_HIGH(num); WHEN 8 => SDA_zd <= REG_8(num); WHEN 9 => SDA_zd <= RSEN_R(num); WHEN 10 => SDA_zd <= CTL0(num); WHEN 14 => SDA_zd <= REG_E(num); WHEN others => null; END CASE; num := (num+7) MOD 8; ELSE SDA_zd <= 'Z'; END IF; END IF; END CASE; END PROCESS Functional; delay_SDA: PROCESS(SDA_zd) VARIABLE SDA_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay ( OutSignal => SDAOut, OutSignalName => "SDAOut", OutTemp => SDA_zd, GlitchData => SDA_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SCLIn'LAST_EVENT, PathDelay => tpd_SCL_SDA, PathCondition => FASTMODE = '1' AND SCLIn = '0'), 1 => (InputChangeTime => SCLIn'LAST_EVENT, PathDelay => tpd_SCL_SDA, PathCondition => FASTMODE = '0' AND SCLIn = '0') ) ); END PROCESS delay_SDA; END BLOCK; END vhdl_behavioral;