-------------------------------------------------------------------------------- -- File Name: p9515.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 02 Dec 27 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IF -- Technology: -- Part: P9515 -- -- Description: I2C Bus Repeater -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY p9515 IS GENERIC ( -- tipd delays: interconnect path delays tipd_EN : VitalDelayType01 := VitalZeroDelay01; tipd_SCL0 : VitalDelayType01 := VitalZeroDelay01; tipd_SCL1 : VitalDelayType01 := VitalZeroDelay01; tipd_SDA0 : VitalDelayType01 := VitalZeroDelay01; tipd_SDA1 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_EN_SDA0 : VitalDelayType01Z := UnitDelay01Z; tpd_SDA0_SDA1 : VitalDelayType01Z := UnitDelay01Z; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( EN : IN std_ulogic := 'H'; SCL0 : INOUT std_ulogic := 'U'; SDA1 : INOUT std_ulogic := 'U'; SCL1 : INOUT std_ulogic := 'U'; SDA0 : INOUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of p9515 : ENTITY IS TRUE; END p9515; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of p9515 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL EN_ipd : std_ulogic := 'U'; SIGNAL SCL0_ipd : std_ulogic := 'U'; SIGNAL SCL1_ipd : std_ulogic := 'U'; SIGNAL SDA0_ipd : std_ulogic := 'U'; SIGNAL SDA1_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_2 : VitalWireDelay (EN_ipd, EN, tipd_EN); w_3 : VitalWireDelay (SCL0_ipd, SCL0, tipd_SCL0); w_4 : VitalWireDelay (SCL1_ipd, SCL1, tipd_SCL1); w_5 : VitalWireDelay (SDA0_ipd, SDA0, tipd_SDA0); w_6 : VitalWireDelay (SDA1_ipd, SDA1, tipd_SDA1); END BLOCK; ---------------------------------------------------------------------------- -- SDA Behavior Process ---------------------------------------------------------------------------- SDA : PROCESS (SDA0_ipd, SDA1_ipd, EN_ipd) VARIABLE a0in : std_ulogic := 'U'; VARIABLE a0out : std_ulogic := 'U'; VARIABLE a1in : std_ulogic := 'U'; VARIABLE a1out : std_ulogic := 'U'; VARIABLE EN_nwv : UX01; -- Functionality Results Variables VARIABLE SDA0_zd : std_ulogic := 'U'; VARIABLE SDA1_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE SDA0_GlitchData : VitalGlitchDataType; VARIABLE SDA1_GlitchData : VitalGlitchDataType; BEGIN EN_nwv := to_UX01(EN_ipd); IF EN_nwv = '0' THEN A0in := 'Z'; A1in := 'Z'; ELSE A0in := a1out; A1in := a0out; END IF; IF a0in = '0' THEN SDA0_zd := '0'; a0out := 'Z'; ELSE a0out := SDA0_ipd; SDA0_zd := 'Z'; END IF; IF a1in = '0' THEN SDA1_zd := '0'; a1out := 'Z'; ELSE a1out := SDA1_ipd; SDA1_zd := 'Z'; END IF; IF EN_nwv /= '0' THEN A0in := a1out; A1in := a0out; END IF; IF a0in = '0' THEN SDA0_zd := '0'; ELSE SDA0_zd := 'Z'; END IF; IF a1in = '0' THEN SDA1_zd := '0'; ELSE SDA1_zd := 'Z'; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => SDA0, OutSignalName => "SDA0", OutTemp => SDA0_zd, GlitchData => SDA0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SDA1_ipd'LAST_EVENT, PathDelay => tpd_SDA0_SDA1, PathCondition => TRUE), 1 => (InputChangeTime => EN_ipd'LAST_EVENT, PathDelay => tpd_EN_SDA0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => SDA1, OutSignalName => "SDA1", OutTemp => SDA1_zd, GlitchData => SDA1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SDA0_ipd'LAST_EVENT, PathDelay => tpd_SDA0_SDA1, PathCondition => TRUE), 1 => (InputChangeTime => EN_ipd'LAST_EVENT, PathDelay => tpd_EN_SDA0, PathCondition => TRUE) ) ); END PROCESS SDA; ---------------------------------------------------------------------------- -- SCL Behavior Process ---------------------------------------------------------------------------- SCL : PROCESS (SCL0_ipd, SCL1_ipd, EN_ipd) VARIABLE a0in : std_ulogic := 'U'; VARIABLE a0out : std_ulogic := 'U'; VARIABLE a1in : std_ulogic := 'U'; VARIABLE a1out : std_ulogic := 'U'; VARIABLE EN_nwv : UX01; -- Functionality Results Variables VARIABLE SCL0_zd : std_ulogic := 'U'; VARIABLE SCL1_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE SCL0_GlitchData : VitalGlitchDataType; VARIABLE SCL1_GlitchData : VitalGlitchDataType; BEGIN EN_nwv := to_UX01(EN_ipd); IF EN_nwv = '0' THEN A0in := 'Z'; A1in := 'Z'; ELSE A0in := a1out; A1in := a0out; END IF; IF a0in = '0' THEN SCL0_zd := '0'; a0out := 'Z'; ELSE a0out := SCL0_ipd; SCL0_zd := 'Z'; END IF; IF a1in = '0' THEN SCL1_zd := '0'; a1out := 'Z'; ELSE a1out := SCL1_ipd; SCL1_zd := 'Z'; END IF; IF EN_nwv /= '0' THEN A0in := a1out; A1in := a0out; END IF; IF a0in = '0' THEN SCL0_zd := '0'; ELSE SCL0_zd := 'Z'; END IF; IF a1in = '0' THEN SCL1_zd := '0'; ELSE SCL1_zd := 'Z'; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => SCL0, OutSignalName => "SCL0", OutTemp => SCL0_zd, GlitchData => SCL0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SCL1_ipd'LAST_EVENT, PathDelay => tpd_SDA0_SDA1, PathCondition => TRUE), 1 => (InputChangeTime => EN_ipd'LAST_EVENT, PathDelay => tpd_EN_SDA0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => SCL1, OutSignalName => "SCL1", OutTemp => SCL1_zd, GlitchData => SCL1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SCL0_ipd'LAST_EVENT, PathDelay => tpd_SDA0_SDA1, PathCondition => TRUE), 1 => (InputChangeTime => EN_ipd'LAST_EVENT, PathDelay => tpd_EN_SDA0, PathCondition => TRUE) ) ); END PROCESS SCL; END vhdl_behavioral;