-------------------------------------------------------------------------------- -- File Name: max9121.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- v1.0 D.Randjelovic 05 Nov 18 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IF -- Technology: CMOS -- Part: MAX9121 -- -- Description: Quad LVDS Receiver -- -- For correct simulation, simulator resolution should be set to 1ps -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- TOP ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY max9121 IS GENERIC ( -- tipd delays: interconnect path delays tipd_IN1 : VitalDelayType01 := VitalZeroDelay01; tipd_IN1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_IN2 : VitalDelayType01 := VitalZeroDelay01; tipd_IN2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_IN3 : VitalDelayType01 := VitalZeroDelay01; tipd_IN3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_IN4 : VitalDelayType01 := VitalZeroDelay01; tipd_IN4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_EN : VitalDelayType01 := VitalZeroDelay01; tipd_ENNeg : VitalDelayType01 := VitalZeroDelay01; -- generic control parameters InstancePath : string := DefaultInstancePath; TimingChecksOn : boolean := DefaultTimingChecks; MsgOn : boolean := DefaultMsgOn; XOn : boolean := DefaultXon; -- For FMF SDF technology file usage TimingModel : string := DefaultTimingModel ); PORT ( IN1 : IN std_ulogic := 'U'; IN1Neg : IN std_ulogic := 'U'; IN2 : IN std_ulogic := 'U'; IN2Neg : IN std_ulogic := 'U'; IN3 : IN std_ulogic := 'U'; IN3Neg : IN std_ulogic := 'U'; IN4 : IN std_ulogic := 'U'; IN4Neg : IN std_ulogic := 'U'; EN : IN std_ulogic := 'U'; ENNeg : IN std_ulogic := 'U'; OUT1 : OUT std_ulogic := 'Z'; OUT2 : OUT std_ulogic := 'Z'; OUT3 : OUT std_ulogic := 'Z'; OUT4 : OUT std_ulogic := 'Z' ); ATTRIBUTE VITAL_LEVEL0 of max9121 : ENTITY IS TRUE; END max9121; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- DIFFREC ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY max9121_1 IS GENERIC ( -- tipd delays: interconnect path delays tipd_RIN : VitalDelayType01 := VitalZeroDelay01; tipd_RINNeg : VitalDelayType01 := VitalZeroDelay01; tipd_REN : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_RIN_ROUT : VitalDelayType01 := UnitDelay01; tpd_REN_ROUT : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths tpw_RIN_posedge : VitalDelayType := UnitDelay; -- tperiod_min (calculated as 1/max freq) tperiod_RIN : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : string := DefaultInstancePath; TimingChecksOn : boolean := DefaultTimingChecks; MsgOn : boolean := DefaultMsgOn; XOn : boolean := DefaultXon; -- For FMF SDF technology file usage TimingModel : string := DefaultTimingModel ); PORT ( RIN : IN std_ulogic := 'U'; RINNeg : IN std_ulogic := 'U'; REN : IN std_ulogic := 'U'; RENNeg : IN std_ulogic := 'U'; ROUT : OUT std_ulogic := 'Z' ); ATTRIBUTE VITAL_LEVEL0 of max9121_1 : ENTITY IS TRUE; END max9121_1; -------------------------------------------------------------------------------- -- DIFFREC ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of max9121_1 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT PartID : string := "MAX9121_1"; -- ipd SIGNAL RIN_ipd : std_ulogic := 'U'; SIGNAL RINNeg_ipd : std_ulogic := 'U'; SIGNAL REN_ipd : std_ulogic := 'U'; SIGNAL RENNeg_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (RIN_ipd, RIN, tipd_RIN); w_2 : VitalWireDelay (RINNeg_ipd, RINNeg, tipd_RINNeg); w_3 : VitalWireDelay (REN_ipd, REN, tipd_REN); w_4 : VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( RIN : IN std_ulogic := 'U'; RINNeg : IN std_ulogic := 'U'; REN : IN std_ulogic := 'U'; RENNeg : IN std_ulogic := 'U'; ROUT : OUT std_ulogic := 'Z' ); PORT MAP ( RIN => RIN_ipd, RINNeg => RINNeg_ipd, REN => REN_ipd, RENNeg => RENNeg_ipd, ROUT => ROUT ); BEGIN ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehaviour: PROCESS(RIN, RINNeg, REN, RENNeg) -- Functionality Results Variables VARIABLE ROUT_zd : std_logic := 'Z'; VARIABLE PrevData : std_logic_vector(0 to 1); -- Glitch Detection Variables VARIABLE ROUT_GlitchData : VitalGlitchDataType; -- Timing Check Variables VARIABLE Pviol_RIN : X01 := '0'; VARIABLE PD_RIN : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RINNeg : X01 := '0'; VARIABLE PD_RINNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN ---------------------------------------------------------------------------- -- Timing Check Section ---------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- PulseWidth and Period Check for RIN VitalPeriodPulseCheck ( TestSignal => RIN, TestSignalName => "RIN", PulseWidthLow => tpw_RIN_posedge, PulseWidthHigh => tpw_RIN_posedge, Period => tperiod_RIN, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_RIN, Violation => Pviol_RIN ); -- PulseWidth and Period Check for RINNeg VitalPeriodPulseCheck ( TestSignal => RINNeg, TestSignalName => "RINNeg", PulseWidthLow => tpw_RIN_posedge, PulseWidthHigh => tpw_RIN_posedge, Period => tperiod_RIN, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_RINNeg, Violation => Pviol_RINNeg ); Violation := Pviol_RIN OR Pviol_RINNeg; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; ---------------------------------------------------------------------------- -- Functionality Section ---------------------------------------------------------------------------- IF REN = '1' AND RENNeg /= '1' THEN IF RIN = 'Z' OR RINNeg = 'Z' THEN ROUT_zd := '1'; ELSE VitalStateTable ( StateTable => Diff_rec_tab, DataIn => (RIN, RINNeg), Result => ROUT_zd, PreviousDataIn => PrevData ); END IF; ELSE ROUT_zd := 'Z'; END IF; ---------------------------------------------------------------------------- -- Path Delay Section ---------------------------------------------------------------------------- VitalPathDelay01Z( OutSignal => ROUT, OutSignalName => "ROUT", OutTemp => ROUT_zd, GlitchData => ROUT_GlitchData, Paths => ( 0 => (InputChangeTime => RIN'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_RIN_ROUT), PathCondition => REN = '1' AND RENNeg /= '1'), 1 => (InputChangeTime => REN'LAST_EVENT, PathDelay => tpd_REN_ROUT, PathCondition => TRUE), 2 => (InputChangeTime => RENNeg'LAST_EVENT, PathDelay => tpd_REN_ROUT, PathCondition => TRUE) ) ); END PROCESS VITALBehaviour; END BLOCK behavior; END vhdl_behavioral; -------------------------------------------------------------------------------- -- TOP ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of max9121 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; COMPONENT max9121_1 GENERIC ( -- tipd delays: interconnect path delays tipd_RIN : VitalDelayType01 := VitalZeroDelay01; tipd_RINNeg : VitalDelayType01 := VitalZeroDelay01; tipd_REN : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_RIN_ROUT : VitalDelayType01 := UnitDelay01; tpd_REN_ROUT : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths tpw_RIN_posedge : VitalDelayType := UnitDelay; -- tperiod_min (calculated as 1/max freq) tperiod_RIN : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : string := DefaultInstancePath; TimingChecksOn : boolean := DefaultTimingChecks; MsgOn : boolean := DefaultMsgOn; XOn : boolean := DefaultXon; -- For FMF SDF technology file usage TimingModel : string := DefaultTimingModel ); PORT ( RIN : IN std_ulogic := 'U'; RINNeg : IN std_ulogic := 'U'; REN : IN std_ulogic := 'U'; RENNeg : IN std_ulogic := 'U'; ROUT : OUT std_ulogic := 'Z' ); END COMPONENT; FOR ALL : max9121_1 use entity work.max9121_1(vhdl_behavioral); BEGIN -- instantiate first component - channel 1 CH_1 : max9121_1 GENERIC MAP ( -- tipd delays: interconnect path delays tipd_RIN => tipd_IN1, tipd_RINNeg => tipd_IN1Neg, tipd_REN => tipd_EN, tipd_RENNeg => tipd_ENNeg, -- generic control parameters InstancePath => DefaultInstancePath, TimingChecksOn => TRUE, MsgOn => DefaultMsgOn, XOn => DefaultXon, -- For FMF SDF technology file usage TimingModel => DefaultTimingModel ) PORT MAP ( RIN => IN1, RINNeg => IN1Neg, REN => EN, RENNeg => ENNeg, ROUT => OUT1 ); -- instantiate second component - channel 2 CH_2 : max9121_1 GENERIC MAP ( -- tipd delays: interconnect path delays tipd_RIN => tipd_IN2, tipd_RINNeg => tipd_IN2Neg, tipd_REN => tipd_EN, tipd_RENNeg => tipd_ENNeg, -- generic control parameters InstancePath => DefaultInstancePath, TimingChecksOn => TRUE, MsgOn => DefaultMsgOn, XOn => DefaultXon, -- For FMF SDF technology file usage TimingModel => DefaultTimingModel ) PORT MAP ( RIN => IN2, RINNeg => IN2Neg, REN => EN, RENNeg => ENNeg, ROUT => OUT2 ); -- instantiate third component - channel 3 CH_3 : max9121_1 GENERIC MAP ( -- tipd delays: interconnect path delays tipd_RIN => tipd_IN3, tipd_RINNeg => tipd_IN3Neg, tipd_REN => tipd_EN, tipd_RENNeg => tipd_ENNeg, -- generic control parameters InstancePath => DefaultInstancePath, TimingChecksOn => TRUE, MsgOn => DefaultMsgOn, XOn => DefaultXon, -- For FMF SDF technology file usage TimingModel => DefaultTimingModel ) PORT MAP ( RIN => IN3, RINNeg => IN3Neg, REN => EN, RENNeg => ENNeg, ROUT => OUT3 ); -- instantiate fourth component - channel 4 CH_4 : max9121_1 GENERIC MAP ( -- tipd delays: interconnect path delays tipd_RIN => tipd_IN4, tipd_RINNeg => tipd_IN4Neg, tipd_REN => tipd_EN, tipd_RENNeg => tipd_ENNeg, -- generic control parameters InstancePath => DefaultInstancePath, TimingChecksOn => TRUE, MsgOn => DefaultMsgOn, XOn => DefaultXon, -- For FMF SDF technology file usage TimingModel => DefaultTimingModel ) PORT MAP ( RIN => IN4, RINNeg => IN4Neg, REN => EN, RENNeg => ENNeg, ROUT => OUT4 ); END vhdl_behavioral;