-------------------------------------------------------------------------------- -- File Name: lvd117.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 02 Dec 12 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IF -- Technology: LVDS -- Part: LVD117 -- -- Description: LVDS Repeater -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY lvd117 IS GENERIC ( -- tipd delays: interconnect path delays tipd_EA : VitalDelayType01 := VitalZeroDelay01; tipd_EB : VitalDelayType01 := VitalZeroDelay01; tipd_EC : VitalDelayType01 := VitalZeroDelay01; tipd_ED : VitalDelayType01 := VitalZeroDelay01; tipd_EE : VitalDelayType01 := VitalZeroDelay01; tipd_EF : VitalDelayType01 := VitalZeroDelay01; tipd_EG : VitalDelayType01 := VitalZeroDelay01; tipd_EH : VitalDelayType01 := VitalZeroDelay01; tipd_EM : VitalDelayType01 := VitalZeroDelay01; tipd_A : VitalDelayType01 := VitalZeroDelay01; tipd_ANeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_EM_AY : VitalDelayType01Z := UnitDelay01Z; tpd_A_AY : VitalDelayType01 := UnitDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( EA : IN std_ulogic := 'U'; EB : IN std_ulogic := 'U'; EC : IN std_ulogic := 'U'; ED : IN std_ulogic := 'U'; EE : IN std_ulogic := 'U'; EF : IN std_ulogic := 'U'; EG : IN std_ulogic := 'U'; EH : IN std_ulogic := 'U'; EM : IN std_ulogic := 'U'; A : IN std_ulogic := 'U'; ANeg : IN std_ulogic := 'U'; AY : OUT std_ulogic := 'U'; AYNeg : OUT std_ulogic := 'U'; BY : OUT std_ulogic := 'U'; BYNeg : OUT std_ulogic := 'U'; CY : OUT std_ulogic := 'U'; CYNeg : OUT std_ulogic := 'U'; DY : OUT std_ulogic := 'U'; DYNeg : OUT std_ulogic := 'U'; EY : OUT std_ulogic := 'U'; EYNeg : OUT std_ulogic := 'U'; FY : OUT std_ulogic := 'U'; FYNeg : OUT std_ulogic := 'U'; GY : OUT std_ulogic := 'U'; GYNeg : OUT std_ulogic := 'U'; HY : OUT std_ulogic := 'U'; HYNeg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of lvd117 : ENTITY IS TRUE; END lvd117; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of lvd117 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL EA_ipd : std_ulogic := 'U'; SIGNAL EB_ipd : std_ulogic := 'U'; SIGNAL EC_ipd : std_ulogic := 'U'; SIGNAL ED_ipd : std_ulogic := 'U'; SIGNAL EE_ipd : std_ulogic := 'U'; SIGNAL EF_ipd : std_ulogic := 'U'; SIGNAL EG_ipd : std_ulogic := 'U'; SIGNAL EH_ipd : std_ulogic := 'U'; SIGNAL EM_ipd : std_ulogic := 'U'; SIGNAL A_ipd : std_ulogic := 'U'; SIGNAL ANeg_ipd : std_ulogic := 'U'; SIGNAL Aint : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (EA_ipd, EA, tipd_EA); w_2 : VitalWireDelay (EB_ipd, EB, tipd_EB); w_3 : VitalWireDelay (EC_ipd, EC, tipd_EC); w_4 : VitalWireDelay (ED_ipd, ED, tipd_ED); w_5 : VitalWireDelay (EE_ipd, EE, tipd_EE); w_6 : VitalWireDelay (EF_ipd, EF, tipd_EF); w_7 : VitalWireDelay (EG_ipd, EG, tipd_EG); w_8 : VitalWireDelay (EH_ipd, EH, tipd_EH); w_9 : VitalWireDelay (EM_ipd, EM, tipd_EM); w_10 : VitalWireDelay (A_ipd, A, tipd_A); w_15 : VitalWireDelay (ANeg_ipd, ANeg, tipd_ANeg); END BLOCK; ---------------------------------------------------------------------------- -- Diff. Receiver Process ---------------------------------------------------------------------------- DiffRec : PROCESS (A_ipd, ANeg_ipd) -- Functionality Results Variables VARIABLE Aint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 1); -- Glitch Detection Variables VARIABLE A_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ VitalStateTable ( StateTable => Diff_rec_tab, DataIn => (A_ipd, ANeg_ipd), Result => Aint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => Aint, OutSignalName => "Aint", OutTemp => Aint_zd, GlitchData => A_GlitchData, Paths => ( 0 => (InputChangeTime => A_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (Aint, EA_ipd, EB_ipd, EC_ipd, ED_ipd, EE_ipd, EF_ipd, EG_ipd, EH_ipd, EM_ipd) -- Functionality Results Variables VARIABLE ANegint : std_ulogic := 'U'; VARIABLE EAint : std_ulogic := 'U'; VARIABLE EBint : std_ulogic := 'U'; VARIABLE ECint : std_ulogic := 'U'; VARIABLE EDint : std_ulogic := 'U'; VARIABLE EEint : std_ulogic := 'U'; VARIABLE EFint : std_ulogic := 'U'; VARIABLE EGint : std_ulogic := 'U'; VARIABLE EHint : std_ulogic := 'U'; VARIABLE AY_zd : std_ulogic := 'U'; VARIABLE AYNeg_zd : std_ulogic := 'U'; VARIABLE BY_zd : std_ulogic := 'U'; VARIABLE BYNeg_zd : std_ulogic := 'U'; VARIABLE CY_zd : std_ulogic := 'U'; VARIABLE CYNeg_zd : std_ulogic := 'U'; VARIABLE DY_zd : std_ulogic := 'U'; VARIABLE DYNeg_zd : std_ulogic := 'U'; VARIABLE EY_zd : std_ulogic := 'U'; VARIABLE EYNeg_zd : std_ulogic := 'U'; VARIABLE FY_zd : std_ulogic := 'U'; VARIABLE FYNeg_zd : std_ulogic := 'U'; VARIABLE GY_zd : std_ulogic := 'U'; VARIABLE GYNeg_zd : std_ulogic := 'U'; VARIABLE HY_zd : std_ulogic := 'U'; VARIABLE HYNeg_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE AY_GlitchData : VitalGlitchDataType; VARIABLE AYNeg_GlitchData : VitalGlitchDataType; VARIABLE BY_GlitchData : VitalGlitchDataType; VARIABLE BYNeg_GlitchData : VitalGlitchDataType; VARIABLE CY_GlitchData : VitalGlitchDataType; VARIABLE CYNeg_GlitchData : VitalGlitchDataType; VARIABLE DY_GlitchData : VitalGlitchDataType; VARIABLE DYNeg_GlitchData : VitalGlitchDataType; VARIABLE EY_GlitchData : VitalGlitchDataType; VARIABLE EYNeg_GlitchData : VitalGlitchDataType; VARIABLE FY_GlitchData : VitalGlitchDataType; VARIABLE FYNeg_GlitchData : VitalGlitchDataType; VARIABLE GY_GlitchData : VitalGlitchDataType; VARIABLE GYNeg_GlitchData : VitalGlitchDataType; VARIABLE HY_GlitchData : VitalGlitchDataType; VARIABLE HYNeg_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ EAint := VitalAND2(a => EM_ipd, b => EA_ipd); EBint := VitalAND2(a => EM_ipd, b => EB_ipd); ECint := VitalAND2(a => EM_ipd, b => EC_ipd); EDint := VitalAND2(a => EM_ipd, b => ED_ipd); EEint := VitalAND2(a => EM_ipd, b => EE_ipd); EFint := VitalAND2(a => EM_ipd, b => EF_ipd); EGint := VitalAND2(a => EM_ipd, b => EG_ipd); EHint := VitalAND2(a => EM_ipd, b => EH_ipd); ANegint := VitalINV(data => Aint); AY_zd := VitalBUFIF1 (data => Aint, enable => EAint); AYNeg_zd := VitalBUFIF1 (data => ANegint, enable => EAint); BY_zd := VitalBUFIF1 (data => Aint, enable => EBint); BYNeg_zd := VitalBUFIF1 (data => ANegint, enable => EBint); CY_zd := VitalBUFIF1 (data => Aint, enable => ECint); CYNeg_zd := VitalBUFIF1 (data => ANegint, enable => ECint); DY_zd := VitalBUFIF1 (data => Aint, enable => EDint); DYNeg_zd := VitalBUFIF1 (data => ANegint, enable => EDint); EY_zd := VitalBUFIF1 (data => Aint, enable => EEint); EYNeg_zd := VitalBUFIF1 (data => ANegint, enable => EEint); FY_zd := VitalBUFIF1 (data => Aint, enable => EFint); FYNeg_zd := VitalBUFIF1 (data => ANegint, enable => EFint); GY_zd := VitalBUFIF1 (data => Aint, enable => EGint); GYNeg_zd := VitalBUFIF1 (data => ANegint, enable => EGint); HY_zd := VitalBUFIF1 (data => Aint, enable => EHint); HYNeg_zd := VitalBUFIF1 (data => ANegint, enable => EHint); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => AY, OutSignalName => "AY", OutTemp => AY_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EAint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EA_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => AY_GlitchData ); VitalPathDelay01Z ( OutSignal => AYNeg, OutSignalName => "AYNeg", OutTemp => AYNeg_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EAint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EA_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => AYNeg_GlitchData ); VitalPathDelay01Z ( OutSignal => BY, OutSignalName => "BY", OutTemp => BY_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EBint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EB_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => BY_GlitchData ); VitalPathDelay01Z ( OutSignal => BYNeg, OutSignalName => "BYNeg", OutTemp => BYNeg_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EBint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EB_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => BYNeg_GlitchData ); VitalPathDelay01Z ( OutSignal => CY, OutSignalName => "CY", OutTemp => CY_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (ECint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EC_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => CY_GlitchData ); VitalPathDelay01Z ( OutSignal => CYNeg, OutSignalName => "CYNeg", OutTemp => CYNeg_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (ECint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EC_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => CYNeg_GlitchData ); VitalPathDelay01Z ( OutSignal => DY, OutSignalName => "DY", OutTemp => DY_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EDint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => ED_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => DY_GlitchData ); VitalPathDelay01Z ( OutSignal => DYNeg, OutSignalName => "DYNeg", OutTemp => DYNeg_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EDint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => ED_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => DYNeg_GlitchData ); VitalPathDelay01Z ( OutSignal => EY, OutSignalName => "EY", OutTemp => EY_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EEint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EE_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => EY_GlitchData ); VitalPathDelay01Z ( OutSignal => EYNeg, OutSignalName => "EYNeg", OutTemp => EYNeg_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EEint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EE_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => EYNeg_GlitchData ); VitalPathDelay01Z ( OutSignal => FY, OutSignalName => "FY", OutTemp => FY_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EFint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EF_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => FY_GlitchData ); VitalPathDelay01Z ( OutSignal => FYNeg, OutSignalName => "FYNeg", OutTemp => FYNeg_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EFint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EF_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => FYNeg_GlitchData ); VitalPathDelay01Z ( OutSignal => GY, OutSignalName => "GY", OutTemp => GY_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EGint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EG_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => GY_GlitchData ); VitalPathDelay01Z ( OutSignal => GYNeg, OutSignalName => "GYNeg", OutTemp => GYNeg_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EGint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EG_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => GYNeg_GlitchData ); VitalPathDelay01Z ( OutSignal => HY, OutSignalName => "HY", OutTemp => HY_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EHint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EH_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => HY_GlitchData ); VitalPathDelay01Z ( OutSignal => HYNeg, OutSignalName => "HYNeg", OutTemp => HYNeg_zd, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A_AY), PathCondition => (EHint = '1')), 1 => (InputChangeTime => EM_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ), 2 => (InputChangeTime => EH_ipd'LAST_EVENT, PathDelay => tpd_EM_AY, PathCondition => TRUE ) ), GlitchData => HYNeg_GlitchData ); END PROCESS; END vhdl_behavioral;