--------------------------------------------------------------------------------
--  File Name: lvd047.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2002 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    02 Nov 18   Initial release
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    IF
--  Technology: LVDS
--  Part:       LVD047
-- 
--  Description: Differential Driver
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY lvd047 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A                   : VitalDelayType01 := VitalZeroDelay01;
        tipd_EN                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_ENNeg               : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_A_Y                  : VitalDelayType01 := UnitDelay01;
        tpd_EN_Y                 : VitalDelayType01Z := UnitDelay01Z;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        Y               : OUT   std_ulogic := 'U';
        YNeg            : OUT   std_ulogic := 'U';
        A               : IN    std_ulogic := 'U';
        EN              : IN    std_ulogic := 'U';
        ENNeg           : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of lvd047 : ENTITY IS TRUE;
END lvd047;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of lvd047 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd               : std_ulogic := 'U';
    SIGNAL EN_ipd              : std_ulogic := 'U';
    SIGNAL ENNeg_ipd           : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (A_ipd, A, tipd_A);
        w_4 : VitalWireDelay (EN_ipd, EN, tipd_EN);
        w_5 : VitalWireDelay (ENNeg_ipd, ENNeg, tipd_ENNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
    VITALBehavior : PROCESS(EN_ipd, ENNeg_ipd, A_ipd)

        -- Functionality Results Variables
        VARIABLE enable     : std_ulogic := 'U';
        VARIABLE Y_zd       : std_ulogic := 'U';
        VARIABLE YNeg_zd    : std_ulogic := 'U';

        -- Output Glitch Detection Variables
        VARIABLE Y_GlitchData    : VitalGlitchDataType;
        VARIABLE YNeg_GlitchData : VitalGlitchDataType;

    BEGIN
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        enable := VitalAND2 (a => EN_ipd, b => not ENNeg_ipd);
        Y_zd := VitalBUFIF1 (data => A_ipd, enable => enable);
        YNeg_zd := VitalBUFIF1 (data => not A_ipd, enable => enable);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       =>  Y,
            OutSignalName   =>  "Y",
            OutTemp         =>  Y_zd,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_A_Y),
                      PathCondition     => (enable = '1')),
                1 => (InputChangeTime   => EN_ipd'LAST_EVENT,
                      PathDelay         => tpd_EN_Y,
                      PathCondition     => TRUE ),
                2 => (InputChangeTime   => ENNeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_EN_Y,
                      PathCondition     => TRUE ) ),
            GlitchData      => Y_GlitchData );

        VitalPathDelay01Z (
            OutSignal       =>  YNeg,
            OutSignalName   =>  "YNeg",
            OutTemp         =>  YNeg_zd,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_A_Y),
                      PathCondition     => (enable = '1')),
                1 => (InputChangeTime   => EN_ipd'LAST_EVENT,
                      PathDelay         => tpd_EN_Y,
                      PathCondition     => TRUE ),
                2 => (InputChangeTime   => ENNeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_EN_Y,
                      PathCondition     => TRUE ) ),
            GlitchData      => YNeg_GlitchData );


    END PROCESS;

END vhdl_behavioral;