-------------------------------------------------------------------------------- -- File Name: if75188.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 98 MAY 26 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IF -- Technology: TTL -- Part: 75188/1488 -- -- Desciption: RS-232 Quad Line Driver -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY if75188 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A : VitalDelayType01 := VitalZeroDelay01; tipd_B1 : VitalDelayType01 := VitalZeroDelay01; tipd_B2 : VitalDelayType01 := VitalZeroDelay01; tipd_C1 : VitalDelayType01 := VitalZeroDelay01; tipd_C2 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A_ANeg : VitalDelayType01 := UnitDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A : IN std_logic := 'U'; B1 : IN std_logic := 'U'; B2 : IN std_logic := 'U'; C1 : IN std_logic := 'U'; C2 : IN std_logic := 'U'; D1 : IN std_logic := 'U'; D2 : IN std_logic := 'U'; ANeg : OUT std_logic := 'U'; BNeg : OUT std_logic := 'U'; CNeg : OUT std_logic := 'U'; DNeg : OUT std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of if75188 : ENTITY IS TRUE; END if75188; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of if75188 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL A_ipd : std_ulogic := 'X'; SIGNAL B1_ipd : std_ulogic := 'X'; SIGNAL B2_ipd : std_ulogic := 'X'; SIGNAL C1_ipd : std_ulogic := 'X'; SIGNAL C2_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (A_ipd, A, tipd_A); w_2 : VitalWireDelay (B1_ipd, B1, tipd_B1); w_3 : VitalWireDelay (B2_ipd, B2, tipd_B2); w_4 : VitalWireDelay (C1_ipd, C1, tipd_C1); w_5 : VitalWireDelay (C2_ipd, C2, tipd_C2); w_6 : VitalWireDelay (D1_ipd, D1, tipd_D1); w_7 : VitalWireDelay (D2_ipd, D2, tipd_D2); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior1 : PROCESS (A_ipd) -- Functionality Results Variables VARIABLE YNeg_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE Y_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ YNeg_zd := VitalINV(data => A_ipd); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => ANeg, OutSignalName => "ANeg", OutTemp => YNeg_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => A_ipd'LAST_EVENT, PathDelay => tpd_A_ANeg, PathCondition => TRUE ) ), GlitchData => Y_GlitchData ); END PROCESS; VitalBehavior2 : PROCESS (B1_ipd, B2_ipd) -- Functionality Results Variables VARIABLE YNeg_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE Y_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ YNeg_zd := VitalNAND2(a=> B1_ipd, b => B2_ipd); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => BNeg, OutSignalName => "BNeg", OutTemp => YNeg_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => B1_ipd'LAST_EVENT, PathDelay => tpd_A_ANeg, PathCondition => TRUE ), 1 => (InputChangeTime => B2_ipd'LAST_EVENT, PathDelay => tpd_A_ANeg, PathCondition => TRUE ) ), GlitchData => Y_GlitchData ); END PROCESS; VitalBehavior3 : PROCESS (C1_ipd, C2_ipd) -- Functionality Results Variables VARIABLE YNeg_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE Y_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ YNeg_zd := VitalNAND2(a=> C1_ipd, b => C2_ipd); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => CNeg, OutSignalName => "CNeg", OutTemp => YNeg_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => C1_ipd'LAST_EVENT, PathDelay => tpd_A_ANeg, PathCondition => TRUE ), 1 => (InputChangeTime => C2_ipd'LAST_EVENT, PathDelay => tpd_A_ANeg, PathCondition => TRUE ) ), GlitchData => Y_GlitchData ); END PROCESS; VitalBehavior4 : PROCESS (D1_ipd, D2_ipd) -- Functionality Results Variables VARIABLE YNeg_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE Y_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ YNeg_zd := VitalNAND2(a=> D1_ipd, b => D2_ipd); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => DNeg, OutSignalName => "DNeg", OutTemp => YNeg_zd, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => D1_ipd'LAST_EVENT, PathDelay => tpd_A_ANeg, PathCondition => TRUE ), 1 => (InputChangeTime => D2_ipd'LAST_EVENT, PathDelay => tpd_A_ANeg, PathCondition => TRUE ) ), GlitchData => Y_GlitchData ); END PROCESS; END vhdl_behavioral;