--------------------------------------------------------------------------------
--  File Name: if75179.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. MUnden    98 MAY 22   initial release
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    IF
--  Technology: TTL
--  Part:       IF75179
-- 
--  Desciption: Differential Driver/Receiver Pair
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY if75179 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_ANeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_A                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D                 : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_A_R             : VitalDelayType01  := UnitDelay01;
        tpd_D_Y             : VitalDelayType01  := UnitDelay01;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        ANeg          : IN    std_logic := 'U';
        A             : IN    std_logic := 'U';
        D             : IN    std_logic := 'U';
        R             : OUT   std_logic := 'U';
        YNeg          : OUT   std_logic := 'U';
        Y             : OUT   std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of if75179 : ENTITY IS TRUE;
END if75179;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of if75179 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL ANeg_ipd          : std_ulogic := 'X';
    SIGNAL A_ipd             : std_ulogic := 'X';
    SIGNAL D_ipd             : std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (ANeg_ipd, ANeg, tipd_ANeg);
        w_2 : VitalWireDelay (A_ipd, A, tipd_A);
        w_3 : VitalWireDelay (D_ipd, D, tipd_D);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Differential Input Process with delay
    ----------------------------------------------------------------------------
    DIFFIn : PROCESS (A_ipd, ANeg_ipd)

        -- Functionality Results Variables
        VARIABLE R_zd           : std_ulogic;
        VARIABLE PrevData       : std_logic_vector(0 to 1);

        -- Output Glitch Detection Variables
        VARIABLE R_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        VitalStateTable (
            StateTable      => diff_rec_tab,
            DataIn          => (A_ipd, ANeg_ipd),
            Result          => R_zd,
            PreviousDataIn  => PrevData
        );

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => R,
            OutSignalName   => "R",
            OutTemp         => R_zd,
            GlitchData      => R_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => tpd_A_R,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => ANeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_A_R,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS;


    ----------------------------------------------------------------------------
    -- VITALBehavior Process
    ----------------------------------------------------------------------------
    VITALBehavior1 : PROCESS(D_ipd)

        -- Functionality Results Variables
        VARIABLE Y_zd       : std_ulogic := 'X';
        VARIABLE YN_zd       : std_ulogic := 'X';

        -- Output Glitch Detection Variables
        VARIABLE Y_GlitchData : VitalGlitchDataType;
        VARIABLE YN_GlitchData : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------

        Y_zd := VitalBUF (data => D_ipd);
        YN_zd := VitalINV (data => D_ipd);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       =>  Y,
            OutSignalName   =>  "Y",
            OutTemp         =>  Y_zd,
            Paths           => (
                0 => (InputChangeTime   => D_ipd'LAST_EVENT,
                      PathDelay         => (tpd_D_Y),
                      PathCondition     => TRUE) ),
            GlitchData      => Y_GlitchData );

        VitalPathDelay01 (
            OutSignal       =>  YNeg,
            OutSignalName   =>  "YNeg",
            OutTemp         =>  YN_zd,
            Paths           => (
                0 => (InputChangeTime   => D_ipd'LAST_EVENT,
                      PathDelay         => (tpd_D_Y),
                      PathCondition     => TRUE) ),
            GlitchData      => YN_GlitchData );

    END PROCESS;

END vhdl_behavioral;