--------------------------------------------------------------------------------
--  File Name: if490.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. MUnden    98 MAY 15   initial release
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    IF
--  Technology: TTL
--  Part:       IF490
-- 
--  Desciption: RS485/RS422 Differential Transceiver
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY if490 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_RINNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_RIN                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_TIN                 : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_RIN_ROUT             : VitalDelayType01  := UnitDelay01;
        tpd_TIN_TOUT             : VitalDelayType01  := UnitDelay01;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        RINNeg          : IN    std_logic := '0';
        RIN             : IN    std_logic := '1';
        TIN             : IN    std_logic := 'U';
        ROUT            : OUT   std_logic := 'U';
        TOUTNeg         : OUT   std_logic := 'U';
        TOUT            : OUT   std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of if490 : ENTITY IS TRUE;
END if490;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of if490 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL RINNeg_ipd          : std_ulogic := 'X';
    SIGNAL RIN_ipd             : std_ulogic := 'X';
    SIGNAL TIN_ipd             : std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (RINNeg_ipd, RINNeg, tipd_RINNeg);
        w_2 : VitalWireDelay (RIN_ipd, RIN, tipd_RIN);
        w_3 : VitalWireDelay (TIN_ipd, TIN, tipd_TIN);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Differential Input Process with delay
    ----------------------------------------------------------------------------
    ECLClock : PROCESS (RIN_ipd, RINNeg_ipd)

        -- Functionality Results Variables
        VARIABLE R_zd           : std_ulogic;
        VARIABLE PrevData       : std_logic_vector(0 to 1);

        -- Output Glitch Detection Variables
        VARIABLE R_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        VitalStateTable (
            StateTable      => diff_rec_tab,
            DataIn          => (RIN_ipd, RINNeg_ipd),
            Result          => R_zd,
            PreviousDataIn  => PrevData
        );

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => ROUT,
            OutSignalName   => "ROUT",
            OutTemp         => R_zd,
            GlitchData      => R_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => RIN_ipd'LAST_EVENT,
                      PathDelay         => tpd_RIN_ROUT,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => RINNeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_RIN_ROUT,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS;


    ----------------------------------------------------------------------------
    -- VITALBehavior Process
    ----------------------------------------------------------------------------
    VITALBehavior1 : PROCESS(TIN_ipd)

        -- Functionality Results Variables
        VARIABLE T_zd       : std_ulogic := 'X';
        VARIABLE TN_zd       : std_ulogic := 'X';

        -- Output Glitch Detection Variables
        VARIABLE T_GlitchData : VitalGlitchDataType;
        VARIABLE TN_GlitchData : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------

        T_zd := VitalBUF (data => TIN_ipd);
        TN_zd := VitalINV (data => TIN_ipd);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       =>  TOUT,
            OutSignalName   =>  "TOUT",
            OutTemp         =>  T_zd,
            Paths           => (
                0 => (InputChangeTime   => TIN_ipd'LAST_EVENT,
                      PathDelay         => (tpd_TIN_TOUT),
                      PathCondition     => TRUE) ),
            GlitchData      => T_GlitchData );

        VitalPathDelay01 (
            OutSignal       =>  TOUTNeg,
            OutSignalName   =>  "TOUTNeg",
            OutTemp         =>  TN_zd,
            Paths           => (
                0 => (InputChangeTime   => TIN_ipd'LAST_EVENT,
                      PathDelay         => (tpd_TIN_TOUT),
                      PathCondition     => TRUE) ),
            GlitchData      => TN_GlitchData );

    END PROCESS;

END vhdl_behavioral;