-------------------------------------------------------------------------------- -- File Name: if4737.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1999 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 99 APR 19 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IF -- Technology: LVTTL -- Part: 75LV4737 -- -- Description: RS-232 Driver/Receiver -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY if4737 IS GENERIC ( -- tipd delays: interconnect path delays tipd_ENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_R1IN : VitalDelayType01 := VitalZeroDelay01; tipd_R2IN : VitalDelayType01 := VitalZeroDelay01; tipd_R3IN : VitalDelayType01 := VitalZeroDelay01; tipd_R4IN : VitalDelayType01 := VitalZeroDelay01; tipd_R5IN : VitalDelayType01 := VitalZeroDelay01; tipd_STBY : VitalDelayType01 := VitalZeroDelay01; tipd_D1IN : VitalDelayType01 := VitalZeroDelay01; tipd_D2IN : VitalDelayType01 := VitalZeroDelay01; tipd_D3IN : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_ENNeg_R5OUT : VitalDelayType01Z := UnitDelay01Z; tpd_R1IN_R1OUT : VitalDelayType01 := UnitDelay01; tpd_D1IN_D1OUT : VitalDelayType01 := UnitDelay01; tpd_STBY_R1OUT : VitalDelayType01Z := UnitDelay01Z; tpd_STBY_D1OUT : VitalDelayType01Z := UnitDelay01Z; -- generic control parameters InstancePath : STRING := DefaultInstancePath; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( ENNeg : IN std_logic := 'U'; R1IN : IN std_logic := 'L'; R1OUT : OUT std_logic := 'U'; R2IN : IN std_logic := 'L'; R2OUT : OUT std_logic := 'U'; R3IN : IN std_logic := 'L'; R3OUT : OUT std_logic := 'U'; R4IN : IN std_logic := 'L'; R4OUT : OUT std_logic := 'U'; R5IN : IN std_logic := 'L'; R5OUT : OUT std_logic := 'U'; STBY : IN std_logic := 'U'; D1OUT : OUT std_logic := 'U'; D1IN : IN std_logic := 'H'; D2OUT : OUT std_logic := 'U'; D2IN : IN std_logic := 'H'; D3OUT : OUT std_logic := 'U'; D3IN : IN std_logic := 'H' ); ATTRIBUTE VITAL_LEVEL0 of if4737 : ENTITY IS TRUE; END if4737; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of if4737 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL ENNeg_ipd : std_ulogic := 'X'; SIGNAL R1IN_ipd : std_ulogic := 'L'; SIGNAL R2IN_ipd : std_ulogic := 'L'; SIGNAL R3IN_ipd : std_ulogic := 'L'; SIGNAL R4IN_ipd : std_ulogic := 'L'; SIGNAL R5IN_ipd : std_ulogic := 'L'; SIGNAL STBY_ipd : std_ulogic := 'X'; SIGNAL D1IN_ipd : std_ulogic := 'H'; SIGNAL D2IN_ipd : std_ulogic := 'H'; SIGNAL D3IN_ipd : std_ulogic := 'H'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (ENNeg_ipd, ENNeg, tipd_ENNeg); w_2 : VitalWireDelay (R1IN_ipd, R1IN, tipd_R1IN); w_3 : VitalWireDelay (R2IN_ipd, R2IN, tipd_R2IN); w_4 : VitalWireDelay (R3IN_ipd, R3IN, tipd_R3IN); w_5 : VitalWireDelay (R4IN_ipd, R4IN, tipd_R4IN); w_6 : VitalWireDelay (R5IN_ipd, R5IN, tipd_R5IN); w_7 : VitalWireDelay (STBY_ipd, STBY, tipd_STBY); w_8 : VitalWireDelay (D1IN_ipd, D1IN, tipd_D1IN); w_9 : VitalWireDelay (D2IN_ipd, D2IN, tipd_D2IN); w_10 : VitalWireDelay (D3IN_ipd, D3IN, tipd_D3IN); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehavior1 : PROCESS(D1IN_ipd, STBY_ipd) -- Functionality Results Variables VARIABLE D_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ D_zd := VitalINVIF0 (data => D1IN_ipd, enable => STBY_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => D1OUT, OutSignalName => "D1OUT", OutTemp => D_zd, Paths => ( 0 => (InputChangeTime => D1IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_D1IN_D1OUT), PathCondition => (STBY_ipd = '0') OR (STBY_ipd = 'L')), 1 => (InputChangeTime => STBY_ipd'LAST_EVENT, PathDelay => tpd_STBY_D1OUT, PathCondition => TRUE ) ), GlitchData => D_GlitchData ); END PROCESS; VITALBehavior2 : PROCESS(D2IN_ipd, STBY_ipd) -- Functionality Results Variables VARIABLE D_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ D_zd := VitalINVIF0 (data => D2IN_ipd, enable => STBY_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => D2OUT, OutSignalName => "D2OUT", OutTemp => D_zd, Paths => ( 0 => (InputChangeTime => D2IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_D1IN_D1OUT), PathCondition => (STBY_ipd = '0') OR (STBY_ipd = 'L')), 1 => (InputChangeTime => STBY_ipd'LAST_EVENT, PathDelay => tpd_STBY_D1OUT, PathCondition => TRUE ) ), GlitchData => D_GlitchData ); END PROCESS; VITALBehavior3 : PROCESS(D3IN_ipd, STBY_ipd) -- Functionality Results Variables VARIABLE D_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ D_zd := VitalINVIF0 (data => D3IN_ipd, enable => STBY_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => D3OUT, OutSignalName => "D3OUT", OutTemp => D_zd, Paths => ( 0 => (InputChangeTime => D3IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_D1IN_D1OUT), PathCondition => (STBY_ipd = '0') OR (STBY_ipd = 'L')), 1 => (InputChangeTime => STBY_ipd'LAST_EVENT, PathDelay => tpd_STBY_D1OUT, PathCondition => TRUE ) ), GlitchData => D_GlitchData ); END PROCESS; VITALBehavior4 : PROCESS(R1IN_ipd, STBY_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ R_zd := VitalINVIF0 (data => R1IN_ipd, enable => STBY_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => R1OUT, OutSignalName => "R1OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R1IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_R1IN_R1OUT), PathCondition => (STBY_ipd = '0') OR (STBY_ipd = 'L')), 1 => (InputChangeTime => STBY_ipd'LAST_EVENT, PathDelay => tpd_STBY_R1OUT, PathCondition => TRUE ) ), GlitchData => R_GlitchData ); END PROCESS; VITALBehavior5 : PROCESS(R2IN_ipd, STBY_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ R_zd := VitalINVIF0 (data => R2IN_ipd, enable => STBY_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => R2OUT, OutSignalName => "R2OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R2IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_R1IN_R1OUT), PathCondition => (STBY_ipd = '0') OR (STBY_ipd = 'L')), 1 => (InputChangeTime => STBY_ipd'LAST_EVENT, PathDelay => tpd_STBY_R1OUT, PathCondition => TRUE ) ), GlitchData => R_GlitchData ); END PROCESS; VITALBehavior6 : PROCESS(R3IN_ipd, STBY_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ R_zd := VitalINVIF0 (data => R3IN_ipd, enable => STBY_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => R3OUT, OutSignalName => "R3OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R3IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_R1IN_R1OUT), PathCondition => (STBY_ipd = '0') OR (STBY_ipd = 'L')), 1 => (InputChangeTime => STBY_ipd'LAST_EVENT, PathDelay => tpd_STBY_R1OUT, PathCondition => TRUE ) ), GlitchData => R_GlitchData ); END PROCESS; VITALBehavior7 : PROCESS(R4IN_ipd, STBY_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ R_zd := VitalINVIF0 (data => R4IN_ipd, enable => STBY_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => R4OUT, OutSignalName => "R4OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R4IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_R1IN_R1OUT), PathCondition => (STBY_ipd = '0') OR (STBY_ipd = 'L')), 1 => (InputChangeTime => STBY_ipd'LAST_EVENT, PathDelay => tpd_STBY_R1OUT, PathCondition => TRUE ) ), GlitchData => R_GlitchData ); END PROCESS; VITALBehavior8 : PROCESS(R5IN_ipd, STBY_ipd, ENNeg_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'X'; VARIABLE enint : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ enint := VitalNAND2 (a => STBY_ipd, b => ENNeg_ipd); R_zd := VitalINVIF1 (data => R5IN_ipd, enable => enint ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => R5OUT, OutSignalName => "R5OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R5IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_R1IN_R1OUT), PathCondition => (STBY_ipd = '0') OR (STBY_ipd = 'L')), 1 => (InputChangeTime => STBY_ipd'LAST_EVENT, PathDelay => tpd_STBY_R1OUT, PathCondition => TRUE ), 2 => (InputChangeTime => ENNeg_ipd'LAST_EVENT, PathDelay => tpd_STBY_R1OUT, PathCondition => TRUE ) ), GlitchData => R_GlitchData ); END PROCESS; END vhdl_behavioral;