--------------------------------------------------------------------------------
--  File Name: if2631.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Munden   98 APR 16   Initial release based on if75172
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    IF (Interface)
--  Technology: TTL
--  Part:       2631
-- 
--  Desciption: Quad Differential Line Drivers
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY if2631 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A              : VitalDelayType01 := VitalZeroDelay01;
        tipd_G              : VitalDelayType01 := VitalZeroDelay01;
        tipd_GNeg           : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_A_Y                          : VitalDelayType01 := UnitDelay01;
        tpd_G_Y                          : VitalDelayType01Z := UnitDelay01Z;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        A               : IN    std_logic := 'U';
        G               : IN    std_logic := 'U';
        GNeg            : IN    std_logic := 'U';
        Y               : OUT   std_logic := 'U';
        YNeg            : OUT   std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of if2631 : ENTITY IS TRUE;
END if2631;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of if2631 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'X';
    SIGNAL G_ipd            : std_ulogic := 'X';
    SIGNAL GNeg_ipd         : std_ulogic := 'X';

    SIGNAL Gint             : std_ulogic := 'X';
    SIGNAL GNegint          : std_ulogic := 'X';

BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (A_ipd, A, tipd_A);
        w_2: VitalWireDelay (G_ipd, G, tipd_G);
        w_3: VitalWireDelay (GNeg_ipd, GNeg, tipd_GNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedure
    ----------------------------------------------------------------------------

    a_1: VitalINV (q => GNegint, a => GNeg_ipd);

    a_2: VitalOR2 (
            q            => Gint,
            a            => G_ipd,
            b            => GNegint
         );

    a_3: VitalBUFIF1 (
            q            => Y, 
            data         => A_ipd, 
            Enable       => Gint, 
            tpd_data_q   => tpd_A_Y,
            tpd_enable_q => tpd_G_Y
         );

    a_4: VitalINVIF1 (
            q            => YNeg, 
            data         => A_ipd, 
            Enable       => Gint, 
            tpd_data_q   => tpd_A_Y,
            tpd_enable_q => tpd_G_Y
         );


END vhdl_behavioral;