-------------------------------------------------------------------------------- -- File Name: if241.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998, 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. MUnden 98 MAY 13 initial release -- V2.0 R. MUnden 02 MAY 20 re-written as flat part -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IF -- Technology: TTL -- Part: IF241 -- -- Description: RS-232 Transceiver -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY if241 IS GENERIC ( -- tipd delays: interconnect path delays tipd_ENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_R1IN : VitalDelayType01 := VitalZeroDelay01; tipd_R2IN : VitalDelayType01 := VitalZeroDelay01; tipd_R3IN : VitalDelayType01 := VitalZeroDelay01; tipd_R4IN : VitalDelayType01 := VitalZeroDelay01; tipd_R5IN : VitalDelayType01 := VitalZeroDelay01; tipd_SHDN : VitalDelayType01 := VitalZeroDelay01; tipd_T1IN : VitalDelayType01 := VitalZeroDelay01; tipd_T2IN : VitalDelayType01 := VitalZeroDelay01; tipd_T3IN : VitalDelayType01 := VitalZeroDelay01; tipd_T4IN : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_ENNeg_R1OUT : VitalDelayType01Z := UnitDelay01Z; tpd_R1IN_R1OUT : VitalDelayType01 := UnitDelay01; tpd_SHDN_R1OUT : VitalDelayType01Z := UnitDelay01Z; tpd_SHDN_T1OUT : VitalDelayType01Z := UnitDelay01Z; tpd_T1IN_T1OUT : VitalDelayType01 := UnitDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( ENNeg : IN std_ulogic := 'U'; SHDN : IN std_ulogic := 'U'; R1IN : IN std_ulogic := '0'; R2IN : IN std_ulogic := '0'; R3IN : IN std_ulogic := '0'; R4IN : IN std_ulogic := '0'; R5IN : IN std_ulogic := '0'; T1IN : IN std_ulogic := '1'; T2IN : IN std_ulogic := '1'; T3IN : IN std_ulogic := '1'; T4IN : IN std_ulogic := '1'; R1OUT : OUT std_ulogic := 'U'; R2OUT : OUT std_ulogic := 'U'; R3OUT : OUT std_ulogic := 'U'; R4OUT : OUT std_ulogic := 'U'; R5OUT : OUT std_ulogic := 'U'; T1OUT : OUT std_ulogic := 'U'; T2OUT : OUT std_ulogic := 'U'; T3OUT : OUT std_ulogic := 'U'; T4OUT : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of if241 : ENTITY IS TRUE; END if241; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of if241 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL ENNeg_ipd : std_ulogic := 'U'; SIGNAL R1IN_ipd : std_ulogic := 'U'; SIGNAL R2IN_ipd : std_ulogic := 'U'; SIGNAL R3IN_ipd : std_ulogic := 'U'; SIGNAL R4IN_ipd : std_ulogic := 'U'; SIGNAL R5IN_ipd : std_ulogic := 'U'; SIGNAL SHDN_ipd : std_ulogic := 'U'; SIGNAL T1IN_ipd : std_ulogic := 'U'; SIGNAL T2IN_ipd : std_ulogic := 'U'; SIGNAL T3IN_ipd : std_ulogic := 'U'; SIGNAL T4IN_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (ENNeg_ipd, ENNeg, tipd_ENNeg); w_2 : VitalWireDelay (R1IN_ipd, R1IN, tipd_R1IN); w_3 : VitalWireDelay (R2IN_ipd, R2IN, tipd_R2IN); w_4 : VitalWireDelay (R3IN_ipd, R3IN, tipd_R3IN); w_5 : VitalWireDelay (R4IN_ipd, R4IN, tipd_R4IN); w_6 : VitalWireDelay (R5IN_ipd, R5IN, tipd_R5IN); w_7 : VitalWireDelay (SHDN_ipd, SHDN, tipd_SHDN); w_8 : VitalWireDelay (T1IN_ipd, T1IN, tipd_T1IN); w_9 : VitalWireDelay (T2IN_ipd, T2IN, tipd_T2IN); w_10 : VitalWireDelay (T3IN_ipd, T3IN, tipd_T3IN); w_11 : VitalWireDelay (T4IN_ipd, T4IN, tipd_T4IN); END BLOCK; ---------------------------------------------------------------------------- -- VITALBehavior Process ---------------------------------------------------------------------------- VITALBehaviorT1 : PROCESS(T1IN_ipd, SHDN_ipd) -- Functionality Results Variables VARIABLE T_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE T_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ T_zd := VitalINVIF0 (data => T1IN_ipd, enable => SHDN_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => T1OUT, OutSignalName => "T1OUT", OutTemp => T_zd, Paths => ( 0 => (InputChangeTime => T1IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_T1IN_T1OUT), PathCondition => (SHDN_ipd = '0') OR (SHDN_ipd = 'L')), 1 => (InputChangeTime => SHDN_ipd'LAST_EVENT, PathDelay => tpd_SHDN_T1OUT, PathCondition => TRUE ) ), GlitchData => T_GlitchData ); END PROCESS; VITALBehaviorT2 : PROCESS(T2IN_ipd, SHDN_ipd) -- Functionality Results Variables VARIABLE T_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE T_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ T_zd := VitalINVIF0 (data => T2IN_ipd, enable => SHDN_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => T2OUT, OutSignalName => "T2OUT", OutTemp => T_zd, Paths => ( 0 => (InputChangeTime => T2IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_T1IN_T1OUT), PathCondition => (SHDN_ipd = '0') OR (SHDN_ipd = 'L')), 1 => (InputChangeTime => SHDN_ipd'LAST_EVENT, PathDelay => tpd_SHDN_T1OUT, PathCondition => TRUE ) ), GlitchData => T_GlitchData ); END PROCESS; VITALBehaviorT3 : PROCESS(T3IN_ipd, SHDN_ipd) -- Functionality Results Variables VARIABLE T_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE T_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ T_zd := VitalINVIF0 (data => T3IN_ipd, enable => SHDN_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => T3OUT, OutSignalName => "T3OUT", OutTemp => T_zd, Paths => ( 0 => (InputChangeTime => T3IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_T1IN_T1OUT), PathCondition => (SHDN_ipd = '0') OR (SHDN_ipd = 'L')), 1 => (InputChangeTime => SHDN_ipd'LAST_EVENT, PathDelay => tpd_SHDN_T1OUT, PathCondition => TRUE ) ), GlitchData => T_GlitchData ); END PROCESS; VITALBehaviorT4 : PROCESS(T4IN_ipd, SHDN_ipd) -- Functionality Results Variables VARIABLE T_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE T_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ T_zd := VitalINVIF0 (data => T4IN_ipd, enable => SHDN_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => T4OUT, OutSignalName => "T4OUT", OutTemp => T_zd, Paths => ( 0 => (InputChangeTime => T4IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_T1IN_T1OUT), PathCondition => (SHDN_ipd = '0') OR (SHDN_ipd = 'L')), 1 => (InputChangeTime => SHDN_ipd'LAST_EVENT, PathDelay => tpd_SHDN_T1OUT, PathCondition => TRUE ) ), GlitchData => T_GlitchData ); END PROCESS; VITALBehaviorR1 : PROCESS(R1IN_ipd, ENNeg_ipd, SHDN_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'U'; VARIABLE E_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ E_zd := VitalOR2(a=> SHDN_ipd, b => ENNeg_ipd); R_zd := VitalINVIF0 (data => R1IN_ipd, enable => E_zd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => R1OUT, OutSignalName => "R1OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R1IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_R1IN_R1OUT), PathCondition => (E_zd = '0')), 1 => (InputChangeTime => SHDN_ipd'LAST_EVENT, PathDelay => tpd_SHDN_R1OUT, PathCondition => TRUE ), 2 => (InputChangeTime => ENNeg_ipd'LAST_EVENT, PathDelay => tpd_ENNeg_R1OUT, PathCondition => TRUE ) ), GlitchData => R_GlitchData ); END PROCESS; VITALBehaviorR2 : PROCESS(R2IN_ipd, ENNeg_ipd, SHDN_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'U'; VARIABLE E_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ E_zd := VitalOR2(a=> SHDN_ipd, b => ENNeg_ipd); R_zd := VitalINVIF0 (data => R2IN_ipd, enable => E_zd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => R2OUT, OutSignalName => "R2OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R2IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_R1IN_R1OUT), PathCondition => (E_zd = '0')), 1 => (InputChangeTime => SHDN_ipd'LAST_EVENT, PathDelay => tpd_SHDN_R1OUT, PathCondition => TRUE ), 2 => (InputChangeTime => ENNeg_ipd'LAST_EVENT, PathDelay => tpd_ENNeg_R1OUT, PathCondition => TRUE ) ), GlitchData => R_GlitchData ); END PROCESS; VITALBehaviorR3 : PROCESS(R3IN_ipd, ENNeg_ipd, SHDN_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'U'; VARIABLE E_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ E_zd := VitalOR2(a=> SHDN_ipd, b => ENNeg_ipd); R_zd := VitalINVIF0 (data => R3IN_ipd, enable => E_zd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => R3OUT, OutSignalName => "R3OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R3IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_R1IN_R1OUT), PathCondition => (E_zd = '0')), 1 => (InputChangeTime => SHDN_ipd'LAST_EVENT, PathDelay => tpd_SHDN_R1OUT, PathCondition => TRUE ), 2 => (InputChangeTime => ENNeg_ipd'LAST_EVENT, PathDelay => tpd_ENNeg_R1OUT, PathCondition => TRUE ) ), GlitchData => R_GlitchData ); END PROCESS; VITALBehaviorR4 : PROCESS(R4IN_ipd, ENNeg_ipd, SHDN_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'U'; VARIABLE E_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ E_zd := VitalOR2(a=> SHDN_ipd, b => ENNeg_ipd); R_zd := VitalINVIF0 (data => R4IN_ipd, enable => E_zd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => R4OUT, OutSignalName => "R4OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R4IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_R1IN_R1OUT), PathCondition => (E_zd = '0')), 1 => (InputChangeTime => SHDN_ipd'LAST_EVENT, PathDelay => tpd_SHDN_R1OUT, PathCondition => TRUE ), 2 => (InputChangeTime => ENNeg_ipd'LAST_EVENT, PathDelay => tpd_ENNeg_R1OUT, PathCondition => TRUE ) ), GlitchData => R_GlitchData ); END PROCESS; VITALBehaviorR5 : PROCESS(R5IN_ipd, ENNeg_ipd, SHDN_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'U'; VARIABLE E_zd : std_ulogic := 'U'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ E_zd := VitalOR2(a=> SHDN_ipd, b => ENNeg_ipd); R_zd := VitalINVIF0 (data => R5IN_ipd, enable => E_zd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => R5OUT, OutSignalName => "R5OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R5IN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_R1IN_R1OUT), PathCondition => (E_zd = '0')), 1 => (InputChangeTime => SHDN_ipd'LAST_EVENT, PathDelay => tpd_SHDN_R1OUT, PathCondition => TRUE ), 2 => (InputChangeTime => ENNeg_ipd'LAST_EVENT, PathDelay => tpd_ENNeg_R1OUT, PathCondition => TRUE ) ), GlitchData => R_GlitchData ); END PROCESS; END vhdl_behavioral;