-------------------------------------------------------------------------------- -- File Name: if1381.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1999, 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 99 MAR 22 Initial release -- V2.0 R. Munden 02 MAY 23 re-written as flat part -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IF -- Technology: TTL/CMOS -- Part: LT1381 -- -- Description: RS-232 Driver/Receiver -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY if1381 IS GENERIC ( -- tipd delays: interconnect path delays tipd_R1IN : VitalDelayType01 := VitalZeroDelay01; tipd_T1IN : VitalDelayType01 := VitalZeroDelay01; tipd_R2IN : VitalDelayType01 := VitalZeroDelay01; tipd_T2IN : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_R1IN_R1OUT : VitalDelayType01 := UnitDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( R1IN : IN std_ulogic := 'L'; R2IN : IN std_ulogic := 'L'; R1OUT : OUT std_ulogic := 'U'; R2OUT : OUT std_ulogic := 'U'; T1IN : IN std_ulogic := 'U'; T2IN : IN std_ulogic := 'U'; T1OUT : OUT std_ulogic := 'U'; T2OUT : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of if1381 : ENTITY IS TRUE; END if1381; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of if1381 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL R1IN_ipd : std_ulogic := 'U'; SIGNAL T1IN_ipd : std_ulogic := 'U'; SIGNAL R2IN_ipd : std_ulogic := 'U'; SIGNAL T2IN_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (R1IN_ipd, R1IN, tipd_R1IN); w_2 : VitalWireDelay (T1IN_ipd, T1IN, tipd_T1IN); w_3 : VitalWireDelay (R2IN_ipd, R2IN, tipd_R2IN); w_4 : VitalWireDelay (T2IN_ipd, T2IN, tipd_T2IN); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehaviorT1 : PROCESS(T1IN_ipd) -- Functionality Results Variables VARIABLE T_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE T_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ T_zd := VitalINV (data => T1IN_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => T1OUT, OutSignalName => "T1OUT", OutTemp => T_zd, Paths => ( 0 => (InputChangeTime => T1IN_ipd'LAST_EVENT, PathDelay => tpd_R1IN_R1OUT, PathCondition => TRUE)), GlitchData => T_GlitchData ); END PROCESS; VITALBehaviorT2 : PROCESS(T2IN_ipd) -- Functionality Results Variables VARIABLE T_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE T_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ T_zd := VitalINV (data => T2IN_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => T2OUT, OutSignalName => "T2OUT", OutTemp => T_zd, Paths => ( 0 => (InputChangeTime => T2IN_ipd'LAST_EVENT, PathDelay => tpd_R1IN_R1OUT, PathCondition => TRUE)), GlitchData => T_GlitchData ); END PROCESS; VITALBehaviorR1 : PROCESS(R1IN_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ R_zd := VitalINV (data => R1IN_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => R1OUT, OutSignalName => "R1OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R1IN_ipd'LAST_EVENT, PathDelay => tpd_R1IN_R1OUT, PathCondition => TRUE)), GlitchData => R_GlitchData ); END PROCESS; VITALBehaviorR2 : PROCESS(R2IN_ipd) -- Functionality Results Variables VARIABLE R_zd : std_ulogic := 'X'; -- Output Glitch Detection Variables VARIABLE R_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ R_zd := VitalINV (data => R2IN_ipd ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => R2OUT, OutSignalName => "R2OUT", OutTemp => R_zd, Paths => ( 0 => (InputChangeTime => R2IN_ipd'LAST_EVENT, PathDelay => tpd_R1IN_R1OUT, PathCondition => TRUE)), GlitchData => R_GlitchData ); END PROCESS; END vhdl_behavioral;