------------------------------------------------------------------------------- -- File Name: fin1101.vhd ------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 G.Gojanovic 05 Jun 28 Initial release ------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: IF -- Technology: LVDS -- Part: fin1101 -- Description: LVDS Single Port High Speed Repeater ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- SIMULATION RESOLUTION MUST BE 1 ps ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY fin1101 IS GENERIC ( -- tipd delays: interconnect path delays tipd_EN : VitalDelayType01 := VitalZeroDelay01; tipd_RIN : VitalDelayType01 := VitalZeroDelay01; tipd_RINNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delay: propagation from input to output tpd_RIN_DOut : VitalDelayType01Z := UnitDelay01Z; -- tperiod_min - minimum clock period - 1/max freq tperiod_RIN : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( EN : IN std_ulogic := 'U'; RIN : IN std_ulogic := 'U'; RINNeg : IN std_ulogic := 'U'; DOut : OUT std_ulogic := 'U'; DOutNeg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of fin1101 : ENTITY IS TRUE; END fin1101; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of fin1101 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "fin1101"; SIGNAL EN_ipd : std_ulogic := 'U'; SIGNAL RIN_ipd : std_ulogic := 'U'; SIGNAL RINNeg_ipd : std_ulogic := 'U'; BEGIN --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay(EN_ipd,EN,tipd_EN); w_2 : VitalWireDelay(RIN_ipd,RIN,tipd_RIN); w_3 : VitalWireDelay(RINNeg_ipd,RINNeg,tipd_RINNeg); END BLOCK; Behavior : BLOCK PORT ( EN : IN std_ulogic := 'U'; RIN : IN std_ulogic := 'U'; RINNeg : IN std_ulogic := 'U'; DOut : OUT std_ulogic := 'U'; DOutNeg : OUT std_ulogic := 'U' ); PORT MAP ( EN => EN_ipd, RIN => RIN_ipd, RINNeg => RINNeg_ipd, DOut => DOut, DOutNeg => DOutNeg ); SIGNAL Dout_zd : std_ulogic := 'U'; SIGNAL Dout_tmp : std_logic := 'U'; SIGNAL DoutNeg_tmp : std_logic := 'U'; SIGNAL viol : X01 := '0'; SIGNAL RINint : std_ulogic := 'U'; BEGIN --------------------------------------------------------------------------- -- Concurrent procedure calls --------------------------------------------------------------------------- a_1: VitalBUFIF1 (q => DOut_tmp, data => Dout_zd, enable => EN_ipd); a_2: VitalINVIF1 (q => DOutNeg_tmp, data => Dout_zd, enable => EN_ipd); --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck : PROCESS (RIN, RINNeg) VARIABLE Pviol_RIN : X01 := '0'; VARIABLE PD_RIN : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RINNeg : X01 := '0'; VARIABLE PD_RINNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN IF TimingChecksOn THEN -- Setup/Hold Checks Violation := '0'; VitalPeriodPulseCheck ( TestSignal => RIN, TestSignalName => "RIN", Period => tperiod_RIN, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_RIN, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RIN ); VitalPeriodPulseCheck ( TestSignal => RINNeg, TestSignalName => "RINNeg", Period => tperiod_RIN, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_RINNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RINNeg ); Violation := Pviol_RIN OR Pviol_RINNeg; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY Warning; viol <= violation; END IF; END PROCESS VITALTimingCheck; --------------------------------------------------------------------------- -- Diff. Receiver Process --------------------------------------------------------------------------- DiffRec : PROCESS (RIN_ipd, RINNeg_ipd, RINint) -- Functionality Results Variables VARIABLE RINint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 1); -- Glitch Detection Variables VARIABLE RIN_GlitchData : VitalGlitchDataType; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- VitalStateTable ( StateTable => diff_rec_tab, DataIn => (RIN_ipd, RINNeg_ipd), Result => RINint_zd, PreviousDataIn => PrevData ); ----------------------------------------------------------------------- -- (Dummy) Path Delay Section ----------------------------------------------------------------------- VitalPathDelay ( OutSignal => RINint, OutSignalName => "RINint", OutTemp => RINint_zd, GlitchData => RIN_GlitchData, Paths => ( 0 => (InputChangeTime => RIN_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => TRUE)) ); Dout_zd <= RINint; END PROCESS; ------------------------------------------------ -- path delay ------------------------------------------------ D_output: PROCESS(Dout_tmp, DOutNeg_tmp) VARIABLE D_GlitchData : VitalGlitchDataType; VARIABLE DN_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => Dout, OutSignalName => "Dout", OutTemp => Dout_tmp, Mode => VitalTransport, GlitchData => D_GlitchData, Paths => ( 0 => (InputChangeTime => Dout_tmp'LAST_EVENT, PathDelay => tpd_RIN_DOut, PathCondition => DOut_tmp /= 'Z' AND DOut_tmp'LAST_VALUE /= 'Z'), 1 => (InputChangeTime => Dout_tmp'LAST_EVENT, PathDelay => tpd_RIN_DOut, PathCondition => ((DOut_tmp = 'Z' AND DOutNeg_tmp'LAST_VALUE /= 'Z') OR (DOut_tmp'LAST_VALUE = 'Z' AND DOut_tmp /= 'Z')))) ); VitalPathDelay01Z( OutSignal => DoutNeg, OutSignalName => "DoutNEG", OutTemp => DoutNeg_tmp, Mode => VitalTransport, GlitchData => DN_GlitchData, Paths => ( 0 => (InputChangeTime => DoutNeg_tmp'LAST_EVENT, PathDelay => tpd_RIN_DOut, PathCondition => DOutNeg_tmp /= 'Z' AND DOutNeg_tmp'LAST_VALUE /= 'Z'), 1 => (InputChangeTime => DoutNeg_tmp'LAST_EVENT, PathDelay => tpd_RIN_DOut, PathCondition => ((DOutNeg_tmp = 'Z' AND DOutNeg_tmp'LAST_VALUE /= 'Z') OR (DOutNeg_tmp'LAST_VALUE = 'Z' AND DOutNeg_tmp /= 'Z')))) ); END PROCESS D_output; END BLOCK; END vhdl_behavioral;