-------------------------------------------------------------------------------- -- File Name: dvi164.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2003-2008 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 M.Radmanovic 03 Nov 25 Initial release -- V1.1 R. Munden 08 Sep 21 Corrected timing generics -- -- The simulator resolution must be 1 ps. -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: -- Technology: -- Part: DVI164 -- Description: PanelBus Digital Transmitter -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.vital_timing.ALL; USE IEEE.vital_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY dvi164 IS GENERIC ( -- tipd delays: interconnect path delays tipd_VREF : VitalDelayType01 := VitalZeroDelay01; tipd_AVCC0 : VitalDelayType01 := VitalZeroDelay01; tipd_AVCC1 : VitalDelayType01 := VitalZeroDelay01; tipd_AVCC2 : VitalDelayType01 := VitalZeroDelay01; tipd_EXTSWING : VitalDelayType01 := VitalZeroDelay01; tipd_PDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_D18 : VitalDelayType01 := VitalZeroDelay01; tipd_D19 : VitalDelayType01 := VitalZeroDelay01; tipd_D20 : VitalDelayType01 := VitalZeroDelay01; tipd_D21 : VitalDelayType01 := VitalZeroDelay01; tipd_D22 : VitalDelayType01 := VitalZeroDelay01; tipd_D23 : VitalDelayType01 := VitalZeroDelay01; tipd_CTL1 : VitalDelayType01 := VitalZeroDelay01; tipd_CTL2 : VitalDelayType01 := VitalZeroDelay01; tipd_CTL3 : VitalDelayType01 := VitalZeroDelay01; tipd_DE : VitalDelayType01 := VitalZeroDelay01; tipd_HSYNC : VitalDelayType01 := VitalZeroDelay01; tipd_VSYNC : VitalDelayType01 := VitalZeroDelay01; tipd_IDCK : VitalDelayType01 := VitalZeroDelay01; tipd_IDCKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ISEL : VitalDelayType01 := VitalZeroDelay01; tipd_BSEL : VitalDelayType01 := VitalZeroDelay01; tipd_DSEL : VitalDelayType01 := VitalZeroDelay01; tipd_EDGE : VitalDelayType01 := VitalZeroDelay01; tipd_DKEN : VitalDelayType01 := VitalZeroDelay01; -- tsetup values: setup times tsetup_D0_IDCK : VitalDelayType := UnitDelay; tsetup_DE_IDCK : VitalDelayType := UnitDelay; -- thold values: hold times thold_D0_IDCK : VitalDelayType := UnitDelay; thold_DE_IDCK : VitalDelayType := UnitDelay; -- tperiod min (calculated as 1/max freq) tperiod_IDCK : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( TX2 : OUT std_ulogic := 'U'; TX2Neg : OUT std_ulogic := 'U'; TX1 : OUT std_ulogic := 'U'; TX1Neg : OUT std_ulogic := 'U'; TX0 : OUT std_ulogic := 'U'; TX0Neg : OUT std_ulogic := 'U'; TXC : OUT std_ulogic := 'U'; TXCNeg : OUT std_ulogic := 'U'; VREF : INOUT std_ulogic := 'U'; EXTSWING : INOUT std_ulogic := 'U'; AVCC0 : INOUT std_ulogic := 'U'; AVCC1 : INOUT std_ulogic := 'U'; AVCC2 : INOUT std_ulogic := 'U'; PDNeg : IN std_ulogic := 'U'; D0 : IN std_ulogic := 'U'; D1 : IN std_ulogic := 'U'; D2 : IN std_ulogic := 'U'; D3 : IN std_ulogic := 'U'; D4 : IN std_ulogic := 'U'; D5 : IN std_ulogic := 'U'; D6 : IN std_ulogic := 'U'; D7 : IN std_ulogic := 'U'; D8 : IN std_ulogic := 'U'; D9 : IN std_ulogic := 'U'; D10 : IN std_ulogic := 'U'; D11 : IN std_ulogic := 'U'; D12 : IN std_ulogic := 'U'; D13 : IN std_ulogic := 'U'; D14 : IN std_ulogic := 'U'; D15 : IN std_ulogic := 'U'; D16 : IN std_ulogic := 'U'; D17 : IN std_ulogic := 'U'; D18 : IN std_ulogic := 'U'; D19 : IN std_ulogic := 'U'; D20 : IN std_ulogic := 'U'; D21 : IN std_ulogic := 'U'; D22 : IN std_ulogic := 'U'; D23 : IN std_ulogic := 'U'; CTL1 : IN std_ulogic := 'U'; CTL2 : IN std_ulogic := 'U'; CTL3 : IN std_ulogic := 'U'; DE : IN std_ulogic := 'U'; HSYNC : IN std_ulogic := 'U'; MSEN : OUT std_ulogic := 'U'; VSYNC : IN std_ulogic := 'U'; IDCK : IN std_ulogic := 'U'; IDCKNeg : IN std_ulogic := 'U'; ISEL : IN std_ulogic := 'U'; BSEL : IN std_ulogic := 'U'; DSEL : INOUT std_ulogic := 'U'; EDGE : IN std_ulogic := 'U'; DKEN : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of dvi164 : ENTITY IS TRUE; END dvi164; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of dvi164 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "dvi164"; CONSTANT de_skew : TIME := 350 ps; SIGNAL VREF_ipd : std_ulogic := 'U'; SIGNAL EXTSWING_ipd : std_ulogic := 'U'; SIGNAL AVCC0_ipd : std_ulogic := 'U'; SIGNAL AVCC1_ipd : std_ulogic := 'U'; SIGNAL AVCC2_ipd : std_ulogic := 'U'; SIGNAL PDNeg_ipd : std_ulogic := 'U'; SIGNAL D0_ipd : std_ulogic := 'U'; SIGNAL D1_ipd : std_ulogic := 'U'; SIGNAL D2_ipd : std_ulogic := 'U'; SIGNAL D3_ipd : std_ulogic := 'U'; SIGNAL D4_ipd : std_ulogic := 'U'; SIGNAL D5_ipd : std_ulogic := 'U'; SIGNAL D6_ipd : std_ulogic := 'U'; SIGNAL D7_ipd : std_ulogic := 'U'; SIGNAL D8_ipd : std_ulogic := 'U'; SIGNAL D9_ipd : std_ulogic := 'U'; SIGNAL D10_ipd : std_ulogic := 'U'; SIGNAL D11_ipd : std_ulogic := 'U'; SIGNAL D12_ipd : std_ulogic := 'U'; SIGNAL D13_ipd : std_ulogic := 'U'; SIGNAL D14_ipd : std_ulogic := 'U'; SIGNAL D15_ipd : std_ulogic := 'U'; SIGNAL D16_ipd : std_ulogic := 'U'; SIGNAL D17_ipd : std_ulogic := 'U'; SIGNAL D18_ipd : std_ulogic := 'U'; SIGNAL D19_ipd : std_ulogic := 'U'; SIGNAL D20_ipd : std_ulogic := 'U'; SIGNAL D21_ipd : std_ulogic := 'U'; SIGNAL D22_ipd : std_ulogic := 'U'; SIGNAL D23_ipd : std_ulogic := 'U'; SIGNAL CTL1_ipd : std_ulogic := 'U'; SIGNAL CTL2_ipd : std_ulogic := 'U'; SIGNAL CTL3_ipd : std_ulogic := 'U'; SIGNAL DE_ipd : std_ulogic := 'U'; SIGNAL HSYNC_ipd : std_ulogic := 'U'; SIGNAL VSYNC_ipd : std_ulogic := 'U'; SIGNAL IDCK_ipd : std_ulogic := 'U'; SIGNAL IDCKNeg_ipd : std_ulogic := 'U'; SIGNAL ISEL_ipd : std_ulogic := 'U'; SIGNAL BSEL_ipd : std_ulogic := 'U'; SIGNAL DSEL_ipd : std_ulogic := 'U'; SIGNAL EDGE_ipd : std_ulogic := 'U'; SIGNAL DKEN_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_9 : VitalWireDelay (VREF_ipd, VREF, tipd_VREF); w_10 : VitalWireDelay (EXTSWING_ipd, EXTSWING, tipd_EXTSWING); w_11 : VitalWireDelay (AVCC0_ipd, AVCC0, tipd_AVCC0); w_12 : VitalWireDelay (AVCC1_ipd, AVCC1, tipd_AVCC1); w_13 : VitalWireDelay (AVCC2_ipd, AVCC2, tipd_AVCC2); w_15 : VitalWireDelay (PDNeg_ipd, PDNeg, tipd_PDNeg); w_16 : VitalWireDelay (D0_ipd, D0, tipd_D0); w_17 : VitalWireDelay (D1_ipd, D1, tipd_D1); w_18 : VitalWireDelay (D2_ipd, D2, tipd_D2); w_19 : VitalWireDelay (D3_ipd, D3, tipd_D3); w_20 : VitalWireDelay (D4_ipd, D4, tipd_D4); w_21 : VitalWireDelay (D5_ipd, D5, tipd_D5); w_22 : VitalWireDelay (D6_ipd, D6, tipd_D6); w_23 : VitalWireDelay (D7_ipd, D7, tipd_D7); w_24 : VitalWireDelay (D8_ipd, D8, tipd_D8); w_25 : VitalWireDelay (D9_ipd, D9, tipd_D9); w_26 : VitalWireDelay (D10_ipd, D10, tipd_D10); w_27 : VitalWireDelay (D11_ipd, D11, tipd_D11); w_28 : VitalWireDelay (D12_ipd, D12, tipd_D12); w_29 : VitalWireDelay (D13_ipd, D13, tipd_D13); w_30 : VitalWireDelay (D14_ipd, D14, tipd_D14); w_31 : VitalWireDelay (D15_ipd, D15, tipd_D15); w_32 : VitalWireDelay (D16_ipd, D16, tipd_D16); w_33 : VitalWireDelay (D17_ipd, D17, tipd_D17); w_34 : VitalWireDelay (D18_ipd, D18, tipd_D18); w_35 : VitalWireDelay (D19_ipd, D19, tipd_D19); w_36 : VitalWireDelay (D20_ipd, D20, tipd_D20); w_37 : VitalWireDelay (D21_ipd, D21, tipd_D21); w_38 : VitalWireDelay (D22_ipd, D22, tipd_D22); w_39 : VitalWireDelay (D23_ipd, D23, tipd_D23); w_40 : VitalWireDelay (CTL1_ipd, CTL1, tipd_CTL1); w_41 : VitalWireDelay (CTL2_ipd, CTL2, tipd_CTL2); w_42 : VitalWireDelay (CTL3_ipd, CTL3, tipd_CTL3); w_43 : VitalWireDelay (DE_ipd, DE, tipd_DE); w_44 : VitalWireDelay (HSYNC_ipd, HSYNC, tipd_HSYNC); w_46 : VitalWireDelay (VSYNC_ipd, VSYNC, tipd_VSYNC); w_47 : VitalWireDelay (IDCK_ipd, IDCK, tipd_IDCK); w_48 : VitalWireDelay (IDCKNeg_ipd, IDCKNeg, tipd_IDCKNeg); w_49 : VitalWireDelay (ISEL_ipd, ISEL, tipd_ISEL); w_50 : VitalWireDelay (BSEL_ipd, BSEL, tipd_BSEL); w_51 : VitalWireDelay (DSEL_ipd, DSEL, tipd_DSEL); w_52 : VitalWireDelay (EDGE_ipd, EDGE, tipd_EDGE); w_53 : VitalWireDelay (DKEN_ipd, DKEN, tipd_DKEN); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( TX2 : OUT std_ulogic := 'U'; TX2Neg : OUT std_ulogic := 'U'; TX1 : OUT std_ulogic := 'U'; TX1Neg : OUT std_ulogic := 'U'; TX0 : OUT std_ulogic := 'U'; TX0Neg : OUT std_ulogic := 'U'; TXC : OUT std_ulogic := 'U'; TXCNeg : OUT std_ulogic := 'U'; VREFIn : IN std_ulogic := 'U'; VREFOut : OUT std_ulogic := 'U'; EXTSWING : OUT std_ulogic := 'U'; AVCC0In : IN std_ulogic := 'U'; AVCC0Out : OUT std_ulogic := 'U'; AVCC1In : IN std_ulogic := 'U'; AVCC1Out : OUT std_ulogic := 'U'; AVCC2In : IN std_ulogic := 'U'; AVCC2Out : OUT std_ulogic := 'U'; PDNeg : IN std_ulogic := 'U'; DIn : IN std_logic_vector(23 downto 0) := (others => 'Z'); CTL1 : IN std_ulogic := 'U'; CTL2 : IN std_ulogic := 'U'; CTL3 : IN std_ulogic := 'U'; DE : IN std_ulogic := 'U'; HSYNC : IN std_ulogic := 'U'; MSEN : OUT std_ulogic := 'U'; VSYNC : IN std_ulogic := 'U'; IDCK : IN std_ulogic := 'U'; IDCKNeg : IN std_ulogic := 'U'; ISEL : IN std_ulogic := 'U'; BSEL : IN std_ulogic := 'U'; DSEL : IN std_ulogic := 'U'; DSELOut : OUT std_ulogic := 'U'; EDGE : IN std_ulogic := 'U'; DKEN : IN std_ulogic := 'U' ); PORT MAP ( TX2 => TX2, TX2Neg => TX2Neg, TX1 => TX1, TX1Neg => TX1Neg, TX0 => TX0, TX0Neg => TX0Neg, TXC => TXC, TXCNeg => TXCNeg, VREFIn => VREF_ipd, VREFOut => VREF, EXTSWING => EXTSWING, AVCC0In => AVCC0_ipd, AVCC0Out => AVCC0, AVCC1In => AVCC1_ipd, AVCC1Out => AVCC1, AVCC2In => AVCC2_ipd, AVCC2Out => AVCC2, PDNeg => PDNeg_ipd, DIn(0) => D0_ipd, DIn(1) => D1_ipd, DIn(2) => D2_ipd, DIn(3) => D3_ipd, DIn(4) => D4_ipd, DIn(5) => D5_ipd, DIn(6) => D6_ipd, DIn(7) => D7_ipd, DIn(8) => D8_ipd, DIn(9) => D9_ipd, DIn(10) => D10_ipd, DIn(11) => D11_ipd, DIn(12) => D12_ipd, DIn(13) => D13_ipd, DIn(14) => D14_ipd, DIn(15) => D15_ipd, DIn(16) => D16_ipd, DIn(17) => D17_ipd, DIn(18) => D18_ipd, DIn(19) => D19_ipd, DIn(20) => D20_ipd, DIn(21) => D21_ipd, DIn(22) => D22_ipd, DIn(23) => D23_ipd, CTL1 => CTL1_ipd, CTL2 => CTL2_ipd, CTL3 => CTL3_ipd, DE => DE_ipd, HSYNC => HSYNC_ipd, MSEN => MSEN, VSYNC => VSYNC_ipd, IDCK => IDCK_ipd, IDCKNeg => IDCKNeg_ipd, ISEL => ISEL_ipd, BSEL => BSEL_ipd, DSEL => DSEL_ipd, DSELOut => DSEL, EDGE => EDGE_ipd, DKEN => DKEN_ipd ); SUBTYPE RegType IS std_logic_vector(7 downto 0); SUBTYPE RegType2 IS std_logic_vector(15 downto 0); SIGNAL Start : std_ulogic := 'U'; SIGNAL DATA_BLUE : std_logic_vector(7 downto 0); SIGNAL DATA_RED : std_logic_vector(7 downto 0); SIGNAL DATA_GREEN : std_logic_vector(7 downto 0); SIGNAL D_VSYNC : std_logic; SIGNAL D_HSYNC : std_logic; SIGNAL D_CTL1 : std_logic; SIGNAL D_CTL2 : std_logic; SIGNAL D_CTL3 : std_logic; SIGNAL q_blue : std_logic_vector(9 downto 0); SIGNAL q_red : std_logic_vector(9 downto 0); SIGNAL q_green : std_logic_vector(9 downto 0); SIGNAL change_red : std_logic := '0'; SIGNAL change_blue : std_logic := '0'; SIGNAL change_green : std_logic := '0'; SIGNAL tCD : time; SIGNAL PERIOD : time := 2 ns; SIGNAL clk : std_ulogic := '1'; SIGNAL DE_int : std_ulogic := '0'; -- registers map SIGNAL VEN_ID : RegType2 := "0000000101001101";-- 014C; Read only SIGNAL DEV_ID : RegType2 := "0000010000010000";--Read only SIGNAL REV_ID : RegType := "00000000";--0410;Read only SIGNAL RES_1 : RegType := "01100100";--Read only SIGNAL RES_2 : RegType2 := "0000000000010100";--Read only SIGNAL CTL_1_MODE : RegType := "11111110";--Read/Write SIGNAL CTL_2_MODE : RegType := "00000000";--Read/Write SIGNAL CTL_3_MODE : RegType := "10000000";--Read/Write SIGNAL CFG : RegType := "00001011";--Read only SIGNAL RES_3 : RegType := "10010111";--Read/Write SIGNAL RES_4 : RegType := "11010000";--Read/Write SIGNAL RES_5 : RegType := "10101001";--Read/Write SIGNAL DE_DLY : RegType := "00000000";--Read/Write SIGNAL DE_CTL : RegType := "00000000";--Read/Write SIGNAL DE_TOP : RegType := "00000000";--Read/Write SIGNAL DE_CNT : RegType2 := "0000000000000000";--Read/Write SIGNAL DE_LIN : RegType2 := "0000000000000000";--Read/Write SIGNAL H_RES : RegType2 := "0000000000000000";--Read Only SIGNAL V_RES : RegType2 := "0000000000000000";--Read Only ALIAS PD_BIT : std_logic IS CTL_1_MODE(0); ALIAS EDGE_BIT : std_logic IS CTL_1_MODE(1); ALIAS BSEL_BIT : std_logic IS CTL_1_MODE(2); ALIAS DSEL_BIT : std_logic IS CTL_1_MODE(3); ALIAS HEN_BIT : std_logic IS CTL_1_MODE(4); ALIAS VEN_BIT : std_logic IS CTL_1_MODE(5); ALIAS TDIS_BIT : std_logic IS CTL_1_MODE(6); ALIAS MDI_BIT : std_logic IS CTL_2_MODE(0); ALIAS HTPLG_BIT : std_logic IS CTL_2_MODE(1); ALIAS RSEN_BIT : std_logic IS CTL_2_MODE(2); ALIAS TSEL_BIT : std_logic IS CTL_2_MODE(3); ALIAS MSEL_BIT : std_logic_vector(2 downto 0) IS CTL_2_MODE(6 downto 4); ALIAS VLOW_BIT : std_logic IS CTL_2_MODE(7); ALIAS CTL_BIT : std_logic_vector(2 downto 0) IS CTL_3_MODE(3 downto 1); ALIAS DKEN_BIT : std_logic IS CTL_3_MODE(4); ALIAS DK_BIT : std_logic_vector(2 downto 0) IS CTL_3_MODE(7 downto 5); ALIAS HS_POL : std_logic IS DE_CTL(4); ALIAS VS_POL : std_logic IS DE_CTL(5); ALIAS DE_GEN : std_logic IS DE_CTL(6); BEGIN HTPLG_BIT <= EDGE; CFG <= DIn(23 downto 16); TXC <= IDCK; TXCNeg <= IDCKNeg; CLOCKTIME: PROCESS(IDCK) VARIABLE Previous : Time := 0 ns; VARIABLE TmpPer : Time := 0 ns; BEGIN IF rising_edge(IDCK) THEN TmpPer := NOW - Previous; IF TmpPer > 0 ns THEN PERIOD <= TmpPer/20; END IF; Previous := NOW; END IF; END PROCESS; PLL : PROCESS BEGIN WAIT FOR PERIOD; clk <= not(clk); END PROCESS PLL; MONITOR : PROCESS(ISEL, MSEL_BIT, RSEN_BIT, MDI_BIT, HTPLG_BIT) BEGIN IF ISEL = '1' THEN CASE MSEL_BIT IS WHEN "000" => MSEN <= '1'; WHEN "001" => MSEN <= MDI_BIT; WHEN "010" => MSEN <= RSEN_BIT; WHEN "011" => MSEN <= HTPLG_BIT; WHEN others => null; END CASE; ELSE MSEN <= RSEN_BIT; END IF; END PROCESS; ------------------------------------------------------------------------ -- Behavior Process ------------------------------------------------------------------------ I2CSlave : PROCESS (ISEL, BSEL, DSEL) VARIABLE ShiftReg : std_logic_vector(7 downto 0); VARIABLE Sub_Address : std_logic_vector(7 downto 0) := (others => '0'); VARIABLE TempReg : std_logic_vector(7 downto 0); VARIABLE ShiftReg1 : std_logic_vector(8 downto 0); VARIABLE AddressReg : std_logic_vector(6 downto 0); VARIABLE counter : NATURAL RANGE 0 TO 8; VARIABLE Addreceived : BOOLEAN := false; VARIABLE SubAddress : BOOLEAN := false; VARIABLE SlaveID : BOOLEAN := false; VARIABLE ackslave : BOOLEAN := false; VARIABLE data : std_logic := '0'; VARIABLE RW : std_logic; BEGIN IF ISEL = '1' AND BSEL = '1' THEN IF falling_edge(DSEL) THEN Start <= '1'; counter := 0; Addreceived := false; ackslave := false; data := '0'; SlaveID := false; SubAddress := false; ELSIF rising_edge(DSEL) THEN Start <= '0'; END IF; END IF; IF rising_edge(BSEL) AND Start = '1' AND ISEL = '1' THEN IF Addreceived = false THEN IF counter < 7 THEN AddressReg(6 - counter) := DSEL; counter := counter + 1; ELSIF counter = 7 THEN RW := DSEL; counter := counter + 1; IF (AddressReg = "0111" & CTL3 & CTL2 & CTL1) THEN SlaveID := true; END IF; ELSIF counter = 8 THEN counter := 0; Addreceived := true; IF RW = '1' THEN CASE Sub_Address IS WHEN "00000000" => ShiftReg := VEN_ID(7 downto 0); WHEN "00000001" => ShiftReg := VEN_ID(15 downto 8); WHEN "00000010" => ShiftReg := DEV_ID(7 downto 0); WHEN "00000011" => ShiftReg := DEV_ID(15 downto 8); WHEN "00000100" => ShiftReg := REV_ID; WHEN "00000101" => ShiftReg := RES_1; WHEN "00000110" => ShiftReg := RES_2(7 downto 0); WHEN "00000111" => ShiftReg := RES_2(15 downto 8); WHEN "00001000" => ShiftReg := CTL_1_MODE; WHEN "00001001" => ShiftReg := CTL_2_MODE; WHEN "00001010" => ShiftReg := CTL_3_MODE; WHEN "00001011" => ShiftReg := CFG; WHEN "00001100" => ShiftReg := RES_3; WHEN "00001101" => ShiftReg := RES_4; WHEN "00001110" => ShiftReg := RES_5; WHEN "00110010" => ShiftReg := DE_DLY; WHEN "00110011" => ShiftReg := DE_CTL; WHEN "00110100" => ShiftReg := DE_TOP; WHEN "00110110" => ShiftReg := DE_CNT(7 downto 0); WHEN "00110111" => ShiftReg := DE_CNT(15 downto 8); WHEN "00111000" => ShiftReg := DE_LIN(7 downto 0); WHEN "00111001" => ShiftReg := DE_LIN(15 downto 8); WHEN "00111010" => ShiftReg := H_RES(7 downto 0); WHEN "00111011" => ShiftReg := H_RES(15 downto 8); WHEN "00111100" => ShiftReg := V_RES(7 downto 0); WHEN "00111101" => ShiftReg := V_RES(15 downto 8); WHEN others => ShiftReg := (others => 'X'); END CASE; ShiftReg1 := ShiftReg & '1'; Sub_Address := to_slv(to_nat(Sub_Address)+1, 8); END IF; END IF; ELSIF RW = '1' AND counter < 8 AND SlaveID = true THEN counter := counter + 1; ELSIF RW = '0' AND counter < 8 AND SlaveID = true THEN ShiftReg(counter) := DSEL; counter := counter + 1; ELSIF counter = 8 AND SlaveID = true THEN data := '0'; counter := 0; IF SubAddress = false AND RW = '0' THEN SubAddress := true; FOR I IN 7 DOWNTO 0 LOOP Sub_Address(i) := ShiftReg(7 - i); END LOOP; ELSIF RW = '0' THEN FOR I IN 7 DOWNTO 0 LOOP TempReg(i) := ShiftReg(7 - i); END LOOP; CASE Sub_Address IS WHEN "00001000" => CTL_1_MODE <= TempReg; WHEN "00001001" => MDI_BIT <= TempReg(0); TSEL_BIT <= TempReg(3); MSEL_BIT <= TempReg(6 downto 4); WHEN "00001010" => CTL_3_MODE <= TempReg; WHEN "00001100" => RES_3 <= TempReg; WHEN "00001101" => RES_4 <= TempReg; WHEN "00001110" => RES_5 <= TempReg; WHEN "00110010" => DE_DLY <= TempReg; WHEN "00110011" => DE_CTL <= TempReg; WHEN "00110100" => DE_TOP<= TempReg; WHEN "00110110" => DE_CNT(7 downto 0) <= TempReg; WHEN "00110111" => DE_CNT(15 downto 8) <= TempReg; WHEN "00111000" => DE_LIN(7 downto 0) <= TempReg; WHEN "00111001" => DE_LIN(15 downto 8) <= TempReg; WHEN others => null; END CASE; Sub_Address := to_slv(to_nat(Sub_Address)+1, 8); END IF; IF RW = '1' THEN CASE Sub_Address IS WHEN "00000001" => ShiftReg := VEN_ID(15 downto 8); WHEN "00000010" => ShiftReg := DEV_ID(7 downto 0); WHEN "00000011" => ShiftReg := DEV_ID(15 downto 8); WHEN "00000100" => ShiftReg := REV_ID; WHEN "00000101" => ShiftReg := RES_1; WHEN "00000110" => ShiftReg := RES_2(7 downto 0); WHEN "00000111" => ShiftReg := RES_2(15 downto 8); WHEN "00001000" => ShiftReg := CTL_1_MODE; WHEN "00001001" => ShiftReg := CTL_2_MODE; WHEN "00001010" => ShiftReg := CTL_3_MODE; WHEN "00001011" => ShiftReg := CFG; WHEN "00001100" => ShiftReg := RES_3; WHEN "00001101" => ShiftReg := RES_4; WHEN "00001110" => ShiftReg := RES_5; WHEN "00110010" => ShiftReg := DE_DLY; WHEN "00110011" => ShiftReg := DE_CTL; WHEN "00110100" => ShiftReg := DE_TOP; WHEN "00110110" => ShiftReg := DE_CNT(7 downto 0); WHEN "00110111" => ShiftReg := DE_CNT(15 downto 8); WHEN "00111000" => ShiftReg := DE_LIN(7 downto 0); WHEN "00111001" => ShiftReg := DE_LIN(15 downto 8); WHEN "00111010" => ShiftReg := H_RES(7 downto 0); WHEN "00111011" => ShiftReg := H_RES(15 downto 8); WHEN "00111100" => ShiftReg := V_RES(7 downto 0); WHEN "00111101" => ShiftReg := V_RES(15 downto 8); WHEN others => ShiftReg := (others => 'X'); END CASE; ShiftReg1 := ShiftReg & '1'; Sub_Address := to_slv(to_nat(Sub_Address)+1, 8); END IF; END IF; ELSIF falling_edge(BSEL) AND Start = '1' AND SlaveID = true AND ISEL = '1' THEN IF RW = '0' THEN IF counter = 8 THEN ackslave := true; ELSIF counter = 0 THEN ackslave := false; END IF; ELSE IF counter = 8 AND Addreceived = false AND ISEL = '1' THEN ackslave := true; ELSIF counter = 0 THEN ackslave := false; END IF; IF counter < 8 THEN data := '1'; ELSE data := '0'; END IF; END IF; END IF; IF ISEL = '1' THEN IF Start = '1' AND SlaveID = true THEN IF ackslave = true THEN DSELOut <= '0'; ELSIF data = '1' AND falling_edge(BSEL) THEN DSELOut <= 'Z', ShiftReg1(8 - counter) AFTER 1 us; ELSIF data = '0' THEN DSELOut <= 'Z'; END IF; ELSE DSELOut <= 'Z'; END IF; END IF; IF rising_edge(ISEL) THEN Start <= '0'; counter := 0; Addreceived := false; ackslave := false; data := '0'; SlaveID := false; VEN_ID <= "0000000101001101"; DEV_ID <= "0000010000010000"; REV_ID <= "00000000"; RES_1 <= "01100100"; RES_2 <= "0000000000010100"; CTL_1_MODE <= "11111110"; MDI_BIT <= '0'; RSEN_BIT <= '0'; TSEL_BIT <= '0'; MSEL_BIT <= "000"; VLOW_BIT <= '0'; CTL_3_MODE <= "10000000"; RES_3 <= "10010111"; RES_4 <= "11010000"; RES_5 <= "10101001"; DE_DLY <= "00000000"; DE_CTL <= "00000000"; DE_TOP <= "00000000"; DE_CNT <= "0000000000000000"; DE_LIN <= "0000000000000000"; H_RES <= "0000000000000000"; V_RES <= "0000000000000000"; END IF; END PROCESS; BLUEENCODER : PROCESS(change_blue) VARIABLE q_m : std_logic_vector(9 downto 0) := (others => '0'); VARIABLE q_out : std_logic_vector(9 downto 0); VARIABLE N1 : NATURAL := 0; VARIABLE N0 : NATURAL := 0; VARIABLE disparity : INTEGER := 0; VARIABLE vsynch : std_logic; VARIABLE hsynch : std_logic; VARIABLE selection : std_logic_vector(1 downto 0); BEGIN N1 := 0; FOR I IN 0 TO 7 LOOP IF DATA_BLUE(i) = '1' THEN N1 := N1 + 1; END IF; END LOOP; IF (N1 > 4 OR ( N1 = 4 AND DATA_BLUE(0) = '0')) THEN q_m(0) := DATA_BLUE(0); q_m(1) := q_m(0) XOR DATA_BLUE(1); q_m(2) := q_m(1) XOR DATA_BLUE(2); q_m(3) := q_m(2) XOR DATA_BLUE(3); q_m(4) := q_m(3) XOR DATA_BLUE(4); q_m(5) := q_m(4) XOR DATA_BLUE(5); q_m(6) := q_m(5) XOR DATA_BLUE(6); q_m(7) := q_m(6) XOR DATA_BLUE(7); q_m(8) := '1'; ELSE q_m(0) := DATA_BLUE(0); q_m(1) := q_m(0) XNOR DATA_BLUE(1); q_m(2) := q_m(1) XNOR DATA_BLUE(2); q_m(3) := q_m(2) XNOR DATA_BLUE(3); q_m(4) := q_m(3) XNOR DATA_BLUE(4); q_m(5) := q_m(4) XNOR DATA_BLUE(5); q_m(6) := q_m(5) XNOR DATA_BLUE(6); q_m(7) := q_m(6) XNOR DATA_BLUE(7); q_m(8) := '0'; END IF; IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN N1 := 0; N0 := 0; FOR I IN 0 TO 7 LOOP IF q_m(i) = '1' THEN N1 := N1 + 1; ELSIF q_m(i) = '0' THEN N0 := N0 + 1; END IF; END LOOP; IF (disparity = 0 OR N1 = N0) THEN q_out(9) := not(q_m(8)); q_out(8) := q_m(8); IF q_out(8) = '1' THEN q_out(7 downto 0) := q_m(7 downto 0); ELSE q_out(7 downto 0) := not(q_m(7 downto 0)); END IF; IF q_m(8) = '0' THEN disparity := disparity + (N0 - N1); ELSE disparity := disparity + (N1 - N0); END IF; ELSE IF (disparity > 0 AND N1 > N0) OR (disparity < 0 AND N0 > N1) THEN q_out(9) := '1'; q_out(8) := q_m(8); q_out(7 downto 0) := not(q_m(7 downto 0)); disparity := disparity + 2 * to_nat(q_m(8)) + (N0 - N1); ELSE q_out(9) := '0'; q_out(8) := q_m(8); q_out(7 downto 0) := q_m(7 downto 0); disparity := disparity + 2 * to_nat(not(q_m(8))) + (N0 - N1); END IF; END IF; ELSE disparity := 0; IF VEN_BIT = '0' THEN vsynch := '0'; ELSE vsynch := D_VSYNC; END IF; IF HEN_BIT = '0' THEN hsynch := '0'; ELSE hsynch := D_HSYNC; END IF; selection := vsynch & hsynch; CASE selection IS WHEN "00" => q_out := "0010101011"; WHEN "01" => q_out := "1101010100"; WHEN "10" => q_out := "0010101010"; WHEN "11" => q_out := "1101010101"; WHEN others => null; END CASE; END IF; q_blue <= q_out; END PROCESS; REDENCODER : PROCESS(change_red) VARIABLE q_m : std_logic_vector(9 downto 0) := (others => '0'); VARIABLE q_out : std_logic_vector(9 downto 0); VARIABLE N1 : NATURAL := 0; VARIABLE N0 : NATURAL := 0; VARIABLE disparity : INTEGER := 0; VARIABLE selection : std_logic_vector(1 downto 0); BEGIN N1 := 0; FOR I IN 0 TO 7 LOOP IF DATA_RED(i) = '1' THEN N1 := N1 + 1; END IF; END LOOP; IF (N1 > 4 OR ( N1 = 4 AND DATA_RED(0) = '0')) THEN q_m(0) := DATA_RED(0); q_m(1) := q_m(0) XOR DATA_RED(1); q_m(2) := q_m(1) XOR DATA_RED(2); q_m(3) := q_m(2) XOR DATA_RED(3); q_m(4) := q_m(3) XOR DATA_RED(4); q_m(5) := q_m(4) XOR DATA_RED(5); q_m(6) := q_m(5) XOR DATA_RED(6); q_m(7) := q_m(6) XOR DATA_RED(7); q_m(8) := '1'; ELSE q_m(0) := DATA_RED(0); q_m(1) := q_m(0) XNOR DATA_RED(1); q_m(2) := q_m(1) XNOR DATA_RED(2); q_m(3) := q_m(2) XNOR DATA_RED(3); q_m(4) := q_m(3) XNOR DATA_RED(4); q_m(5) := q_m(4) XNOR DATA_RED(5); q_m(6) := q_m(5) XNOR DATA_RED(6); q_m(7) := q_m(6) XNOR DATA_RED(7); q_m(8) := '0'; END IF; IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN N1 := 0; N0 := 0; FOR I IN 0 TO 7 LOOP IF q_m(i) = '1' THEN N1 := N1 + 1; ELSIF q_m(i) = '0' THEN N0 := N0 + 1; END IF; END LOOP; IF (disparity = 0 OR N1 = N0) THEN q_out(9) := not(q_m(8)); q_out(8) := q_m(8); IF q_out(8) = '1' THEN q_out(7 downto 0) := q_m(7 downto 0); ELSE q_out(7 downto 0) := not(q_m(7 downto 0)); END IF; IF q_m(8) = '0' THEN disparity := disparity + (N0 - N1); ELSE disparity := disparity + (N1 - N0); END IF; ELSE IF (disparity > 0 AND N1 > N0) OR (disparity < 0 AND N0 > N1) THEN q_out(9) := '1'; q_out(8) := q_m(8); q_out(7 downto 0) := not(q_m(7 downto 0)); disparity := disparity + 2 * to_nat(q_m(8)) + (N0 - N1); ELSE q_out(9) := '0'; q_out(8) := q_m(8); q_out(7 downto 0) := q_m(7 downto 0); disparity := disparity + 2 * to_nat(not(q_m(8))) + (N0 - N1); END IF; END IF; ELSE disparity := 0; IF ISEL = '0' THEN selection := D_CTL2 & D_CTL3; ELSE selection := CTL_BIT(1) & CTL_BIT(2); END IF; CASE selection IS WHEN "00" => q_out := "0010101011"; WHEN "01" => q_out := "1101010100"; WHEN "10" => q_out := "0010101010"; WHEN "11" => q_out := "1101010101"; WHEN others => null; END CASE; END IF; q_red <= q_out; END PROCESS; GREENENCODER : PROCESS( change_green) VARIABLE q_m : std_logic_vector(9 downto 0) := (others => '0'); VARIABLE q_out : std_logic_vector(9 downto 0); VARIABLE N1 : NATURAL := 0; VARIABLE N0 : NATURAL := 0; VARIABLE disparity : INTEGER := 0; VARIABLE selection : std_logic_vector(1 downto 0); BEGIN N1 := 0; FOR I IN 0 TO 7 LOOP IF DATA_GREEN(i) = '1' THEN N1 := N1 + 1; END IF; END LOOP; IF (N1 > 4 OR ( N1 = 4 AND DATA_GREEN(0) = '0')) THEN q_m(0) := DATA_GREEN(0); q_m(1) := q_m(0) XOR DATA_GREEN(1); q_m(2) := q_m(1) XOR DATA_GREEN(2); q_m(3) := q_m(2) XOR DATA_GREEN(3); q_m(4) := q_m(3) XOR DATA_GREEN(4); q_m(5) := q_m(4) XOR DATA_GREEN(5); q_m(6) := q_m(5) XOR DATA_GREEN(6); q_m(7) := q_m(6) XOR DATA_GREEN(7); q_m(8) := '1'; ELSE q_m(0) := DATA_GREEN(0); q_m(1) := q_m(0) XNOR DATA_GREEN(1); q_m(2) := q_m(1) XNOR DATA_GREEN(2); q_m(3) := q_m(2) XNOR DATA_GREEN(3); q_m(4) := q_m(3) XNOR DATA_GREEN(4); q_m(5) := q_m(4) XNOR DATA_GREEN(5); q_m(6) := q_m(5) XNOR DATA_GREEN(6); q_m(7) := q_m(6) XNOR DATA_GREEN(7); q_m(8) := '0'; END IF; IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN N1 := 0; N0 := 0; FOR I IN 0 TO 7 LOOP IF q_m(i) = '1' THEN N1 := N1 + 1; ELSIF q_m(i) = '0' THEN N0 := N0 + 1; END IF; END LOOP; IF (disparity = 0 OR N1 = N0) THEN q_out(9) := not(q_m(8)); q_out(8) := q_m(8); IF q_out(8) = '1' THEN q_out(7 downto 0) := q_m(7 downto 0); ELSE q_out(7 downto 0) := not(q_m(7 downto 0)); END IF; IF q_m(8) = '0' THEN disparity := disparity + (N0 - N1); ELSE disparity := disparity + (N1 - N0); END IF; ELSE IF (disparity > 0 AND N1 > N0) OR (disparity < 0 AND N0 > N1) THEN q_out(9) := '1'; q_out(8) := q_m(8); q_out(7 downto 0) := not(q_m(7 downto 0)); disparity := disparity + 2 * to_nat(q_m(8)) + (N0 - N1); ELSE q_out(9) := '0'; q_out(8) := q_m(8); q_out(7 downto 0) := q_m(7 downto 0); disparity := disparity + 2 * to_nat(not(q_m(8))) + (N0 - N1); END IF; END IF; ELSE disparity := 0; IF ISEL = '0' THEN selection := D_CTL1 & '0'; ELSE selection := CTL_BIT(0) & '0'; END IF; CASE selection IS WHEN "00" => q_out := "0010101011"; WHEN "10" => q_out := "0010101010"; WHEN others => null; END CASE; END IF; q_green <= q_out; END PROCESS; TDMS : PROCESS(clk, q_blue, q_red, q_green) VARIABLE Temp_blue : std_logic_vector(9 downto 0); VARIABLE Temp_red : std_logic_vector(9 downto 0); VARIABLE Temp_green : std_logic_vector(9 downto 0); VARIABLE shift : std_logic; BEGIN IF q_blue'EVENT THEN Temp_blue := q_blue; END IF; IF q_red'EVENT THEN Temp_red := q_red; END IF; IF q_green'EVENT THEN Temp_green := q_green; END IF; IF (ISEL = '0' AND PDNeg = '1') OR (ISEL = '1' AND PD_BIT = '1' AND TDIS_BIT = '0') THEN IF falling_edge(clk) THEN TX0 <= Temp_blue(0); TX0Neg <= not(Temp_blue(0)); TX1 <= Temp_green(0); TX1Neg <= not(Temp_green(0)); TX2 <= Temp_red(0); TX2Neg <= not(Temp_red(0)); shift := Temp_blue(0); Temp_blue(8 downto 0) := Temp_blue(9 downto 1); Temp_blue(9) := shift; shift := Temp_red(0); Temp_red(8 downto 0) := Temp_red(9 downto 1); Temp_red(9) := shift; shift := Temp_green(0); Temp_green(8 downto 0) := Temp_green(9 downto 1); Temp_green(9) := shift; END IF; END IF; END PROCESS; DESKEW : PROCESS(ISEL, DKEN, CTL1, CTL2, CTL3, DKEN_BIT, DK_BIT) BEGIN IF ISEL = '0' THEN -- I2C disabled IF DKEN = '1' THEN -- de-skew enabled tCD <= (to_nat(CTL1 & CTL2 & CTL3) - 4) * de_skew; ELSE tCD <= 0 ns; END IF; ELSE -- I2C enabled IF DKEN_BIT = '1' THEN --de-skew enabled tCD <= (to_nat(DK_BIT) - 4) * de_skew; ELSE tCD <= 0 ns; END IF; END IF; END PROCESS; PIXELBUS : PROCESS(IDCK, IDCKNeg, DIn, DE, VSYNC, HSYNC, tCD) -- Timing Check Variables VARIABLE Tviol_D0_IDCKfall : X01 := '0'; VARIABLE TD_D0_IDCKfall : VitalTimingDataType; VARIABLE Tviol_DE_IDCKfall : X01 := '0'; VARIABLE TD_DE_IDCKfall : VitalTimingDataType; VARIABLE Tviol_VSYNC_IDCKfall : X01 := '0'; VARIABLE TD_VSYNC_IDCKfall : VitalTimingDataType; VARIABLE Tviol_HSYNC_IDCKfall : X01 := '0'; VARIABLE TD_HSYNC_IDCKfall : VitalTimingDataType; VARIABLE Tviol_D0_IDCKrise : X01 := '0'; VARIABLE TD_D0_IDCKrise : VitalTimingDataType; VARIABLE Tviol_DE_IDCKrise : X01 := '0'; VARIABLE TD_DE_IDCKrise : VitalTimingDataType; VARIABLE Tviol_VSYNC_IDCKrise : X01 := '0'; VARIABLE TD_VSYNC_IDCKrise : VitalTimingDataType; VARIABLE Tviol_HSYNC_IDCKrise : X01 := '0'; VARIABLE TD_HSYNC_IDCKrise : VitalTimingDataType; VARIABLE Tviol_D0_IDCKfalld : X01 := '0'; VARIABLE TD_D0_IDCKfalld : VitalTimingDataType; VARIABLE Tviol_DE_IDCKfalld : X01 := '0'; VARIABLE TD_DE_IDCKfalld : VitalTimingDataType; VARIABLE Tviol_VSYNC_IDCKfalld : X01 := '0'; VARIABLE TD_VSYNC_IDCKfalld : VitalTimingDataType; VARIABLE Tviol_HSYNC_IDCKfalld : X01 := '0'; VARIABLE TD_HSYNC_IDCKfalld : VitalTimingDataType; VARIABLE Tviol_D0_IDCKrised : X01 := '0'; VARIABLE TD_D0_IDCKrised : VitalTimingDataType; VARIABLE Tviol_DE_IDCKrised : X01 := '0'; VARIABLE TD_DE_IDCKrised : VitalTimingDataType; VARIABLE Tviol_VSYNC_IDCKrised : X01 := '0'; VARIABLE TD_VSYNC_IDCKrised : VitalTimingDataType; VARIABLE Tviol_HSYNC_IDCKrised : X01 := '0'; VARIABLE TD_HSYNC_IDCKrised : VitalTimingDataType; VARIABLE Pviol_IDCK : X01 := '0'; VARIABLE PD_IDCK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "DIn", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_D0_IDCK + tCD, SetupLow => tsetup_D0_IDCK + tCD, HoldHigh => thold_D0_IDCK + tCD, HoldLow => thold_D0_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '1' AND DSEL = '0' AND DKEN = '0' AND EDGE = '0') OR (ISEL = '1' AND BSEL_BIT = '1' AND DSEL_BIT = '0' AND DKEN_BIT = '0' AND EDGE_BIT = '0')), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_D0_IDCKfall, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_IDCKfall ); VitalSetupHoldCheck ( TestSignal => DE, TestSignalName => "DE", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_D0_IDCK + tCD, SetupLow => tsetup_D0_IDCK + tCD, HoldHigh => thold_D0_IDCK + tCD, HoldLow => thold_D0_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '1' AND DSEL = '0' AND DKEN = '0' AND EDGE = '0') OR (ISEL = '1' AND BSEL_BIT = '1' AND DSEL_BIT = '0' AND DKEN_BIT = '0' AND EDGE_BIT = '0')), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_IDCKfall, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_IDCKfall ); VitalSetupHoldCheck ( TestSignal => VSYNC, TestSignalName => "VSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_D0_IDCK + tCD, SetupLow => tsetup_D0_IDCK + tCD, HoldHigh => thold_D0_IDCK + tCD, HoldLow => thold_D0_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '1' AND DSEL = '0' AND DKEN = '0' AND EDGE = '0') OR (ISEL = '1' AND BSEL_BIT = '1' AND DSEL_BIT = '0' AND DKEN_BIT = '0' AND EDGE_BIT = '0')), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_VSYNC_IDCKfall, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_VSYNC_IDCKfall ); VitalSetupHoldCheck ( TestSignal => HSYNC, TestSignalName => "HSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_D0_IDCK + tCD, SetupLow => tsetup_D0_IDCK + tCD, HoldHigh => thold_D0_IDCK + tCD, HoldLow => thold_D0_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '1' AND DSEL = '0' AND DKEN = '0' AND EDGE = '0') OR (ISEL = '1' AND BSEL_BIT = '1' AND DSEL_BIT = '0' AND DKEN_BIT = '0' AND EDGE_BIT = '0')), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_HSYNC_IDCKfall, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSYNC_IDCKfall ); VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "DIn", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_D0_IDCK + tCD, SetupLow => tsetup_D0_IDCK + tCD, HoldHigh => thold_D0_IDCK + tCD, HoldLow => thold_D0_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '1' AND DSEL = '0' AND DKEN = '0' AND EDGE = '1') OR (ISEL = '1' AND BSEL_BIT = '1' AND DSEL_BIT = '0' AND DKEN_BIT = '0' AND EDGE_BIT = '1')), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_D0_IDCKrise, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_IDCKrise ); VitalSetupHoldCheck ( TestSignal => DE, TestSignalName => "DE", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_D0_IDCK + tCD, SetupLow => tsetup_D0_IDCK + tCD, HoldHigh => thold_D0_IDCK + tCD, HoldLow => thold_D0_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '1' AND DSEL = '0' AND DKEN = '0' AND EDGE = '1') OR (ISEL = '1' AND BSEL_BIT = '1' AND DSEL_BIT = '0' AND DKEN_BIT = '0' AND EDGE_BIT = '1')), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_IDCKrise, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_IDCKrise ); VitalSetupHoldCheck ( TestSignal => VSYNC, TestSignalName => "VSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_D0_IDCK + tCD, SetupLow => tsetup_D0_IDCK + tCD, HoldHigh => thold_D0_IDCK + tCD, HoldLow => thold_D0_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '1' AND DSEL = '0' AND DKEN = '0' AND EDGE = '1') OR (ISEL = '1' AND BSEL_BIT = '1' AND DSEL_BIT = '0' AND DKEN_BIT = '0' AND EDGE_BIT = '1')), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_VSYNC_IDCKrise, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_VSYNC_IDCKrise ); VitalSetupHoldCheck ( TestSignal => HSYNC, TestSignalName => "HSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_D0_IDCK + tCD, SetupLow => tsetup_D0_IDCK + tCD, HoldHigh => thold_D0_IDCK + tCD, HoldLow => thold_D0_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '1' AND DSEL = '0' AND DKEN = '0' AND EDGE = '1') OR (ISEL = '1' AND BSEL_BIT = '1' AND DSEL_BIT = '0' AND DKEN_BIT = '0' AND EDGE_BIT = '1')), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_HSYNC_IDCKrise, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSYNC_IDCKrise ); VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "DIn", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DE_IDCK + tCD, SetupLow => tsetup_DE_IDCK + tCD, HoldHigh => thold_DE_IDCK + tCD, HoldLow => thold_DE_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '0' AND DSEL = '1' AND DKEN = '0') OR (ISEL = '1' AND BSEL_BIT = '0' AND DSEL_BIT = '1' AND DKEN_BIT = '0')), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_D0_IDCKfalld, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_IDCKfalld ); VitalSetupHoldCheck ( TestSignal => DE, TestSignalName => "DE", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DE_IDCK + tCD, SetupLow => tsetup_DE_IDCK + tCD, HoldHigh => thold_DE_IDCK + tCD, HoldLow => thold_DE_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '0' AND DSEL = '1' AND DKEN = '0') OR (ISEL = '1' AND BSEL_BIT = '0' AND DSEL_BIT = '1' AND DKEN_BIT = '0')), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_IDCKfalld, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_IDCKfalld ); VitalSetupHoldCheck ( TestSignal => VSYNC, TestSignalName => "VSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DE_IDCK + tCD, SetupLow => tsetup_DE_IDCK + tCD, HoldHigh => thold_DE_IDCK + tCD, HoldLow => thold_DE_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '0' AND DSEL = '1' AND DKEN = '0') OR (ISEL = '1' AND BSEL_BIT = '0' AND DSEL_BIT = '1' AND DKEN_BIT = '0')), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_VSYNC_IDCKfalld, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_VSYNC_IDCKfalld ); VitalSetupHoldCheck ( TestSignal => HSYNC, TestSignalName => "HSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DE_IDCK + tCD, SetupLow => tsetup_DE_IDCK + tCD, HoldHigh => thold_DE_IDCK + tCD, HoldLow => thold_DE_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '0' AND DSEL = '1' AND DKEN = '0') OR (ISEL = '1' AND BSEL_BIT = '0' AND DSEL_BIT = '1' AND DKEN_BIT = '0')), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_HSYNC_IDCKfalld, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSYNC_IDCKfalld ); VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "DIn", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DE_IDCK + tCD, SetupLow => tsetup_DE_IDCK + tCD, HoldHigh => thold_DE_IDCK + tCD, HoldLow => thold_DE_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '0' AND DSEL = '1' AND DKEN = '0') OR (ISEL = '1' AND BSEL_BIT = '0' AND DSEL_BIT = '1' AND DKEN_BIT = '0')), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_D0_IDCKrised, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_IDCKrised ); VitalSetupHoldCheck ( TestSignal => DE, TestSignalName => "DE", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DE_IDCK + tCD, SetupLow => tsetup_DE_IDCK + tCD, HoldHigh => thold_DE_IDCK + tCD, HoldLow => thold_DE_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '0' AND DSEL = '1' AND DKEN = '0') OR (ISEL = '1' AND BSEL_BIT = '0' AND DSEL_BIT = '1' AND DKEN_BIT = '0')), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DE_IDCKrised, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DE_IDCKrised ); VitalSetupHoldCheck ( TestSignal => VSYNC, TestSignalName => "VSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DE_IDCK + tCD, SetupLow => tsetup_DE_IDCK + tCD, HoldHigh => thold_DE_IDCK + tCD, HoldLow => thold_DE_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '0' AND DSEL = '1' AND DKEN = '0') OR (ISEL = '1' AND BSEL_BIT = '0' AND DSEL_BIT = '1' AND DKEN_BIT = '0')), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_VSYNC_IDCKrised, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_VSYNC_IDCKrised ); VitalSetupHoldCheck ( TestSignal => HSYNC, TestSignalName => "HSYNC", RefSignal => IDCK, RefSignalName => "IDCK", SetupHigh => tsetup_DE_IDCK + tCD, SetupLow => tsetup_DE_IDCK + tCD, HoldHigh => thold_DE_IDCK + tCD, HoldLow => thold_DE_IDCK + tCD, CheckEnabled => ((ISEL = '0' AND BSEL = '0' AND DSEL = '1' AND DKEN = '0') OR (ISEL = '1' AND BSEL_BIT = '0' AND DSEL_BIT = '1' AND DKEN_BIT = '0')), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_HSYNC_IDCKrised, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSYNC_IDCKrised ); VitalPeriodPulseCheck ( TestSignal => IDCK, TestSignalName => "IDCK", Period => tperiod_IDCK, PeriodData => PD_IDCK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_IDCK, HeaderMsg => InstancePath & PartID, CheckEnabled => true ); Violation := Tviol_D0_IDCKfall OR Tviol_DE_IDCKfall OR Tviol_VSYNC_IDCKfall OR Tviol_HSYNC_IDCKfall OR Tviol_D0_IDCKrise OR Tviol_DE_IDCKrise OR Tviol_VSYNC_IDCKrise OR Tviol_HSYNC_IDCKrise OR Tviol_D0_IDCKfalld OR Tviol_DE_IDCKfalld OR Tviol_VSYNC_IDCKfalld OR Tviol_HSYNC_IDCKfalld OR Tviol_D0_IDCKrised OR Tviol_DE_IDCKrised OR Tviol_VSYNC_IDCKrised OR Tviol_HSYNC_IDCKrised OR Pviol_IDCK; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY SeverityMode; END IF; ---------------------------------------------------------------------------- -- Functional Section ---------------------------------------------------------------------------- IF (ISEL = '0' AND BSEL = '1') OR (ISEL = '1' AND BSEL_BIT = '1') THEN -- 24 bit, single-edge mode IF (DSEL = '0' AND ISEL = '0') OR (DSEL_BIT = '0' AND ISEL = '1') THEN --single-ended clock input mode IF (EDGE = '0' AND ISEL = '0') OR (EDGE_BIT = '0' AND ISEL = '1') THEN --latch on falling edge of IDCK+ IF falling_edge(IDCK) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1')THEN DATA_RED <= DIn(23 downto 16); DATA_GREEN <= DIn(15 downto 8); DATA_BLUE <= DIn(7 downto 0); change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); END IF; END IF; ELSE --latch on rising edge of IDCK+ IF rising_edge(IDCK) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_RED <= DIn(23 downto 16); DATA_GREEN <= DIn(15 downto 8); DATA_BLUE <= DIn(7 downto 0); change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); END IF; END IF; END IF; ELSE --differential clock input mode IF (EDGE = '0' AND ISEL = '0') OR (EDGE_BIT = '0' AND ISEL = '1') THEN IF rising_edge(IDCKNeg) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_RED <= DIn(23 downto 16); DATA_GREEN <= DIn(15 downto 8); DATA_BLUE <= DIn(7 downto 0); change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); END IF; END IF; ELSE IF rising_edge(IDCK) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_RED <= DIn(23 downto 16); DATA_GREEN <= DIn(15 downto 8); DATA_BLUE <= DIn(7 downto 0); change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_red <= not(change_red); change_blue <= not(change_blue); change_green <= not(change_green); END IF; END IF; END IF; END IF; ELSE --12 bit, Dual-edge input mode IF (DSEL = '1' AND ISEL = '0') OR (DSEL_BIT = '1' AND ISEL = '1') THEN --single-ended clock input mode IF (EDGE = '0' AND ISEL = '0') OR (EDGE_BIT = '0' AND ISEL = '1') THEN --first latch on falling edge of IDCK+ IF falling_edge(IDCK) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_GREEN(3 downto 0) <= DIn(11 downto 8); DATA_BLUE <= DIn(7 downto 0); change_blue <= not(change_blue); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_blue <= not(change_blue); change_green <= not(change_green); END IF; ELSIF rising_edge(IDCK) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_RED <= DIn(11 downto 4); DATA_GREEN(7 downto 4) <= DIn(3 downto 0); change_red <= not(change_red); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_red <= not(change_red); change_green <= not(change_green); END IF; END IF; ELSE --first latch on rising edge of IDCK+ IF rising_edge(IDCK) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_GREEN(3 downto 0) <= DIn(11 downto 8); DATA_BLUE <= DIn(7 downto 0); change_blue <= not(change_blue); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_blue <= not(change_blue); change_green <= not(change_green); END IF; ELSIF falling_edge(IDCK) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_RED <= DIn(11 downto 4); DATA_GREEN(7 downto 4) <= DIn(3 downto 0); change_red <= not(change_red); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_red <= not(change_red); change_green <= not(change_green); END IF; END IF; END IF; ELSE --differential clock input mode IF (EDGE = '0' AND ISEL = '0') OR (EDGE_BIT = '0' AND ISEL = '1') THEN --first latch on falling edge of IDCK+ IF rising_edge(IDCKNeg) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_GREEN(3 downto 0) <= DIn(11 downto 8); DATA_BLUE <= DIn(7 downto 0); change_blue <= not(change_blue); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_blue <= not(change_blue); change_green <= not(change_green); END IF; ELSIF rising_edge(IDCK) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_RED <= DIn(11 downto 4); DATA_GREEN(7 downto 4) <= DIn(3 downto 0); change_red <= not(change_red); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_red <= not(change_red); change_green <= not(change_green); END IF; END IF; ELSE --first latch on rising edge of IDCK+ IF rising_edge(IDCK) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_GREEN(3 downto 0) <= DIn(11 downto 8); DATA_BLUE <= DIn(7 downto 0); change_blue <= not(change_blue); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_blue <= not(change_blue); change_green <= not(change_green); END IF; ELSIF rising_edge(IDCKNeg) THEN IF (DE = '1' AND DE_GEN = '0') OR (DE_int = '1' AND DE_GEN = '1') THEN DATA_RED <= DIn(11 downto 4); DATA_GREEN(7 downto 4) <= DIn(3 downto 0); change_red <= not(change_red); change_green <= not(change_green); ELSE D_VSYNC <= VSYNC; D_HSYNC <= HSYNC; D_CTL1 <= CTL1; D_CTL2 <= CTL2; D_CTL3 <= CTL3; change_red <= not(change_red); change_green <= not(change_green); END IF; END IF; END IF; END IF; END IF; END PROCESS; DEGENERATOR : PROCESS(clk, VSYNC, HSYNC) VARIABLE VSYNC_active : std_logic; VARIABLE HSYNC_active : std_logic; VARIABLE line_cnt : NATURAL := 0; VARIABLE pixel_cnt : NATURAL := 0; VARIABLE de_top_number : NATURAL := 0; VARIABLE de_lin_number : NATURAL := 0; VARIABLE de_cnt_number : NATURAL := 0; VARIABLE de_dly_number : NATURAL := 0; BEGIN de_dly_number := to_nat(DE_CTL(0) & DE_DLY); de_top_number := to_nat(DE_TOP); de_cnt_number := to_nat(DE_CNT(10 downto 0)); de_lin_number := to_nat(DE_LIN(10 downto 0)); IF (VS_POL = '1' AND rising_edge(VSYNC)) OR (VS_POL = '0' AND falling_edge(VSYNC)) THEN VSYNC_active := '1'; line_cnt := 0; pixel_cnt := 0; END IF; IF VSYNC_active = '1' THEN IF (HS_POL = '1' AND rising_edge(HSYNC)) OR (HS_POL = '0' AND falling_edge(HSYNC)) THEN pixel_cnt := 0; line_cnt := line_cnt + 1; IF line_cnt = de_top_number THEN HSYNC_active := '1'; ELSIF line_cnt = de_lin_number + de_top_number THEN HSYNC_active := '0'; END IF; END IF; IF HSYNC_active = '1' and rising_edge(clk) THEN pixel_cnt := pixel_cnt +1; IF pixel_cnt = de_dly_number THEN DE_int <= '1'; ELSIF pixel_cnt = de_dly_number + de_cnt_number THEN DE_int <= '0'; END IF; END IF; END IF; END PROCESS; END BLOCK; END vhdl_behavioral;