------------------------------------------------------------------------------- -- File name : s71ns128ja0.vhd ------------------------------------------------------------------------------- -- Copyright (C) 2004-2005 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V1.0 M.Radmanovic 04 Sep 10 Initial release -- V1.1 M.Radmanovic 05 May 05 Autoselect code Revision ID updated -- Coding style fixed ------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FLASH -- Technology: MCP Flash/SRAM Memory -- Part: s71ns128ja0 -- -- Description: 128Mbit (8M x16-Bit) Simultaneous opration, Burst mode, -- Top boot sector Flash Memory with 16Mbit (1M x16-Bit) pSRAM -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.all; USE FMF.conversions.all; ------------------------------------------------------------------------------- -- ENTITY DECLARATION FOR s71ns128ja0 TOP MODULE ------------------------------------------------------------------------------- ENTITY s71ns128ja0 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_A18 : VitalDelayType01 := VitalZeroDelay01; tipd_A19 : VitalDelayType01 := VitalZeroDelay01; tipd_A20 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- A/DQ15- tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- A/DQ0 tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_AVDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LBNeg : VitalDelayType01 := VitalZeroDelay01;-- A21/LB# tipd_UBNeg : VitalDelayType01 := VitalZeroDelay01;-- A22/UB# tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; tipd_Vpp : VitalDelayType01 := VitalZeroDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded flash_file_name : STRING := "none"; sram_file_name : STRING := "none"; UserPreload : BOOLEAN := FALSE; LongTimming : BOOLEAN := FALSE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A20 : IN std_ulogic := 'U'; A19 : IN std_ulogic := 'U'; A18 : IN std_ulogic := 'U'; A17 : IN std_ulogic := 'U'; A16 : IN std_ulogic := 'U'; DQ15 : INOUT std_logic := 'U'; DQ14 : INOUT std_logic := 'U'; DQ13 : INOUT std_logic := 'U'; DQ12 : INOUT std_logic := 'U'; DQ11 : INOUT std_logic := 'U'; DQ10 : INOUT std_logic := 'U'; DQ9 : INOUT std_logic := 'U'; DQ8 : INOUT std_logic := 'U'; DQ7 : INOUT std_logic := 'U'; DQ6 : INOUT std_logic := 'U'; DQ5 : INOUT std_logic := 'U'; DQ4 : INOUT std_logic := 'U'; DQ3 : INOUT std_logic := 'U'; DQ2 : INOUT std_logic := 'U'; DQ1 : INOUT std_logic := 'U'; DQ0 : INOUT std_logic := 'U'; CENeg : IN std_ulogic := 'U'; CSNeg : IN std_ulogic := 'U'; AVDNeg : IN std_ulogic := 'U'; LBNeg : IN std_ulogic := 'U'; UBNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; CLK : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; Vpp : IN std_ulogic := 'U'; RDY : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of s71ns128ja0 : ENTITY IS TRUE; END s71ns128ja0; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.all; USE FMF.conversions.all; ------------------------------------------------------------------------------- -- ENTITY DECLARATION FOR s29ns128j ------------------------------------------------------------------------------- ENTITY s29ns128j IS GENERIC ( -- tipd delays: interconnect path delays tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_A18 : VitalDelayType01 := VitalZeroDelay01; tipd_A19 : VitalDelayType01 := VitalZeroDelay01; tipd_A20 : VitalDelayType01 := VitalZeroDelay01; tipd_A21 : VitalDelayType01 := VitalZeroDelay01; tipd_A22 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- A/DQ15- tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- A/DQ0 tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_AVDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_Vpp : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays for FLASH tpd_A16_DQ0_asynchro_eq_0 : VitalDelayType01 := UnitDelay01; tpd_A16_DQ0_asynchro_eq_1 : VitalDelayType01 := UnitDelay01; tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; tpd_CLK_RDY : VitalDelayType01 := UnitDelay01; tpd_CLK_DQ0 : VitalDelayType01 := UnitDelay01; tpd_OENeg_RDY : VitalDelayType01Z := UnitDelay01Z; tpd_CENeg_RDY : VitalDelayType01Z := UnitDelay01Z; -- Burst Mode --tCES , CE LOW , CLK / tsetup_CENeg_CLK : VitalDelayType := UnitDelay; tsetup_RDY_CLK : VitalDelayType := UnitDelay; -- Asynchronous Write --tCS, CENeg LOW, WENeg \ tsetup_CENeg_WENeg : VitalDelayType := UnitDelay; --tAS, , WENeg \ tsetup_A16_AVDNeg : VitalDelayType := UnitDelay; --tDS, , WENeg / tsetup_DQ0_WENeg : VitalDelayType := UnitDelay; --tGHWL, OENeg HIGH , WENeg \ tsetup_OENeg_WENeg : VitalDelayType := UnitDelay; --tOEH, WENeg HIGH , OENeg \ tsetup_WENeg_OENeg : VitalDelayType := UnitDelay; tsetup_AVDNeg_CLK : VitalDelayType := UnitDelay; --thold values -- tAH, , WENeg \ thold_A16_AVDNeg : VitalDelayType := UnitDelay; -- tDH, , WENeg / thold_DQ0_WENeg : VitalDelayType := UnitDelay; thold_DQ0_CLK : VitalDelayType := UnitDelay; --tRH , CENeg HIGH, RESET / thold_CENeg_RESETNeg : VitalDelayType := UnitDelay; --tRH , OENeg HIGH, RESET / thold_OENeg_RESETNeg : VitalDelayType := UnitDelay; --tWH ,WENeg LOW ,CENeg / thold_CENeg_WENeg : VitalDelayType := UnitDelay; thold_AVDNeg_CLK : VitalDelayType := UnitDelay; --tpw values: pulse width -- Burst Mode tpw_AVDNeg_negedge : VitalDelayType := UnitDelay; -- tADVP -- Reset tpw_RESETNeg_negedge : VitalDelayType := UnitDelay; -- tRP -- ASync Write tpw_WENeg_negedge : VitalDelayType := UnitDelay; -- tWP tpw_WENeg_posedge : VitalDelayType := UnitDelay; -- tWPH -- tdevice values: values for internal delays tdevice_POW : VitalDelayType := UnitDelay; --Sector Erase Operation tWHWH2 tdevice_SEO : VitalDelayType := UnitDelay; --erase suspend timeout - only max time specified tdevice_ESTART_T1 : VitalDelayType := UnitDelay; --sector erase command sequence timeout tdevice_CTMOUT : VitalDelayType := UnitDelay; --device ready after Hardware reset(during embeded algorithm) tdevice_READY : VitalDelayType := UnitDelay; --tReady -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded flash_file_name : STRING := "none"; UserPreload : BOOLEAN := FALSE; LongTimming : BOOLEAN := FALSE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A22 : IN std_ulogic := 'U'; A21 : IN std_ulogic := 'U'; A20 : IN std_ulogic := 'U'; A19 : IN std_ulogic := 'U'; A18 : IN std_ulogic := 'U'; A17 : IN std_ulogic := 'U'; A16 : IN std_ulogic := 'U'; DQ15 : INOUT std_ulogic := 'U'; DQ14 : INOUT std_ulogic := 'U'; DQ13 : INOUT std_ulogic := 'U'; DQ12 : INOUT std_ulogic := 'U'; DQ11 : INOUT std_ulogic := 'U'; DQ10 : INOUT std_ulogic := 'U'; DQ9 : INOUT std_ulogic := 'U'; DQ8 : INOUT std_ulogic := 'U'; DQ7 : INOUT std_ulogic := 'U'; DQ6 : INOUT std_ulogic := 'U'; DQ5 : INOUT std_ulogic := 'U'; DQ4 : INOUT std_ulogic := 'U'; DQ3 : INOUT std_ulogic := 'U'; DQ2 : INOUT std_ulogic := 'U'; DQ1 : INOUT std_ulogic := 'U'; DQ0 : INOUT std_ulogic := 'U'; CENeg : IN std_ulogic := 'U'; AVDNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; CLK : IN std_ulogic := 'U'; Vpp : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; RDY : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of s29ns128j : ENTITY IS TRUE; END s29ns128j; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral_flash of s29ns128j IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral_flash : ARCHITECTURE IS TRUE; CONSTANT PartID : STRING := "s29ns128j"; CONSTANT MaxData : NATURAL := 16#FFFF#; CONSTANT MemSize : NATURAL := 16#7FFFFF#; CONSTANT SecSize : NATURAL := 16#8000#; CONSTANT SubSecSize : NATURAL := 16#2000#; CONSTANT BankNum : NATURAL := 4; CONSTANT SecNum : NATURAL := 256; CONSTANT SecNumBank : NATURAL := 64; CONSTANT SubSecNum : NATURAL := 4; CONSTANT HiAddrBit : NATURAL := 22; CONSTANT LowSecAddrBit : NATURAL := 15; CONSTANT TopSec : NATURAL := 255; CONSTANT BurstBound : NATURAL := 64; CONSTANT SP_bit : NATURAL := 6; CONSTANT HighCommand_bit: NATURAL := 19; CONSTANT LowCommand_bit : NATURAL := 12; CONSTANT ComandBurstInit: std_logic_vector(7 DOWNTO 0) := "00000101"; -- interconnect path delay signals SIGNAL A22_ipd : std_ulogic := 'U'; SIGNAL A21_ipd : std_ulogic := 'U'; SIGNAL A20_ipd : std_ulogic := 'U'; SIGNAL A19_ipd : std_ulogic := 'U'; SIGNAL A18_ipd : std_ulogic := 'U'; SIGNAL A17_ipd : std_ulogic := 'U'; SIGNAL A16_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL CENeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; SIGNAL AVDNeg_ipd : std_ulogic := 'U'; SIGNAL CLK_ipd : std_ulogic := 'U'; SIGNAL Vpp_ipd : std_ulogic := 'U'; SIGNAL WPNeg_ipd : std_ulogic := 'U'; --- internal delays SIGNAL POW_out : std_ulogic := '0'; SIGNAL SEO_out : std_ulogic := '0'; SIGNAL POW_in : std_ulogic := '0'; SIGNAL SEO_in : std_ulogic := '0'; SIGNAL ESTART_T1_out : std_ulogic := '0'; --Erase Start TimeOut SIGNAL ESTART_T1_in : std_ulogic := '0'; SIGNAL CTMOUT_out : std_ulogic := '0'; -- start erease timeout SIGNAL CTMOUT_in : std_ulogic := '0'; SIGNAL READY_in : std_ulogic := '0'; SIGNAL READY_out : std_ulogic := '0'; --Device ready after reset BEGIN --------------------------------------------------------------------------- -- Internal Delays --------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays POW :VitalBuf(POW_out, POW_in, (tdevice_POW ,UnitDelay)); SEO :VitalBuf(SEO_out, SEO_in, (tdevice_SEO ,UnitDelay)); CTMOUT :VitalBuf(CTMOUT_out, CTMOUT_in, (tdevice_CTMOUT ,UnitDelay)); READY :VitalBuf(READY_out, READY_in, (tdevice_READY ,UnitDelay)); ESTART_T1 :VitalBuf(ESTART_T1_out, ESTART_T1_in, (tdevice_ESTART_T1,UnitDelay)); --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_0 : VitalWireDelay (A22_ipd, A22, tipd_A22); w_1 : VitalWireDelay (A21_ipd, A21, tipd_A21); w_2 : VitalWireDelay (A20_ipd, A20, tipd_A20); w_3 : VitalWireDelay (A19_ipd, A19, tipd_A19); w_4 : VitalWireDelay (A18_ipd, A18, tipd_A18); w_5 : VitalWireDelay (A17_ipd, A17, tipd_A17); w_6 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_7 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15); w_8 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14); w_9 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13); w_10 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12); w_11 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11); w_12 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10); w_13 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9); w_14 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8); w_15 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7); w_16 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6); w_17 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5); w_18 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4); w_19 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_20 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_21 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_22 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_23 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_24 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_25 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg); w_26 : VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg); w_27 : VitalWireDelay (AVDNeg_ipd, AVDNeg, tipd_AVDNeg); w_28 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_29 : VitalWireDelay (Vpp_ipd, Vpp, tipd_Vpp); w_30 : VitalWireDelay (WPNeg_ipd, WPNeg, tipd_WPNeg); END BLOCK; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior: BLOCK PORT ( A : IN std_logic_vector(HiAddrBit DOWNTO 0) := (OTHERS => 'U'); DIn : IN std_logic_vector(15 DOWNTO 0) := (OTHERS => 'U'); DOut : OUT std_logic_vector(15 DOWNTO 0) := (OTHERS => 'Z'); CENeg : IN std_ulogic := 'U'; AVDNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; Vpp : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; CLK : IN std_ulogic := 'U'; RDY : OUT std_ulogic := 'U' ); PORT MAP ( A(22) => A22_ipd, A(21) => A21_ipd, A(20) => A20_ipd, A(19) => A19_ipd, A(18) => A18_ipd, A(17) => A17_ipd, A(16) => A16_ipd, A(15) => DQ15_ipd, A(14) => DQ14_ipd, A(13) => DQ13_ipd, A(12) => DQ12_ipd, A(11) => DQ11_ipd, A(10) => DQ10_ipd, A(9) => DQ9_ipd, A(8) => DQ8_ipd, A(7) => DQ7_ipd, A(6) => DQ6_ipd, A(5) => DQ5_ipd, A(4) => DQ4_ipd, A(3) => DQ3_ipd, A(2) => DQ2_ipd, A(1) => DQ1_ipd, A(0) => DQ0_ipd, DIn(15) => DQ15_ipd, DIn(14) => DQ14_ipd, DIn(13) => DQ13_ipd, DIn(12) => DQ12_ipd, DIn(11) => DQ11_ipd, DIn(10) => DQ10_ipd, DIn(9) => DQ9_ipd, DIn(8) => DQ8_ipd, DIn(7) => DQ7_ipd, DIn(6) => DQ6_ipd, DIn(5) => DQ5_ipd, DIn(4) => DQ4_ipd, DIn(3) => DQ3_ipd, DIn(2) => DQ2_ipd, DIn(1) => DQ1_ipd, DIn(0) => DQ0_ipd, DOut(15) => DQ15, DOut(14) => DQ14, DOut(13) => DQ13, DOut(12) => DQ12, DOut(11) => DQ11, DOut(10) => DQ10, DOut(9) => DQ9, DOut(8) => DQ8, DOut(7) => DQ7, DOut(6) => DQ6, DOut(5) => DQ5, DOut(4) => DQ4, DOut(3) => DQ3, DOut(2) => DQ2, DOut(1) => DQ1, DOut(0) => DQ0, CENeg => CENeg_ipd, AVDNeg => AVDNeg_ipd, OENeg => OENeg_ipd, WENeg => WENeg_ipd, RESETNeg => RESETNeg_ipd, Vpp => Vpp_ipd, WPNeg => WPNEg, CLK => CLK, RDY => RDY ); -- State Machine : State_Type TYPE state_type IS ( RESET, Z001, -- unlock cycle 1 PREL_SETBWB, -- unlock cycle 2 PREL_ULBYPASS, UNLOCK_RESET, -- unlock reset state SEC_SECURITY_PRIOR2, -- first state for protection SEC_SECURITY_PRIOR, -- second state for protection SEC_SECURITY, -- sector protection state CFI, -- CFI MOD AS, -- autoselect AS_CFI, -- CFI from autoselect A0SEEN, -- program preeliminary C8, -- erase preeliminary C8_Z001, -- erase unlock bypass1 C8_PREL, -- erase unlock bypass2 ERS, -- erase SERS, -- sector erase ESPS, SERS_EXEC, ESP, ESP_AS, ESP_Z001, -- erase unlock 1 ESP_SETBWB, -- erase unlock 2 ESP_CFI, -- ersae CFI MOD ESP_ULBYPASS, -- unlock bypass ESP_UNLOCK_RESET, -- reset unlock during suspend ESP_AS_CFI, ESP_A0SEEN, -- erase programing PGMS ); -- State for read FLASH TYPE read_mem_type IS (IDLE_READ, BURST_READ); --Array of Sub sector start-end address within sector TYPE SubSecAddr IS ARRAY (0 TO SubSecNum-1) OF NATURAL; TYPE SecType IS ARRAY (0 TO SecSize-1) OF INTEGER RANGE -1 TO MaxData; --Flash Memory Bank Array TYPE MemArray IS ARRAY (0 TO SecNum-1) OF SecType; -- states TYPE BURST_TYPE IS (LINEAR, WRAP_AROUND, WRAP_NO_AROUND); SIGNAL current_state : state_type; SIGNAL next_state : state_type; SIGNAL BurstState : read_mem_type; -- powerup SIGNAL PoweredUp : std_logic := '0'; --zero delay signals SIGNAL DOut_zd : std_logic_vector(15 DOWNTO 0) := (OTHERS =>'Z'); SIGNAL RDY_zd : std_logic := 'Z'; SIGNAL RDY_pass : std_logic := 'Z'; SIGNAL DOut_pass : std_logic_vector(15 DOWNTO 0) := (OTHERS =>'Z'); --FSM control signals SIGNAL BankBypassLock : std_logic_vector(BankNum-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL ULBYPASS : std_logic := '0'; SIGNAL SERS_ACT : std_logic := '0'; --Program Embedded SIGNAL PGMS_ACT : std_logic := '0'; --Erase Embedded -- signal for sector security process SIGNAL SecSecurity : std_logic := '0'; SIGNAL PDONE : std_logic := '1'; --Prog. Done SIGNAL PSTART : std_logic := '0'; --Start Programming --Program location is in protected sector SIGNAL PERR : std_logic := '0'; SIGNAL EDONE : std_logic := '1'; --Ers. Done SIGNAL ESTART : std_logic := '0'; --Start Erase SIGNAL ESUSP : std_logic := '0'; --Suspend Erase SIGNAL ESTART_SUSP : std_logic := '0'; --Start and suspend Erase SIGNAL ERES : std_logic := '0'; --Resume Erase --All sectors selected for erasure are protected SIGNAL EERR : std_logic := '0'; --Sectors selected for erasure SIGNAL ERS_QUEUE : std_logic_vector(SecNum-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL ERS_SUBTOP_QUEUE : std_logic_vector(SubSecNum-1 DOWNTO 0) := (OTHERS => '0'); --Command Register SIGNAL write : std_logic := '0'; SIGNAL read : std_logic := '0'; --Address within sector SHARED VARIABLE Address : NATURAL RANGE 0 TO SecSize := 0; SHARED VARIABLE BA : NATURAL RANGE 0 TO BankNum := 0; SHARED VARIABLE SSA : NATURAL RANGE 0 TO SubSecNum := 0; SHARED VARIABLE SA : NATURAL RANGE 0 TO SecNum := 0; SHARED VARIABLE Addr : NATURAL RANGE 0 TO 16#7FF# := 0; SIGNAL AddressLatch : std_logic_vector(HiAddrBit DOWNTO 0); SIGNAL AddressLatch_flag : BOOLEAN := FALSE; SIGNAL D_tmp : NATURAL RANGE 0 TO MaxData; SIGNAL D_tmp0 : NATURAL RANGE 0 TO MaxData; --glitch protection SIGNAL gWE_n : std_logic := '1'; SIGNAL gCE_n : std_logic := '1'; SIGNAL gOE_n : std_logic := '1'; SIGNAL RST : std_logic := '1'; SIGNAL reseted : std_logic := '0'; -- Mem(BA)(SecAddrBank)(Address).... SHARED VARIABLE Mem : MemArray := (OTHERS => (OTHERS => MaxData)); --protected sectors and sub sectors SIGNAL Sec_Prot : std_logic_vector(SecNum-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL SubSecTop_Prot : std_logic_vector(SubSecNum-1 DOWNTO 0) := (OTHERS => '1'); SHARED VARIABLE sssa : SubSecAddr := (16#0000#, 16#2000#, 16#4000#, 16#6000#); SHARED VARIABLE ssea : SubSecAddr:= (16#1FFF#, 16#3FFF#, 16#5FFF#, 16#7FFF#); -- synchro burst mode SIGNAL BurstModeReg : std_logic_vector (HighCommand_bit-LowCommand_bit DOWNTO 0):= ComandBurstInit; ALIAS WrapAround : std_logic is BurstModeReg(5); -- Clock_Act = 1 active is rising adge ALIAS BurstMode : std_logic_vector(2 DOWNTO 0) IS BurstModeReg(5 DOWNTO 3); ALIAS BurstWait : std_logic_vector(2 DOWNTO 0) IS BurstModeReg(2 DOWNTO 0); -- timing check violation SIGNAL Viol : X01 := '0'; -- insert for bankmode SHARED VARIABLE BankAutosel : std_logic_vector(BankNum-1 DOWNTO 0) := (OTHERS => '0'); SHARED VARIABLE BankBusy : std_logic_vector(BankNum-1 DOWNTO 0) := (OTHERS => '0'); SHARED VARIABLE BankEraseExec : std_logic_vector(BankNum-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL BankErase : std_logic_vector(BankNum-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL Start_burst : std_logic:= '0'; SIGNAL End_b : std_logic:= '0'; SIGNAL End_b2 : std_logic:= '0'; SIGNAL End_b3 : std_logic:= '0'; -- temp RDY signal SIGNAL RDY_s : std_logic; -- signal that enable delay from clk SIGNAL clk_oe_en : std_logic := '0'; SIGNAL clk_addr_en : std_logic := '1'; SIGNAL tpd_fromOE : std_logic := '0'; SIGNAL tpd_fromCE : std_logic := '0'; SHARED VARIABLE FROMOE,FROMCE, FROMCLK, OPENLATCH : boolean; SHARED VARIABLE tpd_from_OE : BOOLEAN := FALSE; SHARED VARIABLE tpd_from_CE : BOOLEAN := FALSE; SHARED VARIABLE Open3state : BOOLEAN := FALSE; SHARED VARIABLE ASynchroMod : BOOLEAN := TRUE; SHARED VARIABLE Start_burst_tmp : BOOLEAN := FALSE; SHARED VARIABLE PathDisable : BOOLEAN := TRUE; SHARED VARIABLE RDY_tmp : std_logic; SHARED VARIABLE ERASE_START : TIME; BEGIN --------------------------------------------------------------------------- --Power Up time 100 ns; --------------------------------------------------------------------------- PoweredUp <= '1' AFTER 100 ns; RST <= RESETNeg AFTER 500 ns; --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS(CENeg, AVDNeg, WENeg, OENeg, RESETNeg,A, CLK, RDY_s, DIn) --Setup/Hold checks variables VARIABLE Tviol_CENeg_CLK : X01 := '0'; VARIABLE Tviol_AVDNeg_CLK : X01 := '0'; VARIABLE Tviol_DQ0_CLK : X01 := '0'; VARIABLE Tviol_RDY_CLK : X01 := '0'; VARIABLE Tviol_WENeg_CENeg : X01 := '0'; VARIABLE Tviol_CENeg_RESETNeg : X01 := '0'; VARIABLE Tviol_OENeg_RESETNeg : X01 := '0'; VARIABLE Tviol_OENeg_WENeg : X01 := '0'; VARIABLE Tviol_A16_CLK : X01 := '0'; VARIABLE Tviol_A16_WENeg : X01 := '0'; VARIABLE Tviol_DQ0_WENeg : X01 := '0'; VARIABLE Tviol_WENeg_OENeg : X01 := '0'; VARIABLE Tviol_A16_AVDNeg : X01 := '0'; VARIABLE Tviol_CENeg_AVDNeg : X01 := '0'; VARIABLE Tviol_CLK_AVDNeg : X01 := '0'; VARIABLE Tviol_CENeg_WENeg_setup : X01 := '0'; VARIABLE Tviol_CENeg_WENeg_hold : X01 := '0'; VARIABLE TD_AVDNeg_CLK : VitalTimingDataType; VARIABLE TD_DQ0_CLK : VitalTimingDataType; VARIABLE TD_RDY_CLK : VitalTimingDataType; VARIABLE TD_CENeg_CLK : VitalTimingDataType; VARIABLE TD_WENeg_CENeg : VitalTimingDataType; VARIABLE TD_CENeg_RESETNeg : VitalTimingDataType; VARIABLE TD_OENeg_RESETNeg : VitalTimingDataType; VARIABLE TD_OENeg_WENeg : VitalTimingDataType; VARIABLE TD_A16_CLK : VitalTimingDataType; VARIABLE TD_A16_WENeg : VitalTimingDataType; VARIABLE TD_DQ0_WENeg : VitalTimingDataType; VARIABLE TD_WENeg_OENeg : VitalTimingDataType; VARIABLE TD_A16_AVDNeg : VitalTimingDataType; VARIABLE TD_AVDNeg_WENeg : VitalTimingDataType; VARIABLE TD_CENeg_AVDNeg : VitalTimingDataType; VARIABLE TD_CLK_AVDNeg : VitalTimingDataType; VARIABLE TD_CENeg_WENeg_setup : VitalTimingDataType; VARIABLE TD_CENeg_WENeg_hold : VitalTimingDataType; -- Pulse width cheks variables VARIABLE Pviol_CENeg : X01 := '0'; VARIABLE Pviol_WENeg : X01 := '0'; VARIABLE Pviol_AVDNeg : X01 := '0'; VARIABLE Pviol_RESETNeg : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_CENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_WENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AVDNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01; BEGIN IF TimingChecksOn THEN -- Setup/Hold Checks Violation := '0'; --tCES VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => CLK, RefSignalName => "CLK", SetupLow => tsetup_CENeg_CLK, CheckEnabled => AVDNeg = '0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CENeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CENeg_CLK ); VitalSetupHoldCheck ( TestSignal => AVDNeg, TestSignalName => "AVDNeg", RefSignal => CLK, RefSignalName => "CLK", SetupLow => tsetup_AVDNeg_CLK, HoldLow => thold_AVDNeg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_AVDNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AVDNeg_CLK ); VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => CLK, RefSignalName => "CLK", SetupLow => tsetup_A16_AVDNeg, SetupHigh => tsetup_A16_AVDNeg, HoldLow => thold_A16_AVDNeg, HoldHigh => thold_A16_AVDNeg, CheckEnabled => AVDNeg = '0' , RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_A16_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A16_CLK ); VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => AVDNeg, RefSignalName => "AVDNeg", SetupLow => tsetup_A16_AVDNeg, SetupHigh => tsetup_A16_AVDNeg, HoldLow => thold_A16_AVDNeg, HoldHigh => thold_A16_AVDNeg, CheckEnabled => AddressLatch_flag = FALSE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_A16_AVDNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A16_AVDNeg ); VitalSetupHoldCheck ( TestSignal => Din, TestSignalName => "Din", RefSignal => WENeg, RefSignalName => "WENeg", SetupLow => tsetup_DQ0_WENeg, SetupHigh => tsetup_DQ0_WENeg, HoldLow => thold_DQ0_WENeg, HoldHigh => thold_DQ0_WENeg, CheckEnabled => CENeg = '0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_DQ0_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DQ0_WENeg ); VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "DOut", RefSignal => CLK, RefSignalName => "CLK", HoldLow => thold_DQ0_CLK, HoldHigh => thold_DQ0_CLK, CheckEnabled => RDY_s = '1', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_DQ0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DQ0_CLK ); VitalSetupHoldCheck ( TestSignal => RDY_s, TestSignalName => "RDY", RefSignal => CLK, RefSignalName => "CLK", SetupLow => tsetup_RDY_CLK, SetupHigh => tsetup_RDY_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_DQ0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RDY_CLK ); VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => WENeg, RefSignalName => "WENeg", SetupLow => tsetup_CENeg_WENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_CENeg_WENeg_setup, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CENeg_WENeg_setup ); VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => AVDNeg, RefSignalName => "AVDNeg", SetupLow => tsetup_CENeg_WENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_CENeg_AVDNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CENeg_AVDNeg ); VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OENeg", RefSignal => WENeg, RefSignalName => "WENeg", SetupHigh => tsetup_OENeg_WENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_OENeg_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_OENeg_WENeg ); VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WENeg", RefSignal => OENeg, RefSignalName => "OENeg", SetupHigh => tsetup_WENeg_OENeg, CheckEnabled => PGMS_ACT = '1'AND SERS_ACT = '1', RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_WENeg_OENeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENeg_OENeg ); VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => RESETNeg, RefSignalName => "RESETNeg", HoldHigh => thold_CENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CENeg_RESETNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CENeg_RESETNeg ); VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OENeg", RefSignal => RESETNeg, RefSignalName => "RESETNeg", HoldHigh => thold_OENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_OENeg_RESETNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_OENeg_RESETNeg ); VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => WENeg, RefSignalName => "WENeg", HoldLow => thold_CENeg_WENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CENeg_WENeg_hold, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CENeg_WENeg_hold ); VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthHigh => tpw_WENeg_posedge, PulseWidthLow => tpw_WENeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WENeg ); VitalPeriodPulseCheck ( TestSignal => AVDNeg, TestSignalName => "AVDNeg", PulseWidthLow => tpw_AVDNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AVDNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AVDNeg ); --RESET pulse width will be shorter than tpw_RESETNeg_negedge during simulation --in order to check if device works properly. If you still want these warnings --uncomment the following section VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESETNeg", PulseWidthLow => tpw_RESETNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RESETNeg ); Violation := Tviol_CENeg_CLK OR Tviol_AVDNeg_CLK OR Tviol_WENeg_CENeg OR Tviol_CENeg_RESETNeg OR Tviol_OENeg_RESETNeg OR Tviol_OENeg_WENeg OR Tviol_A16_CLK OR Tviol_A16_WENeg OR Tviol_DQ0_WENeg OR Tviol_WENeg_OENeg OR Tviol_A16_AVDNeg OR Tviol_CENeg_AVDNeg OR Tviol_CLK_AVDNeg OR Tviol_CENeg_WENeg_setup OR Tviol_CENeg_WENeg_hold OR Tviol_RDY_CLK OR Tviol_DQ0_CLK OR Pviol_CENeg OR Pviol_WENeg OR Pviol_AVDNeg OR Pviol_RESETNeg; ASSERT Violation = '0' REPORT InstancePath & partID & " simulation may be inaccurate due to timing violations" SEVERITY WARNING; viol <= violation; END IF; -- TimingChecksOn END PROCESS VITALTimingCheck; --------------------------------------------------------------------------- -- sequential process for reset control and FSM state transition --------------------------------------------------------------------------- StateTransition : PROCESS(next_state, RESETNeg, RST, READY_out, PDone, EDone, PoweredUp) VARIABLE R : std_logic := '0'; --prog or erase in progress VARIABLE E : std_logic := '0'; --reset timming error BEGIN IF PoweredUp = '1' THEN --Hardware reset timing control IF falling_edge(RESETNeg) THEN E := '0'; IF (PDONE = '0' OR EDONE = '0') THEN --IF program or erase in progress READY_in <= '1'; R := '1'; ELSE READY_in <= '0'; R := '0'; --prog or erase not in progress END IF; ELSIF rising_edge(RESETNeg) AND RST = '1' THEN --RESET# pulse < tRP READY_in <= '0'; R := '0'; E := '1'; END IF; IF RESETNeg = '1' AND ( R = '0' OR (R = '1' AND READY_out = '1')) THEN current_state <= next_state; READY_in <= '0'; E := '0'; R := '0'; reseted <= '1'; ELSIF (R = '0' AND RESETNeg = '0' AND RST = '0') OR (R = '1' AND RESETNeg = '0' AND RST = '0' AND READY_out = '0') OR (R = '1' AND RESETNeg = '1' AND RST = '0' AND READY_out = '0') OR (R = '1' AND RESETNeg = '1' AND RST = '1' AND READY_out = '0') THEN --no state transition while RESET# low current_state <= RESET; --reset start reseted <= '0'; END IF; ELSE current_state <= RESET; -- reset reseted <= '0'; E := '0'; R := '0'; END IF; END PROCESS StateTransition; --------------------------------------------------------------------------- --Glitch Protection: Inertial Delay does not propagate pulses <5ns --------------------------------------------------------------------------- gWE_n <= WENeg AFTER 5 ns; gCE_n <= CENeg AFTER 5 ns; gOE_n <= OENeg AFTER 5 ns; --latch address on rising edge and data on falling edge of write write_dc: PROCESS (gWE_n, gCE_n, gOE_n, AVDNeg, RESETNeg, reseted) BEGIN IF AVDNeg = '1' THEN IF RESETNeg /= '0' AND reseted = '1' THEN IF (gWE_n = '0') AND (gCE_n = '0') AND (gOE_n = '1') THEN write <= '1'; ELSIF (gWE_n = '1' OR gCE_n = '1') AND gOE_n = '1' THEN write <= '0'; ELSE write <= '0'; END IF; ELSE write <= '0'; END IF; IF reseted = '1' THEN IF ((gWE_n = '1') AND (gCE_n = '0') AND (gOE_n = '0')) THEN read <= '1'; ELSE read <= '0'; END IF; ELSE read <= '0'; END IF; ELSE read <= '0'; write <= '0'; END IF; END PROCESS write_dc; --------------------------------------------------------------------------- --Process that reports warning when changes on signals WE#, CE#, OE# are --discarded --------------------------------------------------------------------------- PulseWatch : PROCESS (WENeg, CENeg, OENeg, gWE_n, gCE_n, gOE_n) BEGIN IF (WENeg'EVENT AND (WENeg = gWE_n)) OR (CENeg'EVENT AND (CENeg = gCE_n)) OR (OENeg'EVENT AND (OENeg = gOE_n)) THEN ASSERT false REPORT "Glitch detected on control signals" SEVERITY warning; END IF; END PROCESS PulseWatch; --------------------------------------------------------------------------- -- Latch address process --------------------------------------------------------------------------- BusCycleDecode : PROCESS(A, Din, write, WENeg, CENeg, OENeg, --BYTENeg, reseted, CLK, AVDNeg, gCE_n) VARIABLE Addr_latch : BOOLEAN := FALSE; BEGIN IF reseted = '1' THEN IF (CENeg = '0' AND AVDNeg = '0' AND Addr_Latch = FALSE) THEN Addr := to_nat(A(10 DOWNTO 0)); Address := to_nat(A(LowSecAddrBit-1 DOWNTO 0)); BA := to_nat(A(HiAddrBit DOWNTO HiAddrBit-1)); SSA := to_nat(A(LowSecAddrBit-1 DOWNTO LowSecAddrBit-2)); SA := to_nat(A(HiAddrBit DOWNTO LowSecAddrBit)); AddressLatch <= A; ASynchroMod := TRUE; ELSIF (rising_edge(WENeg) OR rising_edge(CENeg)) AND write = '1' THEN D_tmp0 <= to_nat(Din(7 DOWNTO 0)); D_tmp <= to_nat(Din(15 DOWNTO 0)); END IF; IF (rising_edge(CLK) AND (CENeg = '0' OR gCE_n = '0') AND AVDNeg = '0') THEN Addr_latch := TRUE; ASynchroMod := FALSE; END IF; IF rising_edge(gCE_n) OR (rising_edge(CENeg) AND gCE_n = '1') OR rising_edge(AVDNeg) THEN Addr_latch := FALSE; END IF; AddressLatch_flag <= Addr_latch; ELSE ASynchroMod := TRUE; END IF; END PROCESS BusCycleDecode; --------------------------------------------------------------------------- -- Timing control for the Program Operations --------------------------------------------------------------------------- ProgTime : PROCESS(PSTART, reseted) VARIABLE elapsed : time; VARIABLE duration : time; VARIABLE start : time; BEGIN IF rising_edge(reseted) THEN PDONE <= '1'; -- reset done, programing terminated ELSIF reseted = '1' THEN IF rising_edge(PSTART) AND PDONE = '1' THEN IF ((SA /= TopSec) AND Sec_Prot(SA) = '0' AND Ers_Queue(SA) = '0') OR (SA = TopSec AND SubSecTop_Prot(SSA) = '0' AND Ers_SubTop_Queue(SSA) = '0') THEN duration := tdevice_POW; elapsed := 0 ns; PDONE <= '0', '1' AFTER duration; start := NOW; ELSE PERR <= '1', '0' AFTER 1 us; ASSERT FALSE REPORT "CANNOT WRITE IN SUSPEND/PROTECTED SECTOR" SEVERITY NOTE; END IF; END IF; END IF; END PROCESS ProgTime; --------------------------------------------------------------------------- -- Timing control for the Erase Operations --------------------------------------------------------------------------- ErsTime :PROCESS(ESTART, ESUSP, ESTART_SUSP, ERES, Ers_Queue, Ers_SubTop_Queue, reseted) VARIABLE cnt : NATURAL; VARIABLE elapsed : time; VARIABLE duration : time; VARIABLE start : time; VARIABLE seo : time; BEGIN IF LongTimming = TRUE THEN seo := tdevice_SEO; ELSE seo := tdevice_SEO/1000; END IF; IF rising_edge(reseted) THEN EDONE <= '1'; -- reset done, ERASE terminated ELSIF reseted = '1' THEN IF (rising_edge(ESTART) OR rising_edge(ESTART_SUSP)) AND EDONE = '1' THEN cnt := 0; FOR i IN 0 TO SecNum-1 LOOP IF (i /= TopSec) THEN IF Ers_Queue(i) = '1' AND Sec_Prot(i) = '0' THEN cnt := cnt +2; END IF; ELSE FOR y IN 0 TO SubSecNum-1 LOOP IF Ers_SubTop_Queue(y) = '1' AND SubSecTop_Prot(y) = '0' THEN cnt := cnt +1; END IF; END LOOP; END IF; END LOOP; IF cnt > 0 THEN elapsed := 0 ns; duration := cnt * seo/2; EDONE <= '0', '1' AFTER duration ; start := NOW; ELSE EERR <= '1', '0' AFTER 100 us; END IF; END IF; IF (rising_edge(ESUSP) OR rising_edge(ESTART_SUSP)) AND EDONE = '0' THEN elapsed := NOW - start; duration := duration - elapsed; EDONE <= '0'; ELSIF rising_edge(ERES) AND EDONE = '0' THEN start := NOW; EDONE <= '0', '1' AFTER duration; END IF; END IF; END PROCESS; ----------------------------------------------------------------------- -- Process that generate BURST control signals ----------------------------------------------------------------------- BurstControl : PROCESS (CLK, AVDNeg, CENeg, gCE_n, gWE_n, WENeg) VARIABLE burstClk_init : BOOLEAN := FALSE; BEGIN IF (AVDNeg = '0' AND rising_edge(CLK) AND burstClk_init = FALSE AND (CENeg = '0' OR gCE_n = '0') AND WENeg /= '0') THEN burstClk_init:= TRUE; Start_burst <= '1' , '0' AFTER 1 ns; Start_burst_tmp := TRUE; END IF; IF rising_edge(AVDNeg) THEN burstClk_init:= FALSE; END IF; IF (rising_edge(CENeg) AND gCE_n = '1') OR -- glitch start burst (rising_edge(gCE_n)) -- regular CE end OR falling_edge(gWE_n)THEN End_b <= '1' , '0' AFTER 1 ns; END IF; END PROCESS; ----------------------------------------------------------------------- -- Burst Control process ----------------------------------------------------------------------- ReadState : PROCESS (Start_burst ,End_b, End_b2, End_b3, reseted) VARIABLE end_burst : std_logic; BEGIN IF rising_edge(Start_burst) THEN BurstState <= BURST_READ; END IF; IF rising_edge(End_b) OR rising_edge(End_b2) OR rising_edge(End_b3) OR falling_edge(reseted) THEN BurstState <= IDLE_READ; END IF; END PROCESS; --------------------------------------------------------------------------- -- Main Behavior Process -- combinational process for next state generation --------------------------------------------------------------------------- StateGen :PROCESS(write, PDONE, EDONE, CTMOUT_out, ESTART_T1_out, reseted, READY_out, PERR, EERR) VARIABLE PATTERN_1 : boolean := FALSE; VARIABLE PATTERN_2 : boolean := FALSE; VARIABLE A_PAT_1 : boolean := FALSE; --DATA Low Byte VARIABLE DataLo : NATURAL RANGE 0 TO MaxData := 0; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(write) THEN DataLo := D_tmp0; PATTERN_1 := (Addr = 16#555#) AND (DataLo = 16#AA#) ; PATTERN_2 := (Addr = 16#2AA#) AND (DataLo = 16#55#) ; A_PAT_1 := ((Addr = 16#555#) AND (BankBypassLock(BA) = '0')) OR (BankBypassLock(BA) = '1'); END IF; IF reseted /= '1' THEN next_state <= current_state; ELSE CASE current_state IS WHEN RESET => IF falling_edge(write) THEN IF (PATTERN_1) THEN next_state <= Z001; ELSIF ((Addr = 16#55#) AND (DataLo = 16#98#)) THEN next_state <= CFI; ELSIF ((DataLo = 16#60#)) THEN next_state <= SEC_SECURITY_PRIOR2; ELSE next_state <= RESET; END IF; END IF; WHEN SEC_SECURITY_PRIOR2 => IF falling_edge(write) THEN IF (DataLo = 16#60#) THEN next_state <= SEC_SECURITY_PRIOR; ELSE IF to_nat(BankErase) = 0 THEN next_state <= RESET; ELSE next_state <= ESP; END IF; END IF; END IF; WHEN SEC_SECURITY_PRIOR => IF falling_edge(write) THEN IF (DataLo = 16#60#) THEN next_state <= SEC_SECURITY; ELSE IF to_nat(BankErase) = 0 THEN next_state <= RESET; ELSE next_state <= ESP; END IF; END IF; END IF; WHEN SEC_SECURITY => IF falling_edge(write) THEN IF (DataLo = 16#60#) THEN next_state <= SEC_SECURITY; ELSIF (DataLo = 16#F0#) THEN IF to_nat(BankErase) = 0 THEN next_state <= RESET; ELSE next_state <= ESP; END IF; END IF; END IF; WHEN Z001 => IF falling_edge(write) THEN IF (PATTERN_2) THEN next_state <= PREL_SETBWB; ELSE next_state <= RESET; END IF; END IF; WHEN PREL_SETBWB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#A0#)) THEN next_state <= A0SEEN; ELSIF (A_PAT_1 AND (DataLo = 16#20#)) THEN next_state <= PREL_ULBYPASS; ELSIF (A_PAT_1 AND (DataLo = 16#90#)) THEN next_state <= AS; ELSIF (A_PAT_1 AND (DataLo = 16#C0#)) THEN next_state <= RESET; ELSIF (A_PAT_1 AND (DataLo = 16#80#)) THEN next_state <= C8; ELSE next_state <= RESET; END IF; END IF; WHEN PREL_ULBYPASS => IF falling_edge(write) THEN IF (BankBypassLock(BA) = '1' AND (DataLo = 16#90#)) THEN next_state <= UNLOCK_RESET; ELSIF (DataLo = 16#A0#) THEN next_state <= A0SEEN; ELSIF (DataLo = 16#80#) THEN next_state <= C8_PREL; ELSE next_state <= PREL_ULBYPASS; END IF; END IF; WHEN UNLOCK_RESET => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN next_state <= RESET; ELSE next_state <= PREL_ULBYPASS; END IF; END IF; WHEN AS => IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN next_state <= RESET; ELSIF ((Addr = 16#55#) AND (DataLo = 16#98#)) THEN next_state <= AS_CFI; END IF; END IF; WHEN AS_CFI => IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN next_state <= AS; END IF; END IF; WHEN CFI => IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN next_state <= RESET; END IF; END IF; WHEN A0SEEN => IF falling_edge(write) THEN IF (BankBypassLock(BA) = '1' AND ULBYPASS = '1') OR ULBYPASS = '0' THEN next_state <= PGMS; ELSE next_state <= PREL_ULBYPASS; END IF; ELSE next_state <= A0SEEN; END IF; WHEN C8 => IF falling_edge(write) THEN IF PATTERN_1 THEN next_state <= C8_Z001; ELSE next_state <= RESET; END IF; END IF; WHEN C8_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= C8_PREL; ELSE next_state <= RESET; END IF; END IF; WHEN C8_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#10# THEN next_state <= ERS; ELSIF DataLo = 16#30# THEN IF ((BankBypassLock(BA)='1' AND ULBYPASS='1') OR ULBYPASS='0') THEN next_state <= SERS; ELSE next_state <= PREL_ULBYPASS; END IF; ELSE IF ULBYPASS = '0' THEN next_state <= RESET; ELSE next_state <= PREL_ULBYPASS; END IF; END IF; END IF; WHEN ERS => IF rising_edge(EDONE) OR falling_edge(EERR) THEN IF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; END IF; WHEN SERS => IF (CTMOUT_out = '1') THEN next_state <= SERS_EXEC; ELSIF falling_edge(write) THEN IF (DataLo = 16#B0#) THEN IF BankErase(BA) = '1' THEN next_state <= ESP; -- ESP according to datasheet ELSE next_state <= SERS; END IF; ELSIF (DataLo = 16#30#) THEN next_state <= SERS; ELSE IF ULBYPASS /= '1' THEN next_state <= RESET; ELSE next_state <= PREL_ULBYPASS; END IF; END IF; END IF; WHEN SERS_EXEC => IF rising_edge(EDONE) OR falling_edge(EERR) THEN IF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; ELSIF EERR /= '1' THEN IF falling_edge(write) THEN IF DataLo = 16#B0# AND BankErase(BA) = '1' THEN next_state <= ESPS; END IF; END IF; END IF; WHEN ESPS => IF (ESTART_T1_out = '1') THEN IF ULBYPASS = '1' THEN next_state <= ESP_ULBYPASS; ELSE next_state <= ESP; END IF; END IF; WHEN ESP => IF falling_edge(write) THEN IF DataLo = 16#30# AND BankErase(BA) = '1' THEN next_state <= SERS_EXEC; ELSIF ((DataLo = 16#60#)) THEN next_state <= SEC_SECURITY_PRIOR2; ELSE IF Addr = 16#55# AND DataLo = 16#98# THEN next_state <= ESP_CFI; ELSIF PATTERN_1 THEN next_state <= ESP_Z001; END IF; END IF; END IF; WHEN ESP_ULBYPASS => IF falling_edge(write) THEN IF DataLo = 16#30# AND BankErase(BA) = '1' THEN next_state <= SERS_EXEC; ELSIF (DataLo = 16#A0#) THEN next_state <= ESP_A0SEEN; ELSIF (BankBypassLock(BA) = '1' AND (DataLo = 16#90#)) THEN next_state <= ESP_UNLOCK_RESET; END IF; END IF; WHEN ESP_UNLOCK_RESET => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN next_state <= ESP; ELSE next_state <= ESP_ULBYPASS; END IF; END IF; WHEN ESP_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= ESP_SETBWB; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_SETBWB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#90#)) THEN next_state <= ESP_AS; ELSIF A_PAT_1 AND DataLo = 16#A0# THEN next_state <= ESP_A0SEEN; ELSIF (A_PAT_1 AND (DataLo = 16#20#)) THEN next_state <= ESP_ULBYPASS; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_AS => IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN next_state <= ESP; ELSIF ((Addr = 16#55#) AND (DataLo = 16#98#)) THEN next_state <= ESP_AS_CFI; ELSE next_state <= ESP_AS; END IF; END IF; WHEN ESP_CFI => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN next_state <= ESP; END IF; END IF; WHEN ESP_AS_CFI => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN next_state <= ESP_AS; ELSE next_state <= ESP_AS_CFI; END IF; END IF; WHEN ESP_A0SEEN => IF falling_edge(write) THEN IF (BankBypassLock(BA) = '1' AND ULBYPASS = '1') OR ULBYPASS = '0' THEN next_state <= PGMS; ELSE next_state <= ESP_ULBYPASS; END IF; END IF; WHEN PGMS => IF rising_edge(PDONE) OR falling_edge(PERR) THEN IF SERS_ACT = '1' THEN IF ULBYPASS = '0' THEN next_state <= ESP; ELSE next_state <= ESP_ULBYPASS; END IF; ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; END IF; END CASE; END IF; END PROCESS StateGen; WP_PROC: PROCESS(SecSecurity, PoweredUp, Vpp, WPNeg) VARIABLE Sec_ProtTmp : std_logic_vector(SecNum-1 DOWNTO 0) := (OTHERS => '1'); VARIABLE SubSecTop_ProtTmp : std_logic_vector(SubSecNum-1 DOWNTO 0) := (OTHERS => '1'); BEGIN IF PoweredUp = '0' THEN SubSecTop_Prot <= (OTHERS => '1'); Sec_Prot <= (OTHERS => '1'); END IF; IF reseted = '1' THEN IF rising_edge(SecSecurity) THEN IF (SA /= TopSec) THEN Sec_ProtTmp(SA) := NOT AddressLatch(SP_bit); ELSE SubSecTop_ProtTmp(SSA) := NOT AddressLatch(SP_bit); END IF; END IF; --Hardware Write Protection Sec_Prot <= Sec_ProtTmp; SubSecTop_Prot <= SubSecTop_ProtTmp; IF WPNeg = '0' THEN SubSecTop_Prot(SubSecNum-1 DOWNTO SubSecNum-2) <= (OTHERS => '1'); END IF; IF Vpp = '0' THEN SubSecTop_Prot <= (OTHERS => '1'); Sec_Prot <= (OTHERS => '1'); END IF; END IF; END PROCESS WP_PROC; --------------------------------------------------------------------------- --FSM Output generation and general funcionality --------------------------------------------------------------------------- Functional : PROCESS(write, read, AddressLatch, D_tmp0, CLK, PDONE, PERR, EDONE, ESTART_T1_out, CTMOUT_out, RST, reseted, READY_out, gOE_n, gCE_n, current_state, AVDNeg, Start_burst, End_b, OENeg, End_b2) PROCEDURE erase_activ_proc ( VARIABLE BA : IN NATURAL; VARIABLE SA : IN NATURAL; VARIABLE Address : IN NATURAL; VARIABLE erase_active : INOUT BOOLEAN; VARIABLE erase_suspend : INOUT BOOLEAN) IS BEGIN erase_active := FALSE; erase_suspend := FALSE; IF ASynchroMod = FALSE THEN SSA := Address / SubSecSize; END IF; IF (BankErase(BA) = '1' AND current_state = ERS) OR (BankErase(BA) = '1' AND current_state = SERS) OR (BankErase(BA) = '1' AND current_state = ESPS) OR (BankErase(BA) = '1' AND current_state = SERS_EXEC) THEN erase_active := TRUE; ELSIF BankErase(BA) = '1' THEN IF (SA /= TopSec AND Ers_Queue(SA) = '1' AND Sec_Prot(SA) = '0') OR (SA = TopSec AND Ers_SubTop_Queue(SSA) = '1' AND SubSecTop_Prot(SSA) = '0') THEN erase_suspend := TRUE; END IF; END IF; END PROCEDURE erase_activ_proc; PROCEDURE SetRdy ( VARIABLE wait_cycle : INOUT NATURAL) IS BEGIN RDY_tmp := '1'; IF wait_cycle /= 0 THEN RDY_tmp := '0'; END IF; END PROCEDURE SetRdy; PROCEDURE BurstInit( VARIABLE Wait_Cycle : INOUT NATURAL; VARIABLE WrapCnt : INOUT INTEGER; VARIABLE WrapMode : INOUT BURST_TYPE; VARIABLE BoundNoCross : INOUT BOOLEAN; VARIABLE BrEmbedded : OUT BOOLEAN; VARIABLE erase_active : INOUT BOOLEAN; VARIABLE erase_suspend : INOUT BOOLEAN; VARIABLE BrBoundCross : INOUT BOOLEAN) IS BEGIN BrEmbedded := FALSE; Start_burst_tmp := FALSE; BrBoundCross := FALSE; -- cross between little boundary Wait_Cycle := to_nat(BurstWait) + 1; RDY_tmp := '0'; -- if avd start burst rdy is 0 on firsr IF AddressLatch(0) = '1' THEN Wait_Cycle := Wait_Cycle +1; -- time reduce odd address END IF; BoundNoCross := FALSE; CASE BurstMode IS WHEN "000" | "100" => -- linear burst WrapCnt := -1; WrapMode := LINEAR; WHEN "001" => -- wrap 8 WrapCnt := 8 - to_nat(AddressLatch(2 DOWNTO 0)); WrapMode := WRAP_AROUND; WHEN "010" => -- wrap 16 WrapCnt := 16 - to_nat(AddressLatch(3 DOWNTO 0)); WrapMode := WRAP_AROUND; WHEN "011" => -- wrap 32 WrapCnt := 32 - to_nat(AddressLatch(4 DOWNTO 0)); WrapMode := WRAP_AROUND; WHEN "101" => -- wrap 8 WrapCnt := 8; WrapMode := WRAP_NO_AROUND; WHEN "110" => -- wrap 16 WrapCnt := 16; WrapMode := WRAP_NO_AROUND; WHEN "111" => -- wrap 32 WrapCnt := 32; WrapMode := WRAP_NO_AROUND; WHEN OTHERS => END CASE; IF WrapMode /= WRAP_AROUND THEN CASE (Address MOD BurstBound) IS WHEN 16#3E# => -- time reduce start with 3E address Wait_Cycle := Wait_Cycle +2; BoundNoCross := TRUE; WHEN 16#3F# => -- time reduce start with 3F address Wait_Cycle := Wait_Cycle +2; WHEN OTHERS => END CASE; END IF; erase_activ_proc(BA, SA, Address, erase_active, erase_suspend); IF ((BankBusy(BA) = '1' OR BankAutosel(BA) = '1' OR erase_active = TRUE OR erase_suspend = TRUE)) THEN BrEmbedded := TRUE; -- burst start in embaded bank END IF; END PROCEDURE BurstInit; PROCEDURE BurstCycle( VARIABLE Wait_Cycle : INOUT NATURAL; VARIABLE WrapCnt : INOUT INTEGER; VARIABLE WrapMode : INOUT BURST_TYPE; VARIABLE BoundNoCross : INOUT BOOLEAN; VARIABLE BrBoundCross : INOUT BOOLEAN; VARIABLE BrEmbedded : INOUT BOOLEAN; VARIABLE erase_active : INOUT BOOLEAN; VARIABLE erase_suspend : INOUT BOOLEAN ) IS BEGIN IF rising_edge(CLK) AND NOT Start_burst_tmp THEN IF Wait_Cycle = 0 THEN IF WrapMode /= LINEAR THEN WrapCnt := WrapCnt - 1; END IF; IF WrapCnt > 0 AND WrapMode = WRAP_AROUND THEN Address := Address +1; ELSIF WrapCnt = 0 AND WrapMode = WRAP_AROUND THEN CASE BurstMode IS WHEN "001" => -- wrap 8 Address := Address - 8 +1; WrapCnt := 8; WHEN "010" => -- wrap 16 Address := Address - 16 +1; WrapCnt := 16; WHEN "011" => -- wrap 32 Address := Address - 32 +1; WrapCnt := 32; WHEN OTHERS => END CASE; ELSE -- liner mode Address := Address + 1; IF WrapCnt = 0 THEN -- end wrap not around End_b2 <= '1' , '0' AFTER 1 ns; Address := Address -1; RDY_tmp := '0'; Wait_Cycle := 1; END IF; IF Address = SecSize THEN -- calculate BA and SA SA := SA + 1; Address:= 0; IF (SA MOD SecNumBank = 0) THEN BA := ((BA + 1) MOD BankNum); IF SA = SecNum THEN SA := 0; END IF; END IF; END IF; IF (Address mod BurstBound = BurstBound - 1) THEN -- cross bound IF (BoundNoCross = FALSE) THEN Wait_Cycle := 2; BrBoundCross := TRUE; ELSE BoundNoCross := FALSE; END IF; END IF; erase_activ_proc(BA, SA, Address, erase_active, erase_suspend); IF (BankBusy(BA) = '1' OR BankAutosel(BA) = '1' OR erase_active = TRUE OR erase_suspend = TRUE ) THEN -- enter embaded End_b2 <= '1' , '0' AFTER 1 ns; BoundNoCross := FALSE; Wait_Cycle:= 5; RDY_tmp := '0'; END IF; END IF; ELSE Wait_Cycle:= Wait_Cycle-1; RDY_tmp := '0'; END IF; IF wait_cycle = 0 OR BrBoundCross = TRUE THEN SetRdy(wait_cycle); BrBoundCross := FALSE; END IF; ELSIF rising_edge(Start_burst) THEN BurstInit( Wait_Cycle,WrapCnt, WrapMode, BoundNoCross, BrEmbedded, erase_active, erase_suspend, BrBoundCross); END IF; END PROCEDURE BurstCycle; PROCEDURE SetBurstParam( VARIABLE Wait_Cycle : INOUT NATURAL; VARIABLE WrapCnt : INOUT INTEGER; VARIABLE WrapMode : INOUT BURST_TYPE; VARIABLE BoundNoCross : INOUT BOOLEAN; VARIABLE BrBoundCross : INOUT BOOLEAN; VARIABLE BrEmbedded : INOUT BOOLEAN; VARIABLE erase_active : INOUT BOOLEAN; VARIABLE erase_suspend : INOUT BOOLEAN ) IS BEGIN IF ASynchroMod = FALSE THEN CASE BurstState IS WHEN IDLE_READ => IF rising_edge(Start_burst) THEN BurstInit( Wait_Cycle, WrapCnt, WrapMode, BoundNoCross, BrEmbedded, erase_active, erase_suspend, BrBoundCross); ELSIF rising_edge(End_b) THEN RDY_tmp := '0'; END IF; WHEN BURST_READ => BurstCycle( Wait_Cycle, WrapCnt, WrapMode, BoundNoCross, BrBoundCross, BrEmbedded, erase_active, erase_suspend); IF rising_edge(End_b) THEN RDY_tmp := '0'; END IF; END CASE; END IF; END PROCEDURE SetBurstParam; PROCEDURE DriveOut IS BEGIN IF Mem(SA)(Address) = -1 THEN DOut_zd(15 DOWNTO 0) <= (OTHERS => 'X'); ELSE DOut_zd(15 DOWNTO 0) <= to_slv(Mem(SA)(Address),16); END IF; END PROCEDURE DriveOut; -- PROCEDURE FOR READ AUTOSELECT SECTOR PROCEDURE Read_autoselect IS VARIABLE AutoselAddress : NATURAL; VARIABLE AutoselData : std_logic_vector(15 DOWNTO 0); BEGIN AutoselAddress := Address MOD 16#100#; IF ASynchroMod = FALSE THEN SSA := Address / SubSecSize; END IF; IF AutoselAddress = 0 THEN AutoselData := to_slv(1,16); ELSIF AutoselAddress = 1 THEN AutoselData := to_slv(16#007E#,16); ELSIF AutoselAddress = 2 THEN IF (((SA /= TopSec) AND (Sec_Prot(SA) = '0')) OR ((SA = TopSec) AND (SubSecTop_Prot(SSA) = '0'))) THEN AutoselData := to_slv(16#0000#,16); ELSE AutoselData := to_slv(16#0001#,16); END IF; ELSIF AutoselAddress = 3 THEN IF TimingModel(16) = '0' THEN AutoselData := to_slv(16#712E#,16); ELSIF TimingModel(16) = '2' THEN AutoselData := to_slv(16#712C#,16); ELSIF TimingModel(13) = 'A' THEN AutoselData := to_slv(16#711E#,16); ELSIF TimingModel(13) = 'F' THEN AutoselData := to_slv(16#711D#,16); END IF; ELSIF AutoselAddress = 14 THEN AutoselData := to_slv(16#0016#,16); ELSIF AutoselAddress = 15 THEN AutoselData := to_slv(16#0000#,16); ELSE AutoselData := (OTHERS =>'Z'); END IF; DOut_zd <= AutoselData; END PROCEDURE Read_autoselect; -- procedure for read from memory when erase embaded algoritam is suspend PROCEDURE Readmem_EraseSuspend( VARIABLE Status : INOUT std_logic_vector(7 DOWNTO 0) ) IS VARIABLE read_nosuspend_sect : BOOLEAN := TRUE; BEGIN IF ASynchroMod = FALSE THEN SSA := Address / SubSecSize; END IF; read_nosuspend_sect := TRUE; IF (SA /= TopSec) THEN IF Ers_Queue(SA) = '1' AND Sec_Prot(SA) = '0' THEN read_nosuspend_sect := FALSE; END IF; ELSE IF Ers_SubTop_Queue(SSA) = '1' AND SubSecTop_Prot(SSA) = '0' THEN read_nosuspend_sect := FALSE; END IF; END IF; IF read_nosuspend_sect = TRUE THEN DriveOut; ELSE ----------------------------------------------------------- --read status / erase suspend timeout - stil erasing ----------------------------------------------------------- Status(7) := '1'; -- Status(6) No toggle Status(5) := '0'; Status(2) := NOT Status(2); --toggle DOut_zd(7 DOWNTO 0) <= Status; DOut_zd(15 DOWNTO 8) <= (OTHERS => 'Z'); END IF; END PROCEDURE Readmem_EraseSuspend; PROCEDURE Read_EraseStatus ( VARIABLE Status : INOUT std_logic_vector(7 DOWNTO 0)) IS BEGIN IF ASynchroMod = FALSE THEN SSA := Address / SubSecSize; END IF; Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; IF NOW - ERASE_START > 100 us THEN IF (SA /= TopSec AND Ers_Queue(SA) = '1' AND Sec_Prot(SA) = '0') OR (SA = TopSec AND Ers_SubTop_Queue(SSA) = '1' AND SubSecTop_Prot(SSA) = '0') THEN Status(2) := NOT Status(2); --toggle END IF; ELSE IF (SA /= TopSec AND Ers_Queue(SA) = '1') OR (SA = TopSec AND Ers_SubTop_Queue(SSA) = '1') THEN Status(2) := NOT Status(2); --toggle END IF; END IF; END PROCEDURE Read_EraseStatus; --Common Flash Interface Query codes TYPE CFItype IS ARRAY (16#10# TO 16#5C#) OF INTEGER RANGE -1 TO 16#FF#; VARIABLE CFI_array : CFItype := (OTHERS => -1); VARIABLE WRData : INTEGER := 0; VARIABLE Mem_tmp : INTEGER := 0; VARIABLE WRSA : NATURAL := 0; VARIABLE WRAddress : NATURAL := 0; VARIABLE A_PAT_1 : boolean := FALSE; VARIABLE oe : boolean := FALSE; --Status reg. VARIABLE Status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); --DATA Full VARIABLE Data : NATURAL Range 0 TO MaxData := 0; --DATA Low Byte VARIABLE DataLo : NATURAL RANGE 0 TO MaxData := 0; VARIABLE temp : std_logic_vector(7 DOWNTO 0); VARIABLE read_nosuspend_sect : BOOLEAN; VARIABLE i_bank : NATURAL; VARIABLE i_sec : NATURAL; VARIABLE i_sub : NATURAL; VARIABLE new_data : std_logic_vector(15 DOWNTO 0); VARIABLE old_data : std_logic_vector(15 DOWNTO 0); VARIABLE data_mem : natural; VARIABLE Wait_Cycle : NATURAL; VARIABLE WrapCnt : INTEGER; VARIABLE WrapMode : BURST_TYPE; VARIABLE BoundNoCross : BOOLEAN := FALSE; VARIABLE BrBoundCross : BOOLEAN; VARIABLE BrEmbedded : BOOLEAN; VARIABLE erase_active : BOOLEAN; VARIABLE erase_suspend : BOOLEAN; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(write) THEN DataLo := D_tmp0; Data := D_tmp; A_PAT_1 := ((Addr = 16#555#) AND (BankBypassLock(BA) = '0')) OR (BankBypassLock(BA) = '1'); END IF; oe := (rising_edge(read) OR (read = '1' AND (AddressLatch'EVENT)) OR (read = '1' AND ASynchroMod = FALSE AND AVDNeg = '1' AND rising_edge(CLK) AND BurstState /= IDLE_READ)); SetBurstParam(Wait_Cycle, WrapCnt, WrapMode, BoundNoCross, BrBoundCross, BrEmbedded, erase_active, erase_suspend); IF reseted = '1' THEN CASE current_state IS WHEN RESET => ULBYPASS <= '0'; BankErase <= (OTHERS => '0'); BankEraseExec := (OTHERS => '0'); BankBypassLock <= (OTHERS => '0'); BankAutosel := (OTHERS => '0'); BankBusy := (OTHERS => '0'); Ers_Queue <= (OTHERS => '0'); Ers_SubTop_Queue <= (OTHERS => '0'); SERS_ACT <= '0'; PGMS_ACT <= '0'; CTMOUT_in <= '0'; IF falling_edge(write) THEN NULL; ELSIF oe THEN DriveOut; END IF; WHEN SEC_SECURITY_PRIOR2 => WHEN SEC_SECURITY_PRIOR => IF falling_edge(write) THEN IF (DataLo = 16#60#) THEN ASSERT FALSE REPORT "Third(last) cycle for Sector lock/unlock OK" SEVERITY note; IF NOT((SA /= TopSec AND Ers_Queue(SA) = '1') OR (SA = TopSec AND Ers_SubTop_Queue(SSA) = '1')) THEN SecSecurity <= '1', '0' AFTER 1 ns; END IF; END IF; END IF; WHEN SEC_SECURITY => IF falling_edge(write) THEN IF (DataLo = 16#60#) THEN ASSERT FALSE REPORT "Third(last) cycle for Sector lock/unlock OK" SEVERITY note; IF NOT((SA /= TopSec AND Ers_Queue(SA) = '1') OR (SA = TopSec AND Ers_SubTop_Queue(SSA) = '1')) THEN SecSecurity <= '1', '0' AFTER 1 ns; END IF; END IF; END IF; WHEN Z001 => null; WHEN PREL_SETBWB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#20#)) THEN BankBypassLock(BA) <= '1'; ELSIF (A_PAT_1 AND (DataLo = 16#90#)) THEN --autoselect mode BankAutosel(BA) := '1'; ELSIF (A_PAT_1 AND (DataLo = 16#C0#)) THEN BurstModeReg <= AddressLatch(HighCommand_bit DOWNTO LowCommand_bit); END IF; END IF; WHEN AS => IF oe THEN IF BankAutosel(BA) = '1' THEN Read_autoselect; ELSE DriveOut; END IF; END IF; IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN --remove autoselect mode bank BankAutosel := (OTHERS => '0'); END IF; END IF; WHEN PREL_ULBYPASS => ULBYPASS <= '1'; IF oe THEN IF BankBypassLock(BA) = '1' THEN Dout_zd <= (OTHERS => 'Z') ; ELSE DriveOut; END IF; END IF; WHEN UNLOCK_RESET | ESP_UNLOCK_RESET => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN BankBypassLock <= (OTHERS => '0'); ULBYPASS <= '0'; END IF; END IF; WHEN CFI | AS_CFI | ESP_CFI | ESP_AS_CFI => BankBusy := (OTHERS => '1'); IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN BankBusy := (OTHERS => '0'); END IF; ELSIF oe THEN DOut_zd(15 DOWNTO 0) <= (OTHERS => '0'); IF ((to_nat(AddressLatch) >= 16#10#) AND (to_nat(AddressLatch) <= 16#5C#)) THEN IF (CFI_array(to_nat(AddressLatch)) /= -1) THEN DOut_zd(7 DOWNTO 0) <= to_slv(CFI_array(to_nat(AddressLatch)),8); ELSE DOut_zd <= (OTHERS =>'Z'); END IF; ELSE ASSERT FALSE REPORT "Invalid CFI query address" SEVERITY warning; DOut_zd <= (OTHERS =>'Z'); END IF; END IF; WHEN A0SEEN | ESP_A0SEEN => IF falling_edge(write) THEN IF (BankBypassLock(BA) = '1' AND ULBYPASS = '1') OR ULBYPASS = '0' THEN IF (SA /= TopSec AND Sec_Prot(SA) = '0' AND Ers_Queue(SA) = '0') OR (SA = TopSec AND SubSecTop_Prot(SSA) = '0' AND Ers_SubTop_Queue(SSA) = '0') THEN PSTART <= '1', '0' AFTER 1 ns; WRData := Data; WRSA := SA; WRAddress := Address; Mem_tmp := Mem(WRSA)(WRAddress); Mem(WRSA)(WRAddress) := -1; temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); BankBusy := (OTHERS => '0'); BankBusy(BA) := '1'; ELSE temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); BankBusy := (OTHERS => '0'); BankBusy(BA) := '1'; PSTART <= '1', '0' AFTER 1 ns; END IF; END IF; END IF; WHEN PGMS => PGMS_ACT <= '1'; IF oe THEN IF BankBusy(BA) = '1' THEN ----------------------------------------------------------- --read status ----------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; DOut_zd(7 DOWNTO 0) <= Status; DOut_zd(15 DOWNTO 8) <= (OTHERS => 'Z'); ELSE -- read from non program bank!!!!!!!!!!!!!!!!! Readmem_EraseSuspend(Status); END IF; END IF; IF falling_edge(PERR) THEN BankBusy := (OTHERS => '0'); PGMS_ACT <= '0'; END IF; IF PERR /= '1' THEN IF rising_edge(PDONE) AND (NOT PERR'EVENT) THEN PGMS_ACT <= '0'; IF Mem_tmp /= -1 AND WRData /= -1 THEN new_data := to_slv(WRData,16); old_data := to_slv(Mem_tmp,16); data_mem := to_nat(new_data AND old_data); Mem(WRSA)(WRAddress) := data_mem; Mem_tmp := Mem(WRSA)(WRAddress); BankBusy := (OTHERS => '0'); ELSE Mem(WRSA)(WRAddress) := WRData; BankBusy := (OTHERS => '0'); END IF; END IF; END IF; WHEN C8 => IF falling_edge(write) THEN null; END IF; WHEN C8_Z001 => IF falling_edge(write) THEN null; END IF; WHEN C8_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#10# THEN ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; Ers_Queue <= (OTHERS => '1'); Ers_SubTop_Queue <= (OTHERS => '1'); Status := "00001000"; BankErase <= (OTHERS => '1'); SERS_ACT <= '1'; ERASE_START := NOW; ELSIF DataLo = 16#30# THEN --put selected sector to sec. ers. queue --start timeout IF (BankBypassLock(BA) = '1' AND ULBYPASS = '1') OR ULBYPASS = '0' THEN Ers_Queue <= (OTHERS => '0'); Ers_SubTop_Queue <= (OTHERS => '0'); IF (SA = TopSec) THEN Ers_SubTop_Queue(SSA) <= '1'; ELSE Ers_Queue(SA) <= '1'; END IF; BankErase(BA)<= '1'; IF (SA /= TopSec AND Sec_Prot(SA) = '0') THEN BankEraseExec(BA) := '1'; ELSIF (SA = TopSec) AND SubSecTop_Prot(SSA) = '0' THEN BankEraseExec(BA) := '1'; END IF; CTMOUT_in <= '1'; SERS_ACT <= '1'; END IF; END IF; END IF; WHEN ERS => IF oe THEN Read_EraseStatus(Status); DOut_zd(7 DOWNTO 0) <= Status; DOut_zd(15 DOWNTO 8) <= (OTHERS => 'Z'); END IF; IF EERR /= '1' THEN IF NOT CLK'EVENT THEN FOR i IN 0 TO SecNum -1 LOOP IF i /= TopSec THEN IF Sec_Prot(i) = '0' THEN Mem(i) := (OTHERS => -1); END IF; ELSE FOR y IN 0 TO SubSecNum -1 LOOP IF SubSecTop_Prot(y) = '0' THEN Mem(TopSec)(sssa(y) TO ssea(y)) := (OTHERS => -1); END IF; END LOOP; END IF; END LOOP; END IF; IF EDONE = '1' THEN FOR i IN 0 TO SecNum -1 LOOP IF i/= TopSec THEN IF Sec_Prot(i) = '0' THEN Mem(i) := (OTHERS => MaxData); END IF; ELSE FOR y IN 0 TO SubSecNum -1 LOOP IF SubSecTop_Prot(y) = '0' THEN Mem(TopSec)(sssa(y) TO ssea(y)) := (OTHERS => MaxData); END IF; END LOOP; END IF; Ers_Queue <= (OTHERS => '0'); Ers_SubTop_Queue <= (OTHERS => '0'); END LOOP; END IF; END IF; WHEN SERS => IF (CTMOUT_out = '1') THEN CTMOUT_in <= '0'; ESTART_T1_in <= '0'; ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; FOR i IN 0 TO BankNum -1 LOOP IF BankEraseExec(i) = '0' AND BankErase(i) = '1' THEN BankErase(i) <= '0' AFTER 100 us; END IF; END LOOP; ERASE_START := NOW; ELSIF falling_edge(write) THEN IF (DataLo = 16#B0#) THEN --need to start erase process prior to suspend IF BankErase(BA) = '1' THEN ESTART_SUSP <= '1', '0' AFTER 1 ns; CTMOUT_in <= '0'; ERES <= '0'; END IF; ELSIF (DataLo = 16#30#) THEN CTMOUT_in <= '0', '1' AFTER 1 NS; IF (SA = TopSec) THEN Ers_SubTop_Queue(SSA) <= '1'; ELSE Ers_Queue(SA) <= '1'; END IF; BankErase(BA)<= '1'; IF (SA /= TopSec) AND Sec_Prot(SA) = '0' THEN BankEraseExec(BA) := '1'; ELSIF (SA = TopSec) AND SubSecTop_Prot(SSA) = '0' THEN BankEraseExec(BA) := '1'; END IF; ELSE CTMOUT_in <= '0'; Ers_Queue <= (OTHERS => '0'); Ers_SubTop_Queue <= (OTHERS => '0'); END IF; ELSIF oe THEN IF BankErase(BA) = '1' THEN ---------------------------------------------------------- --read status - sector erase timeout ---------------------------------------------------------- Status(3) := '0'; DOut_zd(7 DOWNTO 0) <= Status; DOut_zd(15 DOWNTO 8) <= (OTHERS => 'Z'); ELSE DriveOut; END IF; END IF; WHEN ESPS => IF (ESTART_T1_out = '1') THEN ESTART_T1_in <= '0'; ELSIF oe THEN IF BankErase(BA) = '1' THEN ---------------------------------------------------------- --read status / erase suspend timeout - stil erasing ---------------------------------------------------------- Read_EraseStatus(Status); DOut_zd(7 DOWNTO 0) <= Status; DOut_zd(15 DOWNTO 8) <= (OTHERS => 'Z'); ELSE DriveOut; END IF; END IF; WHEN SERS_EXEC => IF oe THEN IF BankErase(BA) = '1' THEN ----------------------------------------------------------- --read status Erase Busy ----------------------------------------------------------- Read_EraseStatus(Status); DOut_zd(7 DOWNTO 0) <= Status; DOut_zd(15 DOWNTO 8) <= (OTHERS => 'Z'); ELSE DriveOut; END IF; END IF; IF EERR /= '1' THEN IF EDONE /= '1' THEN IF NOT CLK'EVENT THEN FOR i IN 0 TO SecNum -1 LOOP IF i /= TopSec THEN IF Sec_Prot(i) = '0' AND Ers_Queue(i) = '1' THEN Mem(i) := (OTHERS => -1); END IF; ELSE FOR y IN 0 TO SubSecNum -1 LOOP IF SubSecTop_Prot(y) = '0' AND Ers_SubTop_Queue(y) = '1' THEN Mem(TopSec)(sssa(y) TO ssea(y)) := (OTHERS => -1); END IF; END LOOP; END IF; END LOOP; END IF; ELSE FOR i IN 0 TO SecNum-1 LOOP IF i/= TopSec THEN IF Sec_Prot(i) = '0' AND Ers_Queue(i) = '1' THEN Mem(i) := (OTHERS => MaxData); END IF; ELSE FOR y IN 0 TO SubSecNum -1 LOOP IF SubSecTop_Prot(y) = '0' AND Ers_Subtop_Queue(y) = '1' THEN Mem(TopSec)(sssa(y) TO ssea(y)) := (OTHERS => MaxData); END IF; END LOOP; END IF; END LOOP; END IF; IF falling_edge(write) THEN IF DataLo = 16#B0# AND BankErase(BA) = '1' THEN ESTART_T1_in <= '1'; ESUSP <= '1', '0' AFTER 1 ns; END IF; END IF; END IF; WHEN ESP => IF falling_edge(write) THEN IF DataLo = 16#30# AND BankErase(BA) = '1' THEN ERES <= '1', '0' AFTER 1 ns; END IF; ELSIF oe THEN ----------------------------------------------------------- --read memory ----------------------------------------------------------- Readmem_EraseSuspend(Status); END IF; WHEN ESP_Z001 => null; WHEN ESP_SETBWB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#20#)) THEN BankBypassLock(BA) <= '1'; ELSIF (A_PAT_1 AND (DataLo = 16#90#)) THEN --autoselect mode BankAutosel(BA) := '1'; ELSIF (A_PAT_1 AND (DataLo = 16#C0#)) THEN BurstModeReg <= AddressLatch(HighCommand_bit DOWNTO LowCommand_bit); END IF; END IF; WHEN ESP_ULBYPASS => ULBYPASS <= '1'; IF falling_edge(write) THEN IF DataLo = 16#30# AND BankErase(BA) = '1' THEN ERES <= '1', '0' AFTER 1 ns; END IF; ELSIF oe THEN ----------------------------------------------------------- --read memory ----------------------------------------------------------- Readmem_EraseSuspend(Status); END IF; WHEN ESP_AS => IF oe THEN IF BankAutosel(BA) = '1' THEN Read_autoselect; ELSE ----------------------------------------------------------- --read memory ----------------------------------------------------------- Readmem_EraseSuspend(Status); END IF; END IF; IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN --remove autoselect mode bank BankAutosel := (OTHERS => '0'); END IF; END IF; END CASE; ELSE Ers_Queue <= (OTHERS => '0'); Ers_SubTop_Queue <= (OTHERS => '0'); BurstModeReg <= ComandBurstInit; END IF; --Output Disable Control IF (gOE_n = '1' OR gCE_n = '1') OR (RESETNeg = '0'AND RST = '0') THEN DOut_zd <= (OTHERS => 'Z'); END IF; IF rising_edge(read) AND reseted = '1' THEN clk_oe_en <= '1' AFTER 1 ns; ELSIF falling_edge(read) OR reseted = '0' THEN clk_oe_en <= '0'; END IF; IF (gOE_n = '1' OR gCE_n = '1') OR (RESETNeg = '0'AND RST = '0') THEN RDY_zd <= 'Z'; IF (OENeg = '0' AND gCE_n = '0') AND ASynchroMod = FALSE AND NOT (RESETNeg = '0' AND RST = '0') THEN RDY_zd <= RDY_tmp; END IF; ELSE IF CLK = '1'AND ASynchroMod = FALSE THEN RDY_zd <= RDY_tmp; END IF; END IF; --Preload Control ----------------------------------------------------------------------- -- File read Section ----------------------------------------------------------------------- IF NOW = 0 ns THEN ----------------------------------------------------------------------- --CFI array data ----------------------------------------------------------------------- --CFI query identification string CFI_array(16#10#) := 16#51#; CFI_array(16#11#) := 16#52#; CFI_array(16#12#) := 16#59#; CFI_array(16#13#) := 16#02#; CFI_array(16#14#) := 16#00#; CFI_array(16#15#) := 16#40#; CFI_array(16#16#) := 16#00#; CFI_array(16#17#) := 16#00#; CFI_array(16#18#) := 16#00#; CFI_array(16#19#) := 16#00#; CFI_array(16#1A#) := 16#00#; --system interface string CFI_array(16#1B#) := 16#17#; CFI_array(16#1C#) := 16#19#; CFI_array(16#1D#) := 16#00#; CFI_array(16#1E#) := 16#00#; CFI_array(16#1F#) := 16#03#; CFI_array(16#20#) := 16#00#; CFI_array(16#21#) := 16#09#; CFI_array(16#22#) := 16#00#; CFI_array(16#23#) := 16#05#; CFI_array(16#24#) := 16#00#; CFI_array(16#25#) := 16#04#; CFI_array(16#26#) := 16#00#; --device geometry definition CFI_array(16#27#) := 16#18#; CFI_array(16#28#) := 16#01#; CFI_array(16#29#) := 16#00#; CFI_array(16#2A#) := 16#00#; CFI_array(16#2B#) := 16#00#; CFI_array(16#2C#) := 16#02#; CFI_array(16#2D#) := 16#FE#; CFI_array(16#2E#) := 16#00#; CFI_array(16#2F#) := 16#00#; CFI_array(16#30#) := 16#01#; CFI_array(16#31#) := 16#03#; CFI_array(16#32#) := 16#00#; CFI_array(16#33#) := 16#40#; CFI_array(16#34#) := 16#00#; CFI_array(16#35#) := 16#00#; CFI_array(16#36#) := 16#00#; CFI_array(16#37#) := 16#00#; CFI_array(16#38#) := 16#00#; CFI_array(16#39#) := 16#00#; CFI_array(16#3A#) := 16#00#; CFI_array(16#3B#) := 16#00#; CFI_array(16#3C#) := 16#00#; --primary vendor-specific extended query CFI_array(16#40#) := 16#50#; CFI_array(16#41#) := 16#52#; CFI_array(16#42#) := 16#49#; CFI_array(16#43#) := 16#31#; CFI_array(16#44#) := 16#33#; CFI_array(16#45#) := 16#00#; CFI_array(16#46#) := 16#02#; CFI_array(16#47#) := 16#01#; CFI_array(16#48#) := 16#00#; CFI_array(16#49#) := 16#05#; CFI_array(16#4A#) := 16#C0#; CFI_array(16#4B#) := 16#01#; CFI_array(16#4C#) := 16#00#; CFI_array(16#4D#) := 16#B5#; CFI_array(16#4E#) := 16#C5#; CFI_array(16#4F#) := 16#03#; CFI_array(16#50#) := 16#00#; CFI_array(16#57#) := 16#04#; CFI_array(16#58#) := 16#40#; CFI_array(16#59#) := 16#40#; CFI_array(16#5A#) := 16#40#; CFI_array(16#5B#) := 16#43#; CFI_array(16#5C#) := 16#02#; END IF; END PROCESS Functional; --------------------------------------------------------------------------- ---- File read Section - Preload Control --------------------------------------------------------------------------- MemPreload : PROCESS -- text file input variables FILE mem_f : text is flash_file_name; VARIABLE addr_ind : NATURAL; VARIABLE sec_ind : NATURAL; VARIABLE offset : NATURAL; VARIABLE ind : NATURAL; VARIABLE buf : line; VARIABLE sect : NATURAL; VARIABLE report_err : BOOLEAN := FALSE; BEGIN ----------------------------------------------------------------------- --s71ns128ja0 memory preload file format ----------------------------------------------------------------------- -- / - comment -- @aaaaaa - stands for address -- dddd - is word to be written at Mem(aaaaaa++) -- (aaaaaa is incremented at every load) -- only first 1-7 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ----------------------------------------------------------------------- IF UserPreload AND (flash_file_name /= "none" ) THEN addr_ind := 0; WHILE (not ENDFILE (mem_f)) LOOP READLINE (mem_f, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN addr_ind := h(buf(2 to 7)); sec_ind := addr_ind / SecSize; offset := addr_ind - (sec_ind * SecSize); ELSE IF addr_ind <= MemSize THEN Mem(sec_ind)(offset):= h(buf(1 to 4)); addr_ind := (addr_ind + 1); sec_ind := addr_ind / SecSize; offset := addr_ind - (sec_ind * SecSize); ELSE IF report_err = FALSE THEN REPORT "Memory file:" & flash_file_name & " Address range overflow" SEVERITY warning; report_err := TRUE; END IF; END IF; END IF; END LOOP; END IF; WAIT; END PROCESS; ----------------------------------------------------------------------- -- Path Delay Section ----------------------------------------------------------------------- DOutPassThrough : PROCESS(DOut_zd) VARIABLE tOD : time := 0 ns; VARIABLE tCD : time := 0 ns; VARIABLE tAD : time := 0 ns; BEGIN IF DOut_zd(0) /= 'Z' THEN IF ASynchroMod = TRUE THEN tpd_from_OE := FALSE; tpd_from_CE := FALSE; Open3state := TRUE; tOD := -OENeg'LAST_EVENT + tpd_OENeg_DQ0(trz1); tCD := -CENeg'LAST_EVENT + tpd_CENeg_DQ0(trz1); tAD := -AddressLatch'LAST_EVENT + tpd_A16_DQ0_asynchro_eq_1(tr10); IF tOD >= tCD AND tOD > 0 ns THEN tpd_from_OE := TRUE; ELSIF tCD >= tOD AND tCD > 0 ns THEN tpd_from_CE := TRUE; END IF; IF tAD > 0 ns AND ((tAD >= tOD AND tpd_from_OE = TRUE) OR (tAD >= tCD AND tpd_from_CE = TRUE)) THEN Dout_pass <= "XXXXXXXXXXXXXXXX", Dout_zd AFTER tAD; ELSE Dout_pass <= Dout_zd; END IF; ELSE tAD := -Start_burst'LAST_EVENT -1 ns + tpd_A16_DQ0_asynchro_eq_0(tr10); IF tAD > 0 ns THEN Dout_pass <= "XXXXXXXXXXXXXXXX", Dout_zd AFTER tAD; clk_addr_en <= '0' AFTER 1 ns, '1' AFTER tAD + 1 ns ; ELSIF End_b2 = '1' THEN Dout_pass <= Dout_zd AFTER tpd_A16_DQ0_asynchro_eq_0(tr10); ELSE Dout_pass <= Dout_zd; END IF; END IF; ELSE tCD := -CENeg'LAST_EVENT + tpd_CENeg_DQ0(tr0z); tOD := -OENeg'LAST_EVENT + tpd_OENeg_DQ0(tr0z); tpd_from_OE := (tOD <= tCD) AND (tOD > 0 ns); tpd_from_CE := (tCD < tOD) AND (tCD > 0 ns); IF tpd_from_CE = TRUE THEN tpd_from_OE := FALSE; ELSIF tpd_from_OE = TRUE THEN tpd_from_CE := FALSE; ELSE tpd_from_OE := TRUE; tpd_from_CE := TRUE; END IF; Open3state := FALSE; DOut_Pass <= DOut_zd; END IF; END PROCESS DOutPassThrough; RDYPassThrough : PROCESS(RDY_zd) VARIABLE tAD : time := 0 ns; BEGIN IF RDY_zd /= 'Z' THEN PathDisable := TRUE; IF BankBusy(BA) = '1' OR BankAutosel(BA) = '1' OR (BankErase(BA) = '1' AND (current_state = SERS_EXEC OR current_state = ERS)) OR (SA = TopSec AND SubSecTop_Prot(SSA) = '0' AND Ers_SubTop_Queue(SSA) = '1') OR (SA /= TopSec AND Sec_Prot(SA) = '0' AND Ers_Queue(SA) = '1') THEN PathDisable := FALSE; End_b3 <= '1', '0' AFTER 1 ns; IF End_b2 /= '1' THEN tAD := -Start_burst'LAST_EVENT -1 ns + tpd_A16_DQ0_asynchro_eq_0(tr10); IF tAD > 0 ns THEN RDY_pass <= '0', '1' AFTER tAD; ELSE RDY_pass <= '1'; END IF; ELSE tAD := tpd_A16_DQ0_asynchro_eq_0(tr10); RDY_pass <= '0' AFTER tpd_CLK_RDY(tr10), '1' AFTER tAD; END IF; ELSE RDY_pass <= RDY_zd; END IF; ELSE RDY_pass <= RDY_zd; END IF; END PROCESS RDYPassThrough; RDY_OUT: PROCESS(RDY_pass) VARIABLE RDY_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => RDY_s, OutSignalName => "RDY", OutTemp => RDY_pass, Mode => VitalTransport, GlitchData => RDY_GlitchData, Paths => ( 0 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_RDY, PathCondition => TRUE), 1 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_RDY, PathCondition => OENeg = '0'), 2 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CLK_RDY), PathCondition => OENEg = '0' AND CENeg = '0' AND ASynchroMod = FALSE AND PathDisable)) ); END PROCESS RDY_Out; RDY <= RDY_s; --------------------------------------------------------------------------- -- Path Delay Section for DOut signal --------------------------------------------------------------------------- D_Out_PathDelay_Gen : FOR i IN 0 TO 15 GENERATE --Dout_zd'RANGE GENERATE PROCESS(DOut_pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; VARIABLE OE :boolean := false; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_pass(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ0, PathCondition => tpd_from_OE), 1 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_DQ0, PathCondition => tpd_from_CE), 2 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CLK_DQ0), PathCondition => CENeg = '0' AND OENeg = '0' AND ASynchroMod = FALSE AND clk_addr_en = '1' AND PathDisable AND clk_oe_en = '1') ) ); END PROCESS; END GENERATE D_Out_PathDelay_Gen; END BLOCK behavior; END vhdl_behavioral_flash; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.all; USE FMF.conversions.all; ------------------------------------------------------------------------------- -- ENTITY DECLARATION FOR pSRAM_16 MODULE ------------------------------------------------------------------------------- ENTITY pSRAM_16 IS GENERIC ( tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_A18 : VitalDelayType01 := VitalZeroDelay01; tipd_A19 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_UBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_AVDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; --tpd delays for SRAM tpd_OENeg_DQ0 : VitalDelayType01ZX := UnitDelay01ZX; tpd_A16_DQ0 : VitalDelayType01 := UnitDelay01;--tVpp tpd_CSNeg_DQ0 : VitalDelayType01ZX := UnitDelay01ZX; tpd_LBNeg_DQ0 : VitalDelayType01ZX := UnitDelay01ZX; tpd_UBNeg_DQ0 : VitalDelayType01ZX := UnitDelay01ZX; tsetup_DQ0_WENeg : VitalDelayType := UnitDelay; -- tD0, WENeg / tsetup_A16_AVDNeg : VitalDelayType := UnitDelay; tsetup_A16_WENeg : VitalDelayType := UnitDelay; -- tA, WENeg / -- tCSNeg, CSNeglow, WENeg / tsetup_CSNeg_WENeg : VitalDelayType := UnitDelay; -- tUBNeg, UBlow, WENeg / tsetup_UBNeg_WENeg : VitalDelayType := UnitDelay; -- tLBNeg, LBlow, WENeg / tsetup_LBNeg_WENeg : VitalDelayType := UnitDelay; -- tWENeg, WENeglow, CSNeg / tsetup_WENeg_CSNeg : VitalDelayType := UnitDelay; -- dq stable after address has change tsetup_CSNeg_AVDNeg : VitalDelayType := UnitDelay; tsetup_AVDNeg_WENEg : VitalDelayType := UnitDelay; thold_DQ0_WENeg : VitalDelayType := UnitDelay; -- tD0, WENeg / thold_A16_AVDNeg : VitalDelayType := UnitDelay; --sram tpw_WENeg_negedge : VitalDelayType := UnitDelay; -- tWENeg tpw_AVDNeg_negedge : VitalDelayType := UnitDelay; -- tWENeg -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded sram_file_name : STRING := "none"; UserPreload : BOOLEAN := FALSE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A19 : IN std_ulogic := 'U'; A18 : IN std_ulogic := 'U'; A17 : IN std_ulogic := 'U'; A16 : IN std_ulogic := 'U'; DQ15 : INOUT std_ulogic := 'U'; DQ14 : INOUT std_ulogic := 'U'; DQ13 : INOUT std_ulogic := 'U'; DQ12 : INOUT std_ulogic := 'U'; DQ11 : INOUT std_ulogic := 'U'; DQ10 : INOUT std_ulogic := 'U'; DQ9 : INOUT std_ulogic := 'U'; -- data DQ8 : INOUT std_ulogic := 'U'; -- lines DQ7 : INOUT std_ulogic := 'U'; DQ6 : INOUT std_ulogic := 'U'; DQ5 : INOUT std_ulogic := 'U'; DQ4 : INOUT std_ulogic := 'U'; DQ3 : INOUT std_ulogic := 'U'; DQ2 : INOUT std_ulogic := 'U'; DQ1 : INOUT std_ulogic := 'U'; DQ0 : INOUT std_ulogic := 'U'; CSNeg : IN std_ulogic := 'U'; AVDNeg : IN std_ulogic := 'U'; LBNeg : IN std_ulogic := 'U'; UBNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of pSRAM_16 : ENTITY IS TRUE; END pSRAM_16; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral_sram of pSRAM_16 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral_sram : ARCHITECTURE IS TRUE; CONSTANT PartID : STRING := "pSRAM_16"; -- interconnect path delay signals SIGNAL A19_ipd : std_ulogic := 'U'; SIGNAL A18_ipd : std_ulogic := 'U'; SIGNAL A17_ipd : std_ulogic := 'U'; SIGNAL A16_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; SIGNAL CSNeg_ipd : std_ulogic := 'U'; SIGNAL AVDNeg_ipd : std_ulogic := 'U'; SIGNAL LBNeg_ipd : std_ulogic := 'U'; SIGNAL UBNeg_ipd : std_ulogic := 'U'; BEGIN --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_0 : VitalWireDelay (A19_ipd, A19, tipd_A19); w_1 : VitalWireDelay (A18_ipd, A18, tipd_A18); w_2 : VitalWireDelay (A17_ipd, A17, tipd_A17); w_3 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_4 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15); w_5 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14); w_6 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13); w_7 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12); w_8 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11); w_9 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10); w_10 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9); w_11 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8); w_12 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7); w_13 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6); w_14 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5); w_15 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4); w_16 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_17 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_18 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_19 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_20 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_21 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg); w_22 : VitalWireDelay (LBNeg_ipd, LBNeg, tipd_LBNeg); w_23 : VitalWireDelay (UBNeg_ipd, UBNeg, tipd_UBNeg); w_24 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_25 : VitalWireDelay (AVDNeg_ipd, AVDNeg, tipd_AVDNeg); END BLOCK; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior: BLOCK PORT ( A : IN std_logic_vector(19 DOWNTO 0) := (OTHERS => 'U'); DIn : IN std_logic_vector(15 DOWNTO 0) := (OTHERS => 'U'); DOut : OUT std_logic_vector(15 DOWNTO 0) := (OTHERS => 'U'); CSNeg : IN std_ulogic := 'U'; AVDNeg : IN std_ulogic := 'U'; LBNeg : IN std_ulogic := 'U'; UBNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U' ); PORT MAP ( A(19) => A19_ipd, A(18) => A18_ipd, A(17) => A17_ipd, A(16) => A16_ipd, A(15) => DQ15_ipd, A(14) => DQ14_ipd, A(13) => DQ13_ipd, A(12) => DQ12_ipd, A(11) => DQ11_ipd, A(10) => DQ10_ipd, A(9) => DQ9_ipd, A(8) => DQ8_ipd, A(7) => DQ7_ipd, A(6) => DQ6_ipd, A(5) => DQ5_ipd, A(4) => DQ4_ipd, A(3) => DQ3_ipd, A(2) => DQ2_ipd, A(1) => DQ1_ipd, A(0) => DQ0_ipd, DIn(15) => DQ15_ipd, DIn(14) => DQ14_ipd, DIn(13) => DQ13_ipd, DIn(12) => DQ12_ipd, DIn(11) => DQ11_ipd, DIn(10) => DQ10_ipd, DIn(9) => DQ9_ipd, DIn(8) => DQ8_ipd, DIn(7) => DQ7_ipd, DIn(6) => DQ6_ipd, DIn(5) => DQ5_ipd, DIn(4) => DQ4_ipd, DIn(3) => DQ3_ipd, DIn(2) => DQ2_ipd, DIn(1) => DQ1_ipd, DIn(0) => DQ0_ipd, DOut(15) => DQ15, DOut(14) => DQ14, DOut(13) => DQ13, DOut(12) => DQ12, DOut(11) => DQ11, DOut(10) => DQ10, DOut(9) => DQ9, DOut(8) => DQ8, DOut(7) => DQ7, DOut(6) => DQ6, DOut(5) => DQ5, DOut(4) => DQ4, DOut(3) => DQ3, DOut(2) => DQ2, DOut(1) => DQ1, DOut(0) => DQ0, CSNeg => CSNeg_ipd, AVDNeg => AVDNeg_ipd, LBNeg => LBNeg_ipd, UBNeg => UBNeg_ipd, OENeg => OENeg_ipd, WENeg => WENeg_ipd ); -- SRAM DECLERATION CONSTANT SRAMMaxData : NATURAL := 16#FF#; CONSTANT SRAM_DEPTH : NATURAL := 16#1FFFFF#; -- 512 KBit CONSTANT SRAM_LENGTH : NATURAL := 8; -- 8 bit word TYPE SRAM_TYPE IS ARRAY (0 to SRAM_DEPTH) OF INTEGER RANGE 0 TO SRAMMaxData; SHARED VARIABLE SRAM : SRAM_TYPE := (OTHERS => 0); SIGNAL Sram_address : NATURAL; SIGNAL Sram_read : std_logic := '0'; SIGNAL Sram_write : std_logic := '0'; SIGNAL DOutH_zd : std_logic_vector(7 DOWNTO 0):= (OTHERS =>'Z'); SIGNAL DOutL_zd : std_logic_vector(7 DOWNTO 0):= (OTHERS =>'Z'); SIGNAL DOutH_pass : std_logic_vector(7 DOWNTO 0):= (OTHERS =>'Z'); SIGNAL DOutL_pass : std_logic_vector(7 DOWNTO 0):= (OTHERS =>'Z'); SIGNAL DOutH_tmp : std_logic_vector(7 DOWNTO 0):= (OTHERS =>'Z'); SIGNAL DOutL_tmp : std_logic_vector(7 DOWNTO 0):= (OTHERS =>'Z'); -- signals that disable OE vital path condition SIGNAL OEUB_en: std_logic := '1'; SIGNAL OELB_en: std_logic := '1'; SIGNAL tOLZ_en: BOOLEAN := FALSE; SHARED VARIABLE ConfReg: std_logic_vector (15 DOWNTO 0) := (OTHERS =>'0'); SHARED VARIABLE path_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; SHARED VARIABLE path_CSNeg_DQ0: VitalDelayType01Z := UnitDelay01Z; SHARED VARIABLE path_LBNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; SHARED VARIABLE path_UBNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; SHARED VARIABLE tOLZ_OE : VitalDelayType01Z := UnitDelay01Z; SHARED VARIABLE tOLZ_CSNeg : VitalDelayType01Z := UnitDelay01Z; SHARED VARIABLE tOLZ_UBNeg : VitalDelayType01Z := UnitDelay01Z; SHARED VARIABLE tOLZ_LBNeg : VitalDelayType01Z := UnitDelay01Z; SHARED VARIABLE FROMOEUB, FROMCSUB, FROMUB, FROMLB: BOOLEAN; SHARED VARIABLE FROMOELB, FROMCSLB, OPENLATCH : BOOLEAN; BEGIN --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS(WENeg,OENeg,CSNeg, AVDNeg, UBNeg,LBNeg, DIn, Sram_write, A) --Setup/Hold checks variables --sram VARIABLE Tviol_D0_WENeg : X01 := '0'; VARIABLE Tviol_A16_AVDNeg : X01 := '0'; VARIABLE Tviol_A16_WENeg : X01 := '0'; VARIABLE Tviol_CSNeg_WENeg : X01 := '0'; VARIABLE Tviol_LBNeg_WENeg : X01 := '0'; VARIABLE Tviol_UBNeg_WENeg : X01 := '0'; VARIABLE Tviol_WENeg_CSNeg : X01 := '0'; VARIABLE Tviol_CSNeg_AVDNeg : X01 := '0'; VARIABLE Tviol_AVDNeg_WENEg : X01 := '0'; VARIABLE TD_A16_WENeg : VitalTimingDataType; VARIABLE TD_D0_WENeg : VitalTimingDataType; VARIABLE TD_CSNeg_WENeg : VitalTimingDataType; VARIABLE TD_A16_AVDNeg : VitalTimingDataType; VARIABLE TD_LBNeg_WENeg : VitalTimingDataType; VARIABLE TD_UBNeg_WENeg : VitalTimingDataType; VARIABLE TD_WENeg_CSNeg : VitalTimingDataType; VARIABLE TD_AVDNeg_WENEg : VitalTimingDataType; VARIABLE TD_CSNeg_AVDNeg : VitalTimingDataType; --sram VARIABLE Pviol_WENeg : X01 := '0'; VARIABLE Pviol_AVDNeg : X01 := '0'; VARIABLE PD_WENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AVDNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01; BEGIN IF TimingChecksOn THEN -- Setup/Hold Checks Violation := '0'; --sram VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "Data", RefSignal => Sram_write, RefSignalName => "Sram_write", SetupHigh => tsetup_DQ0_WENeg, SetupLow => tsetup_DQ0_WENeg, HoldHigh => thold_DQ0_WENeg, HoldLow => thold_DQ0_WENeg, CheckEnabled => Sram_read = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_D0_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_WENeg ); VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "Address", RefSignal => AVDNeg, RefSignalName => "AVDNeg", SetupHigh => tsetup_A16_AVDNeg, SetupLow => tsetup_A16_AVDNeg, HoldHigh => thold_A16_AVDNeg, HoldLow => thold_A16_AVDNeg, CheckEnabled => CSNeg = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A16_AVDNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A16_AVDNeg ); VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "Address", RefSignal => Sram_write, RefSignalName => "Sram_write", SetupHigh => tsetup_A16_WENeg, SetupLow => tsetup_A16_WENeg, CheckEnabled => (Sram_read = '0'), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A16_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A16_WENeg ); VitalSetupHoldCheck ( TestSignal => CSNeg, TestSignalName => "CS#", RefSignal => Sram_write, RefSignalName => "Sram_write", SetupLow => tsetup_CSNeg_WENeg, CheckEnabled => Sram_read = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CSNeg_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CSNeg_WENeg ); VitalSetupHoldCheck ( TestSignal => UBNeg, TestSignalName => "UB#", RefSignal => Sram_write, RefSignalName => "Sram_write#", SetupLow => tsetup_UBNeg_WENeg, SetupHigh => tsetup_UBNeg_WENeg, CheckEnabled => Sram_read = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_UBNeg_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_UBNeg_WENeg ); VitalSetupHoldCheck ( TestSignal => LBNeg, TestSignalName => "LB#", RefSignal => Sram_write, RefSignalName => "Sram_write", SetupLow => tsetup_LBNeg_WENeg, SetupHigh => tsetup_LBNeg_WENeg, CheckEnabled => Sram_read = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_LBNeg_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LBNeg_WENeg ); VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WE#", RefSignal => Sram_write, RefSignalName => "Sram_write", SetupLow => tsetup_WENeg_CSNeg, CheckEnabled => Sram_read = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_CSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENeg_CSNeg ); VitalSetupHoldCheck ( TestSignal => CSNeg, TestSignalName => "CS#", RefSignal => AVDNeg, RefSignalName => "AVD#", SetupLow => tsetup_CSNeg_AVDNeg, CheckEnabled => Sram_read = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CSNeg_AVDNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CSNeg_AVDNeg ); VitalSetupHoldCheck ( TestSignal => AVDNeg, TestSignalName => "AVD#", RefSignal => Sram_write, RefSignalName => "Sram_write", SetupLow => tsetup_AVDNeg_WENEg, CheckEnabled => Sram_read = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_AVDNeg_WENEg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AVDNeg_WENEg ); VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WE#", PulseWidthLow => tpw_WENeg_negedge, PeriodData => PD_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WENeg, HeaderMsg => InstancePath & PartID, CheckEnabled => CSNeg = '0' ); VitalPeriodPulseCheck ( TestSignal => AVDNEg, TestSignalName => "AVD#", PulseWidthLow => tpw_AVDNeg_negedge, PeriodData => PD_AVDNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AVDNeg, HeaderMsg => InstancePath & PartID, CheckEnabled => CSNeg = '0' ); Violation := Tviol_D0_WENeg OR Tviol_A16_AVDNeg OR Tviol_A16_WENeg OR Tviol_CSNeg_WENeg OR Tviol_LBNeg_WENeg OR Tviol_UBNeg_WENeg OR Tviol_WENeg_CSNeg OR Tviol_AVDNeg_WENEg OR Tviol_CSNeg_AVDNeg OR Pviol_WENeg OR Pviol_AVDNeg ; ASSERT Violation = '0' REPORT InstancePath & " simulation may be inaccurate due to timing violations" SEVERITY WARNING; END IF; -- TimingChecksOn END PROCESS VITALTimingCheck; --------------------------------------------------------------------------- -- sequential process for reset control and FSM state transition --------------------------------------------------------------------------- -- SRAM INSERT SRAM_COMMAND : PROCESS(CSNeg, OENeg, WENeg, AVDNeg) BEGIN IF AVDNeg = '1' THEN IF CSNeg = '0' AND OENeg = '0' AND WENeg = '1' THEN Sram_read <= '1'; Sram_write <= '0'; ELSIF CSNeg = '0' AND OENeg = '1' AND WENeg = '0' THEN Sram_write <= '1'; Sram_read <= '0'; ELSE Sram_read <= '0'; Sram_write <= '0'; END IF; ELSE Sram_read <= '0'; Sram_write <= '0'; END IF; END PROCESS SRAM_COMMAND ; --------------------------------------------------------------------------- -- Latch address on falling edge of WE# or CE# what ever comes later -- Latches data on rising edge of WE# or CE# what ever comes first -- also Write cycle decode --------------------------------------------------------------------------- LatchAddress : PROCESS(A, AVDNeg, CSNeg) VARIABLE Addr_latch : BOOLEAN := FALSE; BEGIN IF (AVDNeg = '0' AND CSNeg = '0') THEN IF ConfReg(3 DOWNTO 2) = "00" THEN Sram_address <= 2*to_nat(A); ELSIF ConfReg(3 DOWNTO 2) = "01" THEN Sram_address <= 2*to_nat(A(18 DOWNTO 0)); ELSIF ConfReg(3 DOWNTO 2) = "10" THEN Sram_address <= 2*to_nat(A(17 DOWNTO 0)); ELSE Sram_address <= 2*to_nat(A(16 DOWNTO 0)); END IF; END IF; END PROCESS LatchAddress; SRAM_RW_PROC: PROCESS(Sram_read, Sram_write, UBNeg, LBNeg, A, CSNeg, WENeg) VARIABLE SramDatahigh : NATURAL; VARIABLE SramDataLow : NATURAL; VARIABLE DOut_tmp : std_logic_vector(15 DOWNTO 0); BEGIN IF falling_edge(Sram_write) THEN SramDataHigh := to_nat(DIn(15 DOWNTO 8)); SramDataLow := to_nat(DIn(7 DOWNTO 0)); IF UBNeg = '0' THEN SRAM(Sram_address+1) := SramDataHigh; END IF; IF LBNeg = '0' THEN SRAM(Sram_address) := SramDataLow; END IF; IF UBNeg = '1' AND LBNeg = '1' THEN ConfReg := DIn; END IF; END IF; IF Sram_read = '1' THEN DOut_tmp := to_slv(SRAM(Sram_address+1), 8) & to_slv(SRAM(Sram_address), 8); IF falling_edge(UBNeg) THEN DOutH_zd <= (OTHERS =>'X'), DOut_tmp(15 DOWNTO 8)AFTER 2 ns; tOLZ_en <= TRUE, FALSE AFTER 1 ns; ELSIF UBNeg = '0' THEN DOutH_zd <= DOut_tmp(15 DOWNTO 8)AFTER 2 ns; ELSE DOutH_zd <= (OTHERS =>'Z')AFTER 2 ns; END IF; IF falling_edge(LBNeg) THEN DOutL_zd <= (OTHERS =>'X'), DOut_tmp(7 DOWNTO 0)AFTER 2 ns; tOLZ_en <= TRUE, FALSE AFTER 1 ns; ELSIF LBNeg = '0' THEN DOutL_zd <= DOut_tmp(7 DOWNTO 0)AFTER 2 ns; ELSE DOutL_zd <= (OTHERS =>'Z')AFTER 2 ns; END IF; IF rising_edge(sram_read) THEN tOLZ_en <= TRUE, FALSE AFTER 1 ns; END IF; IF UBNeg = '1' AND LBNeg = '1' THEN IF rising_edge(sram_read) THEN DOutL_zd <= (OTHERS =>'X'), ConfReg(7 DOWNTO 0) AFTER 2 ns; DOutH_zd <= (OTHERS =>'X'), ConfReg(15 DOWNTO 8) AFTER 2 ns; ELSE DOutL_zd <= ConfReg(7 DOWNTO 0) AFTER 2 ns; DOutH_zd <= ConfReg(15 DOWNTO 8) AFTER 2 ns; END IF; END IF; ELSE DOutH_zd <= (OTHERS =>'Z') AFTER 2 ns; DOutL_zd <= (OTHERS =>'Z') AFTER 2 ns; END IF; END PROCESS SRAM_RW_PROC; MemPldSRAM : PROCESS -- text file input variables FILE sram_f : text is sram_file_name; VARIABLE ind : NATURAL; VARIABLE buf : line; VARIABLE report_err : BOOLEAN := FALSE; BEGIN ----------------------------------------------------------------------- -- s71ns128ja0 SRAM preload file format ----------------------------------------------------------------------- -- / - comment -- @aaaaa - stands for address -- dddd - is word to be written at SRAM(aaaaa++) -- (aaaaa is incremented at every load) -- only first 1-6 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ----------------------------------------------------------------------- IF UserPreload AND (sram_file_name/= "none" ) THEN ind := 0; SRAM := (OTHERS => SRAMMaxData); WHILE (not ENDFILE (sram_f)) LOOP READLINE (sram_f, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 6))*2; ELSE IF ind < SRAM_DEPTH THEN SRAM(ind) := h(buf(3 to 4)); ind := ind + 1; SRAM(ind) := h(buf(1 to 2)); ind := ind + 1; ELSE IF report_err = FALSE THEN REPORT "Memory file:" & sram_file_name & " Address range overflow" SEVERITY warning; report_err := TRUE; END IF; END IF; END IF; END LOOP; END IF; WAIT; END PROCESS; ----------------------------------------------------------------------- -- Path Delay Section ----------------------------------------------------------------------- DOutPassThroughL : PROCESS(DOutL_zd, sram_read) VARIABLE ValidData : std_logic_vector(15 DOWNTO 0); VARIABLE CEDQ_t : TIME; VARIABLE OEDQ_t : TIME; VARIABLE LBDQ_t : TIME; VARIABLE ADDRDQ_t : TIME; BEGIN IF rising_edge(sram_read) THEN DOutL_Pass <= "ZZZZZZZZ"; IF LBNeg = '0' THEN DOutL_Pass <= "XXXXXXXX"; END IF; ELSE OPENLATCH := TRUE; OEDQ_t := - OENeg'LAST_EVENT + tpd_OENeg_DQ0(trz0); CEDQ_t := - CSNeg'LAST_EVENT + tpd_CSNeg_DQ0(trz0); LBDQ_t := - LBNeg'LAST_EVENT + tpd_LBNeg_DQ0(trz0); ADDRDQ_t := - Sram_address'LAST_EVENT + tpd_A16_DQ0(tr01); FROMOELB := (OEDQ_t >= CEDQ_t) AND (OEDQ_t >= LBDQ_t) AND (OEDQ_t > 0 ns) ; FROMCSLB := (CEDQ_t > OEDQ_t) AND (CEDQ_t >= LBDQ_t) AND (CEDQ_t > 0 ns) ; FROMLB := (LBDQ_t > OEDQ_t) AND (LBDQ_t > CEDQ_t) AND (LBDQ_t > 0 ns) ; IF DOutL_zd(0) /= 'Z' THEN IF LBNeg = '0' THEN ValidData(7 DOWNTO 0) := "XXXXXXXX"; ELSE ValidData(7 DOWNTO 0) := "ZZZZZZZZ"; END IF; IF ((ADDRDQ_t > 0 ns) AND (((ADDRDQ_t > CEDQ_t) AND FROMCSLB) OR ((ADDRDQ_t > OEDQ_t) AND FROMOELB) OR ((ADDRDQ_t > LBDQ_t) AND FROMLB) )) THEN DOutL_Pass <= ValidData(7 DOWNTO 0) , DOutL_zd AFTER ADDRDQ_t; ELSE DOutL_Pass <= DOutL_zd ; END IF; ELSE DOutL_Pass <= DOutL_zd; END IF; END IF; END PROCESS DOutPassThroughL; ----------------------------------------------------------------------- -- Path Delay Section ----------------------------------------------------------------------- DOutPassThroughH : PROCESS(DOutH_zd, sram_read) VARIABLE ValidData : std_logic_vector(15 DOWNTO 0); VARIABLE CEDQ_t : TIME; VARIABLE OEDQ_t : TIME; VARIABLE UBDQ_t : TIME; VARIABLE ADDRDQ_t : TIME; BEGIN IF rising_edge(sram_read) THEN DOutH_Pass <= "ZZZZZZZZ"; IF UBNeg = '0' THEN DOutH_Pass <= "XXXXXXXX"; END IF; ELSE OPENLATCH := TRUE; OEDQ_t := - OENeg'LAST_EVENT + tpd_OENeg_DQ0(trz0); CEDQ_t := - CSNeg'LAST_EVENT + tpd_CSNeg_DQ0(trz0); UBDQ_t := - UBNeg'LAST_EVENT + tpd_UBNeg_DQ0(trz0); ADDRDQ_t := - Sram_address'LAST_EVENT + tpd_A16_DQ0(tr01); FROMOEUB := (OEDQ_t >= CEDQ_t) AND (OEDQ_t >= UBDQ_t) AND (OEDQ_t > 0 ns); FROMCSUB := (CEDQ_t > OEDQ_t) AND (CEDQ_t >= UBDQ_t) AND (CEDQ_t > 0 ns); FROMUB := (UBDQ_t > OEDQ_t) AND (UBDQ_t > CEDQ_t) AND (UBDQ_t > 0 ns) ; IF DOutH_zd(0) /= 'Z' THEN IF UBNeg = '0' THEN ValidData(15 DOWNTO 8) := "XXXXXXXX"; ELSE ValidData(15 DOWNTO 8) := "ZZZZZZZZ"; END IF; IF ((ADDRDQ_t > 0 ns) AND (((ADDRDQ_t > CEDQ_t) AND FROMCSUB) OR ((ADDRDQ_t > OEDQ_t) AND FROMOEUB) OR ((ADDRDQ_t > UBDQ_t) AND FROMUB) )) THEN DOutH_Pass <= ValidData(15 DOWNTO 8), DOutH_zd AFTER ADDRDQ_t ; ELSE DOutH_Pass <= DOutH_zd; END IF; ELSE DOutH_Pass <= DOutH_zd; END IF; END IF; END PROCESS DOutPassThroughH; InithPathDelay : PROCESS BEGIN path_OENeg_DQ0 (tr0z) := tpd_OENeg_DQ0 (tr0z); path_CSNeg_DQ0 (tr0z) := tpd_CSNeg_DQ0 (tr0z); path_LBNeg_DQ0 (tr0z) := tpd_LBNeg_DQ0 (tr0z); path_UBNeg_DQ0 (tr0z) := tpd_UBNeg_DQ0 (tr0z); path_OENeg_DQ0 (tr1z) := tpd_OENeg_DQ0 (tr1z); path_CSNeg_DQ0 (tr1z) := tpd_CSNeg_DQ0 (tr1z); path_LBNeg_DQ0 (tr1z) := tpd_LBNeg_DQ0 (tr1z); path_UBNeg_DQ0 (tr1z) := tpd_UBNeg_DQ0 (tr1z); path_OENeg_DQ0 (tr01) := tpd_OENeg_DQ0 (tr01); path_CSNeg_DQ0 (tr01) := tpd_CSNeg_DQ0 (tr01); path_LBNeg_DQ0 (tr01) := tpd_LBNeg_DQ0 (tr01); path_UBNeg_DQ0 (tr01) := tpd_UBNeg_DQ0 (tr01); path_OENeg_DQ0 (trz1) := tpd_OENeg_DQ0 (trz1); path_CSNeg_DQ0 (trz1) := tpd_CSNeg_DQ0 (trz1); path_LBNeg_DQ0 (trz1) := tpd_LBNeg_DQ0 (trz1); path_UBNeg_DQ0 (trz1) := tpd_UBNeg_DQ0 (trz1); path_OENeg_DQ0 (tr10) := tpd_OENeg_DQ0 (tr10); path_CSNeg_DQ0 (tr10) := tpd_CSNeg_DQ0 (tr10); path_LBNeg_DQ0 (tr10) := tpd_LBNeg_DQ0 (tr10); path_UBNeg_DQ0 (tr10) := tpd_UBNeg_DQ0 (tr10); path_OENeg_DQ0 (trz0) := tpd_OENeg_DQ0 (trz0); path_CSNeg_DQ0 (trz0) := tpd_CSNeg_DQ0 (trz0); path_LBNeg_DQ0 (trz0) := tpd_LBNeg_DQ0 (trz0); path_UBNeg_DQ0 (trz0) := tpd_UBNeg_DQ0 (trz0); tOLZ_OE (tr01):= tpd_OENeg_DQ0 (trzx); tOLZ_CSNeg (tr01):= tpd_CSNeg_DQ0 (trzx); tOLZ_UBNeg (tr01):= tpd_LBNeg_DQ0 (trzx); tOLZ_LBNeg (tr01):= tpd_UBNeg_DQ0 (trzx); tOLZ_OE (tr0z):= tpd_OENeg_DQ0 (trzx); tOLZ_CSNeg (tr0z):= tpd_CSNeg_DQ0 (trzx); tOLZ_UBNeg (tr0z):= tpd_LBNeg_DQ0 (trzx); tOLZ_LBNeg (tr0z):= tpd_UBNeg_DQ0 (trzx); tOLZ_OE (trz1):= tpd_OENeg_DQ0 (trzx); tOLZ_CSNeg (trz1):= tpd_CSNeg_DQ0 (trzx); tOLZ_UBNeg (trz1):= tpd_LBNeg_DQ0 (trzx); tOLZ_LBNeg (trz1):= tpd_UBNeg_DQ0 (trzx); tOLZ_OE (trz0):= tpd_OENeg_DQ0 (trzx); tOLZ_CSNeg (trz0):= tpd_CSNeg_DQ0 (trzx); tOLZ_UBNeg (trz0):= tpd_LBNeg_DQ0 (trzx); tOLZ_LBNeg (trz0):= tpd_UBNeg_DQ0 (trzx); tOLZ_OE (tr10):= tpd_OENeg_DQ0 (trzx); tOLZ_CSNeg (tr10):= tpd_CSNeg_DQ0 (trzx); tOLZ_UBNeg (tr10):= tpd_LBNeg_DQ0 (trzx); tOLZ_LBNeg (tr10):= tpd_UBNeg_DQ0 (trzx); tOLZ_OE (tr1z):= tpd_OENeg_DQ0 (trzx); tOLZ_CSNeg (tr1z):= tpd_CSNeg_DQ0 (trzx); tOLZ_UBNeg (tr1z):= tpd_LBNeg_DQ0 (trzx); tOLZ_LBNeg (tr1z):= tpd_UBNeg_DQ0 (trzx); WAIT; END PROCESS; --------------------------------------------------------------------------- -- Path Delay Section for DOut signal --------------------------------------------------------------------------- D_OutUB_PathDelay_Gen : FOR i IN 0 TO 7 GENERATE --Dout_zd'RANGE GENERATE PROCESS(DOutH_Pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; VARIABLE OE :boolean := false; BEGIN VitalPathDelay01Z( OutSignal => DOutH_tmp(i), OutSignalName => "DOut", OutTemp => DOutH_Pass(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => CSNeg'LAST_EVENT, PathDelay => path_CSNeg_DQ0, PathCondition => FROMCSUB AND tOLZ_en = FALSE), 1 => (InputChangeTime => UBNeg'LAST_EVENT, PathDelay => path_UBNeg_DQ0, PathCondition => FROMUB AND tOLZ_en = FALSE), 2 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => path_OENeg_DQ0, PathCondition => FROMOEUB AND tOLZ_en = FALSE), 3 => (InputChangeTime => CSNeg'LAST_EVENT, PathDelay => tOLZ_CSNeg, PathCondition => tOLZ_en = TRUE), 4 => (InputChangeTime => UBNeg'LAST_EVENT, PathDelay => tOLZ_UBNeg, PathCondition => tOLZ_en = TRUE), 5 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tOLZ_OE, PathCondition => tOLZ_en = TRUE) ) ); END PROCESS; END GENERATE D_OutUB_PathDelay_Gen; D_OutLB_PathDelay_Gen : FOR i IN 0 TO 7 GENERATE --Dout_zd'RANGE GENERATE PROCESS(DOutL_Pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; VARIABLE OE :boolean := false; BEGIN VitalPathDelay01Z( OutSignal => DOutL_tmp(i), OutSignalName => "DOut", OutTemp => DOutL_Pass(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => CSNeg'LAST_EVENT, PathDelay => path_CSNeg_DQ0, PathCondition => FROMCSLB AND tOLZ_en = FALSE), 1 => (InputChangeTime => LBNeg'LAST_EVENT, PathDelay => path_LBNeg_DQ0, PathCondition => FROMLB AND tOLZ_en = FALSE), 2 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => path_OENeg_DQ0, PathCondition => FROMOELB AND tOLZ_en = FALSE), 3 => (InputChangeTime => CSNeg'LAST_EVENT, PathDelay => tOLZ_CSNeg, PathCondition => tOLZ_en = TRUE), 4 => (InputChangeTime => LBNeg'LAST_EVENT, PathDelay => tOLZ_LBNeg, PathCondition => tOLZ_en = TRUE), 5 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tOLZ_OE, PathCondition => tOLZ_en = TRUE) ) ); END PROCESS; DOut <= DOutH_tmp & DOutL_tmp; END GENERATE D_OutLB_PathDelay_Gen; END BLOCK behavior; END vhdl_behavioral_sram; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION FOR TOP s71ns128ja0 ENTITY ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of s71ns128ja0 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; COMPONENT s29ns128j GENERIC ( tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_A18 : VitalDelayType01 := VitalZeroDelay01; tipd_A19 : VitalDelayType01 := VitalZeroDelay01; tipd_A20 : VitalDelayType01 := VitalZeroDelay01; tipd_A21 : VitalDelayType01 := VitalZeroDelay01; tipd_A22 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_AVDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; tipd_Vpp : VitalDelayType01 := VitalZeroDelay01; -- tpd delays for FLASH tpd_A16_DQ0_asynchro_eq_0 : VitalDelayType01 := UnitDelay01; tpd_A16_DQ0_asynchro_eq_1 : VitalDelayType01 := UnitDelay01; tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; tpd_CLK_RDY : VitalDelayType01 := UnitDelay01; tpd_CLK_DQ0 : VitalDelayType01 := UnitDelay01; tpd_OENeg_RDY : VitalDelayType01Z := UnitDelay01Z; tpd_CENeg_RDY : VitalDelayType01Z := UnitDelay01Z; --tCES , CE LOW , CLK / tsetup_CENeg_CLK : VitalDelayType := UnitDelay; tsetup_RDY_CLK : VitalDelayType := UnitDelay; -- Asynchronous Write --tCS, CENeg LOW, WENeg \ tsetup_CENeg_WENeg : VitalDelayType := UnitDelay; --tAS, , WENeg \ tsetup_A16_AVDNeg : VitalDelayType := UnitDelay; --tDS, , WENeg / tsetup_DQ0_WENeg : VitalDelayType := UnitDelay; --tGHWL, OENeg HIGH , WENeg \ tsetup_OENeg_WENeg : VitalDelayType := UnitDelay; --tOEH, WENeg HIGH , OENeg \ tsetup_WENeg_OENeg : VitalDelayType := UnitDelay; tsetup_AVDNeg_CLK : VitalDelayType := UnitDelay; --thold values -- tAH, , WENeg \ thold_A16_AVDNeg : VitalDelayType := UnitDelay; -- tDH, , WENeg / thold_DQ0_WENeg : VitalDelayType := UnitDelay; thold_DQ0_CLK : VitalDelayType := UnitDelay; --tRH , CENeg HIGH, RESET / thold_CENeg_RESETNeg : VitalDelayType := UnitDelay; --tRH , OENeg HIGH, RESET / thold_OENeg_RESETNeg : VitalDelayType := UnitDelay; --tWH ,WENeg LOW ,CENeg / thold_CENeg_WENeg : VitalDelayType := UnitDelay; thold_AVDNeg_CLK : VitalDelayType := UnitDelay; --tpw values: pulse width -- Burst Mode tpw_AVDNeg_negedge : VitalDelayType := UnitDelay; -- tADVP -- Reset tpw_RESETNeg_negedge : VitalDelayType := UnitDelay; -- tRP -- ASync Write tpw_WENeg_negedge : VitalDelayType := UnitDelay; -- tWP tpw_WENeg_posedge : VitalDelayType := UnitDelay; -- tWPH -- tdevice values: values for internal delays tdevice_POW : VitalDelayType := UnitDelay; --Sector Erase Operation tWHWH2 tdevice_SEO : VitalDelayType := UnitDelay; --erase suspend timeout - only max time specified tdevice_ESTART_T1 : VitalDelayType := UnitDelay; --sector erase command sequence timeout tdevice_CTMOUT : VitalDelayType := UnitDelay; --device ready after Hardware reset(during embeded algorithm) tdevice_READY : VitalDelayType := UnitDelay; --tReady -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded flash_file_name : STRING := "none"; UserPreload : BOOLEAN := FALSE; LongTimming : BOOLEAN := FALSE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A22 : IN std_ulogic := 'U'; A21 : IN std_ulogic := 'U'; A20 : IN std_ulogic := 'U'; A19 : IN std_ulogic := 'U'; A18 : IN std_ulogic := 'U'; A17 : IN std_ulogic := 'U'; A16 : IN std_ulogic := 'U'; DQ15 : INOUT std_ulogic := 'U'; DQ14 : INOUT std_ulogic := 'U'; DQ13 : INOUT std_ulogic := 'U'; DQ12 : INOUT std_ulogic := 'U'; DQ11 : INOUT std_ulogic := 'U'; DQ10 : INOUT std_ulogic := 'U'; DQ9 : INOUT std_ulogic := 'U'; DQ8 : INOUT std_ulogic := 'U'; DQ7 : INOUT std_ulogic := 'U'; DQ6 : INOUT std_ulogic := 'U'; DQ5 : INOUT std_ulogic := 'U'; DQ4 : INOUT std_ulogic := 'U'; DQ3 : INOUT std_ulogic := 'U'; DQ2 : INOUT std_ulogic := 'U'; DQ1 : INOUT std_ulogic := 'U'; DQ0 : INOUT std_ulogic := 'U'; CENeg : IN std_ulogic := 'U'; AVDNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; CLK : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; Vpp : IN std_ulogic := 'U'; RDY : OUT std_ulogic := 'U' ); END COMPONENT s29ns128j; FOR U_FLASH: s29ns128j USE ENTITY WORK.s29ns128j(vhdl_behavioral_flash); COMPONENT pSRAM_16 GENERIC ( tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_A18 : VitalDelayType01 := VitalZeroDelay01; tipd_A19 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_UBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_AVDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; --tpd delays for SRAM tpd_OENeg_DQ0 : VitalDelayType01ZX := UnitDelay01ZX; tpd_A16_DQ0 : VitalDelayType01 := UnitDelay01; tpd_CSNeg_DQ0 : VitalDelayType01ZX := UnitDelay01ZX; tpd_LBNeg_DQ0 : VitalDelayType01ZX := UnitDelay01ZX; tpd_UBNeg_DQ0 : VitalDelayType01ZX := UnitDelay01ZX; tsetup_DQ0_WENeg : VitalDelayType := UnitDelay; -- tD0, WENeg / thold_DQ0_WENeg : VitalDelayType := UnitDelay; -- tD0, WENeg / tsetup_A16_WENeg : VitalDelayType := UnitDelay; -- tA, WENeg / -- tCSNeg, CSNeglow, WENeg / tsetup_CSNeg_WENeg : VitalDelayType := UnitDelay; -- tUBNeg, UBlow, WENeg / tsetup_UBNeg_WENeg : VitalDelayType := UnitDelay; -- tLBNeg, LBlow, WENeg / tsetup_LBNeg_WENeg : VitalDelayType := UnitDelay; -- tWENeg, WENeglow, CSNeg / tsetup_WENeg_CSNeg : VitalDelayType := UnitDelay; -- dq stable after address has change tsetup_CSNeg_AVDNeg : VitalDelayType := UnitDelay; tsetup_AVDNeg_WENEg : VitalDelayType := UnitDelay; --sram tpw_WENeg_negedge : VitalDelayType := UnitDelay; tpw_AVDNeg_negedge : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded sram_file_name : STRING := "none"; UserPreload : BOOLEAN := FALSE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A19 : IN std_ulogic := 'U'; A18 : IN std_ulogic := 'U'; A17 : IN std_ulogic := 'U'; A16 : IN std_ulogic := 'U'; DQ15 : INOUT std_ulogic := 'U'; DQ14 : INOUT std_ulogic := 'U'; DQ13 : INOUT std_ulogic := 'U'; DQ12 : INOUT std_ulogic := 'U'; DQ11 : INOUT std_ulogic := 'U'; DQ10 : INOUT std_ulogic := 'U'; DQ9 : INOUT std_ulogic := 'U'; DQ8 : INOUT std_ulogic := 'U'; DQ7 : INOUT std_ulogic := 'U'; DQ6 : INOUT std_ulogic := 'U'; DQ5 : INOUT std_ulogic := 'U'; DQ4 : INOUT std_ulogic := 'U'; DQ3 : INOUT std_ulogic := 'U'; DQ2 : INOUT std_ulogic := 'U'; DQ1 : INOUT std_ulogic := 'U'; DQ0 : INOUT std_ulogic := 'U'; CSNeg : IN std_ulogic := 'U'; AVDNeg : IN std_ulogic := 'U'; LBNeg : IN std_ulogic := 'U'; UBNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U' ); END COMPONENT pSRAM_16; FOR U_SRAM: pSRAM_16 USE ENTITY WORK.pSRAM_16(vhdl_behavioral_sram); BEGIN U_SRAM : pSRAM_16 GENERIC MAP( -- tipd delays: interconnect path delays tipd_A16 => tipd_A16, tipd_A17 => tipd_A17, tipd_A18 => tipd_A18, tipd_A19 => tipd_A19, tipd_DQ0 => tipd_DQ0, tipd_DQ1 => tipd_DQ1, tipd_DQ2 => tipd_DQ2, tipd_DQ3 => tipd_DQ3, tipd_DQ4 => tipd_DQ4, tipd_DQ5 => tipd_DQ5, tipd_DQ6 => tipd_DQ6, tipd_DQ7 => tipd_DQ7, tipd_DQ8 => tipd_DQ8, tipd_DQ9 => tipd_DQ9, tipd_DQ10 => tipd_DQ10, tipd_DQ11 => tipd_DQ11, tipd_DQ12 => tipd_DQ12, tipd_DQ13 => tipd_DQ13, tipd_DQ14 => tipd_DQ14, tipd_DQ15 => tipd_DQ15, tipd_AVDNeg => tipd_AVDNeg, tipd_CSNeg => tipd_CSNeg, tipd_LBNeg => tipd_LBNeg, tipd_UBNeg => tipd_UBNeg, tipd_OENeg => tipd_OENeg, tipd_WENeg => tipd_WENeg, -- generic control parameters InstancePath => InstancePath, TimingChecksOn => TimingChecksOn, MsgOn => MsgOn, XOn => XOn, -- memory file to be loaded sram_file_name => sram_file_name, UserPreload => UserPreload, -- For FMF SDF technology file usage TimingModel => TimingModel ) PORT MAP( A19 => A19, A18 => A18, A17 => A17, A16 => A16, DQ15 => DQ15, DQ14 => DQ14, DQ13 => DQ13, DQ12 => DQ12, DQ11 => DQ11, DQ10 => DQ10, DQ9 => DQ9, DQ8 => DQ8, DQ7 => DQ7, DQ6 => DQ6, DQ5 => DQ5, DQ4 => DQ4, DQ3 => DQ3, DQ2 => DQ2, DQ1 => DQ1, DQ0 => DQ0, CSNeg => CSNeg, AVDNeg => AVDNeg, LBNeg => LBNeg, UBNeg => UBNeg, OENeg => OENeg, WENeg => WENeg ); U_FLASH : s29ns128j GENERIC MAP( -- tipd delays: interconnect path delays tipd_A16 => tipd_A16, tipd_A17 => tipd_A17, tipd_A18 => tipd_A18, tipd_A19 => tipd_A19, tipd_A20 => tipd_A20, tipd_A21 => tipd_LBNeg, tipd_A22 => tipd_UBNeg, tipd_DQ0 => tipd_DQ0, tipd_DQ1 => tipd_DQ1, tipd_DQ2 => tipd_DQ2, tipd_DQ3 => tipd_DQ3, tipd_DQ4 => tipd_DQ4, tipd_DQ5 => tipd_DQ5, tipd_DQ6 => tipd_DQ6, tipd_DQ7 => tipd_DQ7, tipd_DQ8 => tipd_DQ8, tipd_DQ9 => tipd_DQ9, tipd_DQ10 => tipd_DQ10, tipd_DQ11 => tipd_DQ11, tipd_DQ12 => tipd_DQ12, tipd_DQ13 => tipd_DQ13, tipd_DQ14 => tipd_DQ14, tipd_DQ15 => tipd_DQ15, -- generic control parameters InstancePath => InstancePath, TimingChecksOn => TimingChecksOn, MsgOn => MsgOn, XOn => XOn, -- memory file to be loaded flash_file_name => flash_file_name, UserPreload => UserPreload, LongTimming => LongTimming, -- For FMF SDF technology file usage TimingModel => TimingModel ) PORT MAP( A22 => UBNeg, A21 => LBNeg, A20 => A20, A19 => A19, A18 => A18, A17 => A17, A16 => A16, DQ15 => DQ15, DQ14 => DQ14, DQ13 => DQ13, DQ12 => DQ12, DQ11 => DQ11, DQ10 => DQ10, DQ9 => DQ9, DQ8 => DQ8, DQ7 => DQ7, DQ6 => DQ6, DQ5 => DQ5, DQ4 => DQ4, DQ3 => DQ3, DQ2 => DQ2, DQ1 => DQ1, DQ0 => DQ0, CENeg => CENeg, AVDNeg => AVDNeg, OENeg => OENeg, WENeg => WENeg, RESETNeg => RESETNeg, CLK => CLK, WPNeg => WPNeg, Vpp => Vpp, RDY => RDY ); END vhdl_behavioral;