------------------------------------------------------------------------------- -- File name : s29gl128s.vhd ------------------------------------------------------------------------------- -- Copyright (C) 2010-2011 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V1.0 H.Dimitrijevic 10 Sep 24 Initial -- V1.1 H. Dimitrijevic 11 Aug 08 Latest datasheet aligned(rev 02) -- V1.2 H. Dimitrijevic 11 Oct 11 Latest datasheet aligned(rev 04) -- V1.3 H. Dimitrijevic 11 Dec 26 Updated Typ. Erase Time(rev 05) -- ------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FLASH -- Technology: Flash Memory -- Part: s29gl128s -- -- Description: 128 Mbit(16MByte) CMOS 3.0 Volt core with Versatile I/O, -- 65nm MirrorBit Technology, x16 data bus -- ------------------------------------------------------------------------------- -- Known Bugs: -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.all; USE FMF.conversions.all; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY s29gl128s IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; --address tipd_A10 : VitalDelayType01 := VitalZeroDelay01; --lines tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A18 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A19 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A20 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A21 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A22 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; --WP#/ACC -- tpd delays tpd_A0_DQ0 : VitalDelayType01 := UnitDelay01;--tACC tpd_A0_DQ1 : VitalDelayType01 := UnitDelay01;--tPACC tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tCE,tCE,tDF,-,tDF,-) tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tOE,tOE,tDF,-,tDF,-) tpd_RESETNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(-,-,0,-,0,-) tpd_CENeg_RY : VitalDelayType01 := UnitDelay01; --tBUSY tpd_WENeg_RY : VitalDelayType01 := UnitDelay01; --tBUSY --tsetup values tsetup_A0_CENeg : VitalDelayType := UnitDelay; --tAS edge \ tsetup_A0_OENeg : VitalDelayType := UnitDelay; --tASO edge \ tsetup_DQ0_CENeg : VitalDelayType := UnitDelay; --tDS edge / tsetup_CENeg_WENeg : VitalDelayType := UnitDelay; --tCS edge \ --thold values thold_A0_CENeg : VitalDelayType := UnitDelay; --tAH edge thold_A0_OENeg : VitalDelayType := UnitDelay; --tAHT edge / thold_DQ0_CENeg : VitalDelayType := UnitDelay; --tDH edge / thold_OENeg_WENeg : VitalDelayType := UnitDelay; --tOEH edge / thold_CENeg_RESETNeg: VitalDelayType := UnitDelay; --tRH edge / thold_WENeg_OENeg : VitalDelayType := UnitDelay; --tGHWL edge / thold_CENeg_WENeg : VitalDelayType := UnitDelay; --tCH edge / --tpw values: pulse width tpw_A0_negedge : VitalDelayType := UnitDelay; --tWC,tRC tpw_RESETNeg_negedge: VitalDelayType := UnitDelay; --tRP tpw_OENeg_posedge : VitalDelayType := UnitDelay; --tOEPH tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP tpw_WENeg_posedge : VitalDelayType := UnitDelay; --tWPH tpw_CENeg_negedge : VitalDelayType := UnitDelay; --tCP tpw_CENeg_posedge : VitalDelayType := UnitDelay; --tCPH -- tdevice values: values for internal delays --Write Buffer Program Operation tWHWH1 tdevice_WBPB : VitalDelayType := 340 us; --Effective Write Buffer Program Operation tWHWH1 tdevice_WBPBW : VitalDelayType := 1.33 us; -- per word --Program Operation tdevice_POW : VitalDelayType := 125 us;-- per word --Sector Erase Operation tWHWH2 tdevice_SEO : VitalDelayType := 275 ms; -- Blank Check tdevice_BC :VitalDelayType := 8.5 ms; --program/erase suspend timeout tdevice_START_T1 : VitalDelayType := 40 us; --tPSL,tESL --device ready after Hardware reset(during embeded algorithm) tdevice_READY : VitalDelayType := 35 us; --tRPH -- Password Unlock tdevice_UNLOCK : VitalDelayType := 100 us; -- set the PPB Lock bit tdevice_PPBLOCK : VitalDelayType := 100 ns; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING := "none";--"s29gl128s.mem"; prot_file_name : STRING := "none";--"s29gl128s_prot.mem"; secsi_file_name : STRING := "none";--"s29gl128s_secsi.mem"; UserPreload : BOOLEAN := FALSE; LongTimming : BOOLEAN := TRUE; -- For FMF SDF technology file usage TimingModel : STRING ); PORT ( A22 : IN std_ulogic := 'U'; -- A21 : IN std_ulogic := 'U'; -- A20 : IN std_ulogic := 'U'; -- A19 : IN std_ulogic := 'U'; -- A18 : IN std_ulogic := 'U'; -- A17 : IN std_ulogic := 'U'; -- A16 : IN std_ulogic := 'U'; -- A15 : IN std_ulogic := 'U'; -- A14 : IN std_ulogic := 'U'; -- A13 : IN std_ulogic := 'U'; --address A12 : IN std_ulogic := 'U'; --lines A11 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A8 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- A6 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A1 : IN std_ulogic := 'U'; -- A0 : IN std_ulogic := 'U'; -- DQ15 : INOUT std_ulogic := 'U'; -- DQ14 : INOUT std_ulogic := 'U'; -- DQ13 : INOUT std_ulogic := 'U'; -- DQ12 : INOUT std_ulogic := 'U'; -- DQ11 : INOUT std_ulogic := 'U'; -- DQ10 : INOUT std_ulogic := 'U'; -- DQ9 : INOUT std_ulogic := 'U'; -- data DQ8 : INOUT std_ulogic := 'U'; -- lines DQ7 : INOUT std_ulogic := 'U'; -- DQ6 : INOUT std_ulogic := 'U'; -- DQ5 : INOUT std_ulogic := 'U'; -- DQ4 : INOUT std_ulogic := 'U'; -- DQ3 : INOUT std_ulogic := 'U'; -- DQ2 : INOUT std_ulogic := 'U'; -- DQ1 : INOUT std_ulogic := 'U'; -- DQ0 : INOUT std_ulogic := 'U'; -- CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; --WP#/ACC RY : OUT std_ulogic := 'U' --RY/BY# ); ATTRIBUTE VITAL_LEVEL0 of s29gl128s : ENTITY IS TRUE; END s29gl128s; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of s29gl128s IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT PartID : STRING := "S29GL128s10TFIV10"; CONSTANT MaxData : NATURAL := 16#FFFF#; CONSTANT SecSize : NATURAL := 16#FFFF#; CONSTANT SecSiSize : NATURAL := 16#1FF#; CONSTANT SecNum : NATURAL := 127; CONSTANT HiAddrBit : NATURAL := 22; CONSTANT AddrRANGE : NATURAL := 16#7FFFFF#; CONSTANT SecSiAddrRANGE: NATURAL := 16#7F01FF#; -- interconnect path delay signals SIGNAL A22_ipd : std_ulogic := 'U'; SIGNAL A21_ipd : std_ulogic := 'U'; SIGNAL A20_ipd : std_ulogic := 'U'; SIGNAL A19_ipd : std_ulogic := 'U'; SIGNAL A18_ipd : std_ulogic := 'U'; SIGNAL A17_ipd : std_ulogic := 'U'; SIGNAL A16_ipd : std_ulogic := 'U'; SIGNAL A15_ipd : std_ulogic := 'U'; SIGNAL A14_ipd : std_ulogic := 'U'; SIGNAL A13_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL CENeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; SIGNAL WPNeg_ipd : std_ulogic := 'U'; --- internal delays SIGNAL WBPO_in : std_ulogic := '0'; SIGNAL WBPO_out : std_ulogic := '0'; SIGNAL WBPOW_in : std_ulogic := '0'; SIGNAL WBPOW_out : std_ulogic := '0'; SIGNAL PO_in : std_ulogic := '0'; SIGNAL PO_out : std_ulogic := '0'; SIGNAL SEO_in : std_ulogic := '0'; SIGNAL SEO_out : std_ulogic := '0'; SIGNAL BC_in : std_ulogic := '0'; SIGNAL BC_out : std_ulogic := '0'; SIGNAL sSTART_T1 : std_ulogic := '0'; --Start TimeOut SIGNAL START_T1_in : std_ulogic := '0'; SIGNAL READY_in : std_ulogic := '0'; SIGNAL sREADY : std_ulogic := '0'; -- Device ready after reset SIGNAL sSTART_T1t : std_ulogic := '0'; --Start TimeOut SIGNAL START_T1_int : std_ulogic := '0'; SIGNAL READY_int : std_ulogic := '0'; SIGNAL sREADYt : std_ulogic := '0'; -- Device ready after reset SIGNAL UNLOCKDONE_in : std_ulogic := '0'; SIGNAL UNLOCKDONE_out : std_ulogic := '0'; SIGNAL PBPROG_in : std_ulogic := '0'; SIGNAL PBPROG_out : std_ulogic := '0'; -- Annotate SIGNAL P1_in : std_ulogic := '0'; SIGNAL P1_out : std_ulogic := '0'; SIGNAL P2_in : std_ulogic := '0'; SIGNAL P2_out : std_ulogic := '0'; BEGIN --------------------------------------------------------------------------- -- Internal Delays --------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays WBPBW :VitalBuf(WBPOW_out,WBPOW_in, (tdevice_WBPBW ,UnitDelay)); WBPB :VitalBuf(WBPO_out,WBPO_in, (tdevice_WBPB ,UnitDelay)); POW :VitalBuf(PO_out, PO_in, (tdevice_POW ,UnitDelay)); SEO :VitalBuf(SEO_out, SEO_in, (tdevice_SEO ,UnitDelay)); BC :VitalBUF(BC_out, BC_in, (tdevice_BC ,UnitDelay)); START_T1 :VitalBuf(sSTART_T1t,START_T1_int,(tdevice_START_T1,UnitDelay)); READY :VitalBuf(sREADYt, READY_int, (tdevice_READY ,UnitDelay)); UNLOCK :VitalBuf(P1_out,P1_in, (tdevice_UNLOCK ,UnitDelay)); PPBLOCK :VitalBuf(P2_out,P2_in, (tdevice_PPBLOCK ,UnitDelay)); --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (A22_ipd, A22, tipd_A22); w_2 : VitalWireDelay (A21_ipd, A21, tipd_A21); w_3 : VitalWireDelay (A20_ipd, A20, tipd_A20); w_4 : VitalWireDelay (A19_ipd, A19, tipd_A19); w_5 : VitalWireDelay (A18_ipd, A18, tipd_A18); w_6 : VitalWireDelay (A17_ipd, A17, tipd_A17); w_7 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_8 : VitalWireDelay (A15_ipd, A15, tipd_A15); w_9 : VitalWireDelay (A14_ipd, A14, tipd_A14); w_10 : VitalWireDelay (A13_ipd, A13, tipd_A13); w_11 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_12 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_13 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_14 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_15 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_16 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_17 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_18 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_19 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_20 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_21 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_22 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_23 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_24 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15); w_25 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14); w_26 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13); w_27 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12); w_28 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11); w_29 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10); w_30 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9); w_31 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8); w_32 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7); w_33 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6); w_34 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5); w_35 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4); w_36 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_37 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_38 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_39 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_40 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_41 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_42 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg); w_43 : VitalWireDelay (WPNeg_ipd, WPNeg, tipd_WPNeg); w_44 : VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg); END BLOCK; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior: BLOCK PORT ( A : IN std_logic_vector(HiAddrBit downto 0) := (OTHERS => 'U'); DIn : IN std_logic_vector(15 downto 0) := (OTHERS => 'U'); DOut : OUT std_ulogic_vector(15 downto 0) := (OTHERS => 'Z'); CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; RY : OUT std_ulogic := 'U' ); PORT MAP ( A(22) => A22_ipd, A(21) => A21_ipd, A(20) => A20_ipd, A(19) => A19_ipd, A(18) => A18_ipd, A(17) => A17_ipd, A(16) => A16_ipd, A(15) => A15_ipd, A(14) => A14_ipd, A(13) => A13_ipd, A(12) => A12_ipd, A(11) => A11_ipd, A(10) => A10_ipd, A(9) => A9_ipd, A(8) => A8_ipd, A(7) => A7_ipd, A(6) => A6_ipd, A(5) => A5_ipd, A(4) => A4_ipd, A(3) => A3_ipd, A(2) => A2_ipd, A(1) => A1_ipd, A(0) => A0_ipd, DIn(15) => DQ15_ipd, DIn(14) => DQ14_ipd, DIn(13) => DQ13_ipd, DIn(12) => DQ12_ipd, DIn(11) => DQ11_ipd, DIn(10) => DQ10_ipd, DIn(9) => DQ9_ipd, DIn(8) => DQ8_ipd, DIn(7) => DQ7_ipd, DIn(6) => DQ6_ipd, DIn(5) => DQ5_ipd, DIn(4) => DQ4_ipd, DIn(3) => DQ3_ipd, DIn(2) => DQ2_ipd, DIn(1) => DQ1_ipd, DIn(0) => DQ0_ipd, DOut(15) => DQ15, DOut(14) => DQ14, DOut(13) => DQ13, DOut(12) => DQ12, DOut(11) => DQ11, DOut(10) => DQ10, DOut(9) => DQ9, DOut(8) => DQ8, DOut(7) => DQ7, DOut(6) => DQ6, DOut(5) => DQ5, DOut(4) => DQ4, DOut(3) => DQ3, DOut(2) => DQ2, DOut(1) => DQ1, DOut(0) => DQ0, CENeg => CENeg_ipd, OENeg => OENeg_ipd, WENeg => WENeg_ipd, RESETNeg => RESETNeg_ipd, WPNeg => WPNeg_ipd, RY => RY ); -- State Machine : State_Type TYPE state_type IS ( RESET, --initial state READUL1, --2nd bus write cycle READUL2, --3rd bus write cycle READSR, --Read Status Register BLCK, --Blanc Check PG1, --555/A0 PG, --PGMS PGSR, --Read status reg ER, --erase command ERSR, --erase command, Read Status Reg ERUL1, --2nd bus write cycle for erase ERUL2, --3rd bus write cycle CER, --chip erase SER, --sector erase ESR, --erase susp req,latency start ES, --erase suspend mode ESSR, --erase suspend, Rd Status Reg ESUL1, ESUL2, ESPG, --er susp, program(A0) ESPG1, --er susp, Word program ESPGSR, --erase susp,program,Rd Stat Reg ESPSR, --ersusp,progsusp req(tPSL start) ESPS, --er susp,prog susp mode ESPSSR, --er susp,prog susp mode,RdStat ESPSUL1, ESPSUL2, ESDYB, --er susp, DYB ASO ESDYBSET, --er susp, DYB SET/CLR ESDYBEXT, --er susp, DYB exit ES_WB, ES_WB_D, PSR, --program suspend latency start PS, --program suspend mode PSSR, --program susp mode,Rd Stat Reg WB, WB_D, PBF, WBUL1, WBUL2, ID_CFI, --ID-ID_CFI enter CFISR, --ID_CFI Read Status Register SSR, --Secure Silicon(SSR) SSRSR, --Secure Silicon, Rd Stat Reg SSRUL1, SSRUL2, SSREXT, --Secure Silicon(SSR) exit SSRPG1, SSRPG, SSR_WB, SSR_WB_D, LR, --Lock Register ASO LRSR, --Lock Register, Rd Status Reg LRPG1, LRPG, LREXT, --Lock Register ASO exit PP, --Password Protection Command Set PPSR, --Password Prot ASO , Rd Stat Reg PPPG1, PPPG, PPWB25, PPD, PASSUNLOCK3, PASSUNLOCK4, PASSUNLOCK5, PASSUNLOCK6, PASSUNLOCK, PPEXT, --Password Protection ASO exit PPB_ASO, --Non-Volatile Sec Prot. Command PPBSR, PPBPG1, PPBPG, PPBER, PPBEXT, PPBLB, --PPB Lock bit ASO PPBLBSR, --PPB Lock bit ASO,Rd Status Reg PPBLBPG1, PPBLBSET, --PPB Lock bit set PPBLBEXT, --PPB Lock bit ASO exit DYB_ASO, --DYB ASO DYBEXT, --DYB ASO exit DYBSET, --DYB ASO set/clr DYBSR --DYB-Read Status Register ); TYPE PASS_TYPE IS ARRAY(0 TO 3) OF std_logic_vector(15 downto 0); TYPE PassUnlockType IS ARRAY(0 TO 3) OF BOOLEAN; TYPE PgmsTargetType IS (MEMORY, SSR, PASSW, PPB_BIT, LREG ); SHARED VARIABLE Password : PASS_TYPE; SHARED VARIABLE LockReg : std_logic_vector(15 downto 0); SHARED VARIABLE StatusReg : std_logic_vector(15 downto 0) := "0000000010000000"; -- Protection parameters SHARED VARIABLE DYB : std_logic_vector(SecNum downto 0) := (OTHERS => '1'); SHARED VARIABLE PPB : std_logic_vector(SecNum downto 0) := (OTHERS => '1'); SHARED VARIABLE PPBLock : std_logic; -- states SIGNAL current_state : state_type; SIGNAL next_state : state_type; -- powerup SIGNAL PoweredUp : std_logic := '0'; --zero delay signals SIGNAL DOut_zd : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL DOut_Pass : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL RY_zd : std_logic := 'Z'; --FSM control signals SIGNAL CER_ACT : std_logic := '0'; SIGNAL SER_ACT : std_logic := '0'; SIGNAL STAT_ACT : std_logic := '0'; SIGNAL OTP_ACT : std_logic := '0'; --SecSi access SIGNAL PSP_ACT : std_logic := '0'; --Program Suspend SIGNAL ESP_ACT : std_logic := '0'; --Erase Suspend SIGNAL ESPG_ACT : std_logic := '0'; --Erase Suspend,prog activ SIGNAL ESR_ACT : std_logic := '0'; --Erase Suspend Latency SIGNAL ES_DYB_ACT : std_logic := '0'; --Erase Suspend, DYB SIGNAL PASS_ACT : std_logic := '0'; --Password access SIGNAL PPB_ACT : std_logic := '0'; --PPB access SIGNAL PPB_ACT_ER : std_logic := '0'; --PPB erase SIGNAL LOCK_ACT : std_logic := '0'; --Lock register access SIGNAL LCNT : NATURAL RANGE 0 TO 255:= 0; --Load Counter --number of location to be writen in Write Buffer: 0-255 word. --if 256 word programming SIGNAL PCNT : NATURAL RANGE 0 TO 256:= 0; SIGNAL PDONE : std_logic := '1'; --Prog. Done SIGNAL PSTART : std_logic := '0'; --Start Programming SIGNAL PSUSP : std_logic := '0'; --Suspend programming SIGNAL PRES : std_logic := '0'; --Resume Programming --Program location is in protected sector SIGNAL PERR : std_logic := '0'; SIGNAL EDONE : std_logic := '1'; --Ers. Done SIGNAL ESTART : std_logic := '0'; --Start Erase SIGNAL ESUSP : std_logic := '0'; --Suspend Erase SIGNAL ERES : std_logic := '0'; --Resume Erase --All sectors selected for erasure are protected SIGNAL EERR : std_logic := '0'; SIGNAL BCSTART : std_logic := '0'; --Blank Check Start SIGNAL BCDONE : std_logic := '1'; --Blank Check Done --Sectors selected for erasure SIGNAL ERS_QUEUE : std_logic_vector(SecNum downto 0) := (OTHERS => '0'); --Command Register SIGNAL write : std_logic := '0'; SIGNAL read : std_logic := '0'; --Sector Address SIGNAL SecAddr : NATURAL RANGE 0 TO SecNum := 0; SIGNAL SA : NATURAL RANGE 0 TO SecNum := 0; SIGNAL WBPage : NATURAL; --Address within sector SIGNAL Address : NATURAL RANGE 0 TO SecSize := 0; SIGNAL D_tmp : NATURAL RANGE 0 TO MaxData; SIGNAL D_tmp1 : NATURAL RANGE 0 TO 16#FFF#; --A21:A11 Don't Care SIGNAL Addr : NATURAL RANGE 0 TO 16#FFF# := 0; SIGNAL WPage : NATURAL RANGE 0 TO 16#FFF# := 0; SIGNAL RPage : NATURAL RANGE 0 TO 16#2000# := 0; SIGNAL RPChange : boolean := true; --glitch protection SIGNAL gWE_n : std_logic := 'U'; SIGNAL gCE_n : std_logic := 'U'; SIGNAL gOE_n : std_logic := 'U'; SIGNAL RST : std_logic := '1'; SIGNAL reseted : std_logic := '0'; --SecSi ProtectionStatus SIGNAL FactoryProt : std_logic := '1'; --x --SecSi Factory Address SIGNAL FactoryAddr : std_logic := '0'; --x -- timing check violation SIGNAL Viol : X01 := '0'; -- Address of the Protected Sector SIGNAL ProtSecNum : NATURAL ; -- Access time variables SHARED VARIABLE OPENLATCH : BOOLEAN; SHARED VARIABLE FROMCE : BOOLEAN; SHARED VARIABLE FROMOE : BOOLEAN; FUNCTION READMEM(Data : INTEGER RANGE -1 TO MaxData) RETURN STD_LOGIC_VECTOR IS VARIABLE ReadData : STD_LOGIC_VECTOR(15 downto 0); BEGIN IF Data = -1 THEN ReadData := (OTHERS=>'X'); ELSE ReadData := to_slv(Data,16); END IF; RETURN ReadData; END READMEM; BEGIN --------------------------------------------------------------------------- --protected sector --------------------------------------------------------------------------- ProtSecNum <= 127 WHEN TimingModel(16) = '1' ELSE 0; --------------------------------------------------------------------------- --Power Up time 300 us; --------------------------------------------------------------------------- PoweredUp <= '1' AFTER 300 us; RST <= RESETNeg AFTER 200 ns; --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS(A, Din, CENeg, OENeg, WENeg, RESETNeg, WPNeg) -- Timing Check Variables --Setup/Hold Check Variables VARIABLE Tviol_A0_CENeg_F : X01 := '0'; VARIABLE TD_A0_CENeg_F : VitalTimingDataType; VARIABLE Tviol_A0_WENeg : X01 := '0'; VARIABLE TD_A0_WENeg : VitalTimingDataType; VARIABLE Tviol_DQ0_CENeg : X01 := '0'; VARIABLE TD_DQ0_CENeg : VitalTimingDataType; VARIABLE Tviol_DQ0_WENeg : X01 := '0'; VARIABLE TD_DQ0_WENeg : VitalTimingDataType; VARIABLE Tviol_A0_OENeg_F : X01 := '0'; VARIABLE TD_A0_OENeg_F : VitalTimingDataType; VARIABLE Tviol_CENeg_WENeg_F : X01 := '0'; VARIABLE TD_CENeg_WENeg_F : VitalTimingDataType; VARIABLE Tviol_A0_OENeg_R : X01 := '0'; VARIABLE TD_A0_OENeg_R : VitalTimingDataType; VARIABLE Tviol_A0_CENeg_R : X01 := '0'; VARIABLE TD_A0_CENeg_R : VitalTimingDataType; VARIABLE Tviol_CENeg_RESETNeg : X01 := '0'; VARIABLE TD_CENeg_RESETNeg : VitalTimingDataType; VARIABLE Tviol_WENeg_RESETNeg : X01 := '0'; VARIABLE TD_WENeg_RESETNeg : VitalTimingDataType; VARIABLE Tviol_OENeg_WENeg : X01 := '0'; VARIABLE TD_OENeg_WENeg : VitalTimingDataType; VARIABLE Tviol_WENeg_OENeg : X01 := '0'; VARIABLE TD_WENeg_OENeg : VitalTimingDataType; VARIABLE Tviol_CENeg_WENeg_R : X01 := '0'; VARIABLE TD_CENeg_WENeg_R : VitalTimingDataType; --Pulse Width and Period Check Variables VARIABLE Pviol_RESETNeg : X01 := '0'; VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_OENeg : X01 := '0'; VARIABLE PD_OENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CENeg : X01 := '0'; VARIABLE PD_CENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg : X01 := '0'; VARIABLE PD_WENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A0 : X01 := '0'; VARIABLE PD_A0 : VitalPeriodDataType := VitalPeriodDataInit; --Functionality Results Variables --(used to OR all individual violations) VARIABLE Violation : X01 := '0'; BEGIN --------------------------------------------------------------------------- -- Timing Check Section --------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Setup/Hold Check between A and CENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => CENeg, RefSignalName => "CE#", SetupHigh => tsetup_A0_CENeg, SetupLow => tsetup_A0_CENeg, HoldHigh => thold_A0_CENeg, HoldLow => thold_A0_CENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CENeg_F, Violation => Tviol_A0_CENeg_F ); -- Setup/Hold Check between A and WENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => tsetup_A0_CENeg, SetupLow => tsetup_A0_CENeg, HoldHigh => thold_A0_CENeg, HoldLow => thold_A0_CENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_WENeg, Violation => Tviol_A0_WENeg ); -- Setup/Hold Check between DQ and CENeg VitalSetupHoldCheck ( TestSignal => DQ0, TestSignalName => "DQ", RefSignal => CENeg, RefSignalName => "CE#", SetupHigh => tsetup_DQ0_CENeg, SetupLow => tsetup_DQ0_CENeg, HoldHigh => thold_DQ0_CENeg, HoldLow => thold_DQ0_CENeg, CheckEnabled => DIn(15 downto 0)/=DOut_zd(15 downto 0), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_CENeg, Violation => Tviol_DQ0_CENeg ); -- Setup/Hold Check between DQ and WENeg VitalSetupHoldCheck ( TestSignal => DQ0, TestSignalName => "DQ", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => tsetup_DQ0_CENeg, SetupLow => tsetup_DQ0_CENeg, HoldHigh => thold_DQ0_CENeg, HoldLow => thold_DQ0_CENeg, CheckEnabled => DIn(15 downto 0)/=DOut_zd(15 downto 0), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_WENeg, Violation => Tviol_DQ0_WENeg ); -- Setup Check between A and OENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => OENeg, RefSignalName => "OE#", SetupHigh => tsetup_A0_OENeg, SetupLow => tsetup_A0_OENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_OENeg_F, Violation => Tviol_A0_OENeg_F ); -- Setup Check between CENeg and WENeg VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CE#", RefSignal => WENeg, RefSignalName => "WE#", SetupLow => tsetup_CENeg_WENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_WENeg_F, Violation => Tviol_CENeg_WENeg_F ); -- Hold Check between A and OENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => OENeg, RefSignalName => "OE#", HoldHigh => thold_A0_OENeg, HoldLow => thold_A0_OENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_OENeg_R, Violation => Tviol_A0_OENeg_R ); -- Hold Check between A and CENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => CENeg, RefSignalName => "CE#", HoldHigh => thold_A0_OENeg, HoldLow => thold_A0_OENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CENeg_R, Violation => Tviol_A0_CENeg_R ); -- Hold Check between CENeg and RESETNeg VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CE#", RefSignal => RESETNeg, RefSignalName => "RESET#", HoldHigh => thold_CENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_RESETNeg, Violation => Tviol_CENeg_RESETNeg ); -- Hold Check between WENeg and RESETNeg VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WE#", RefSignal => RESETNeg, RefSignalName => "RESET#", HoldHigh => thold_CENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_RESETNeg, Violation => Tviol_WENeg_RESETNeg ); -- Hold Check between OENeg and WENeg VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OE#", RefSignal => WENeg, RefSignalName => "WE#", HoldHigh => thold_OENeg_WENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_WENeg, Violation => Tviol_OENeg_WENeg ); -- Hold Check between WENeg and OENeg VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WE#", RefSignal => OENeg, RefSignalName => "OE#", HoldHigh => thold_WENeg_OENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_OENeg, Violation => Tviol_WENeg_OENeg ); -- Setup/Hold Check between CENeg and WENeg VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CE#", RefSignal => WENeg, RefSignalName => "WE#", HoldLow => thold_CENeg_WENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_WENeg_R, Violation => Tviol_CENeg_WENeg_R ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESET#", PulseWidthLow => tpw_RESETNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg, Violation => Pviol_RESETNeg ); -- PulseWidth Check for OENeg VitalPeriodPulseCheck ( TestSignal => OENeg, TestSignalName => "OE#", PulseWidthHigh => tpw_OENeg_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_OENeg, Violation => Pviol_OENeg ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WE#", PulseWidthHigh => tpw_WENeg_posedge, PulseWidthLow => tpw_WENeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg, Violation => Pviol_WENeg ); -- PulseWidth Check for CENeg VitalPeriodPulseCheck ( TestSignal => CENeg, TestSignalName => "CE#", PulseWidthHigh => tpw_CENeg_posedge, PulseWidthLow => tpw_CENeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_CENeg, Violation => Pviol_CENeg ); -- PulseWidth Check for A VitalPeriodPulseCheck ( TestSignal => A(0), TestSignalName => "A", PulseWidthHigh => tpw_A0_negedge, PulseWidthLow => tpw_A0_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_A0, Violation => Pviol_A0 ); Violation := Tviol_A0_CENeg_F OR Tviol_A0_WENeg OR Tviol_DQ0_CENeg OR Tviol_DQ0_WENeg OR Tviol_A0_OENeg_F OR Tviol_CENeg_WENeg_F OR Tviol_A0_OENeg_R OR Tviol_A0_CENeg_R OR Tviol_CENeg_RESETNeg OR Tviol_WENeg_RESETNeg OR Tviol_OENeg_WENeg OR Tviol_WENeg_OENeg OR Tviol_CENeg_WENeg_R OR Pviol_RESETNeg OR Pviol_OENeg OR Pviol_CENeg OR Pviol_WENeg OR Pviol_A0 ; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS VITALTimingCheck; ---------------------------------------------------------------------------- -- sequential process for reset control and FSM state transition ---------------------------------------------------------------------------- StateTransition : PROCESS(next_state, RESETNeg, RST, sREADY, PDONE, EDONE, PoweredUp) VARIABLE R : std_logic := '0'; --prog or erase in progress VARIABLE E : std_logic := '0'; --reset timming error BEGIN IF PoweredUp = '1' THEN --Hardware reset timing control IF falling_edge(RESETNeg) THEN E := '0'; IF (PDONE = '0' OR EDONE = '0') THEN --if program or erase in progress READY_in <= '1'; R := '1'; ELSE READY_in <= '0'; R := '0'; --prog or erase not in progress END IF; ELSIF rising_edge(RESETNeg) AND RST = '1' THEN --RESET# pulse < tRP READY_in <= '0'; R := '0'; E := '1'; END IF; IF RESETNeg = '1' AND ( R = '0' OR (R = '1' AND sREADY = '1')) THEN current_state <= next_state; READY_in <= '0'; E := '0'; R := '0'; reseted <= '1'; ELSIF (R = '0' AND RESETNeg = '0' AND RST = '0') OR (R = '1' AND RESETNeg = '0' AND RST = '0' AND sREADY = '0') OR (R = '1' AND RESETNeg = '1' AND RST = '0' AND sREADY = '0') THEN --no state transition while RESET# low current_state <= RESET; --reset start reseted <= '0'; END IF; ELSE current_state <= RESET; -- reset reseted <= '0'; E := '0'; R := '0'; END IF; END PROCESS StateTransition; --------------------------------------------------------------------------- --Glitch Protection: Inertial Delay does not propagate pulses <5ns --------------------------------------------------------------------------- gWE_n <= WENeg AFTER 5 ns; gCE_n <= CENeg AFTER 5 ns; gOE_n <= OENeg AFTER 5 ns; --latch address on rising edge and data on falling edge of write write_dc: PROCESS (gWE_n, gCE_n, gOE_n, RESETNeg, reseted) BEGIN IF RESETNeg /= '0' AND reseted ='1' THEN IF (gWE_n = '0') AND (gCE_n = '0') AND (gOE_n = '1') THEN write <= '1'; ELSIF (gWE_n = '1' OR gCE_n = '1') AND gOE_n = '1' THEN write <= '0'; ELSE write <= 'X'; END IF; END IF; IF ((gWE_n = '1') AND (gCE_n = '0') AND (gOE_n = '0')) THEN read <= '1'; ELSE read <= '0'; END IF; END PROCESS write_dc; --------------------------------------------------------------------------- --Process that reports warning when changes on signals WE#, CE#, OE# are --discarded --------------------------------------------------------------------------- PulseWatch : PROCESS (WENeg, CENeg, OENeg, gWE_n, gCE_n, gOE_n) BEGIN IF (gWE_n'EVENT AND (gWE_n /= WENeg)) OR (gCE_n'EVENT AND (gCE_n /= CENeg)) OR (gOE_n'EVENT AND (gOE_n /= OENeg)) THEN ASSERT false REPORT "Glitch detected on write control signals" SEVERITY warning; END IF; END PROCESS PulseWatch; ---------------------------------------------------------------------------- -- Device internal operation control ---------------------------------------------------------------------------- -- configuring the PPB Lock Bit to the freeze state ProtPROG : PROCESS(PBPROG_in) BEGIN IF PBPROG_in = '0' THEN PBPROG_out <= '0'; ELSE IF LongTimming = TRUE THEN PBPROG_out <= '1' AFTER (tdevice_PPBLOCK - 1 ns); ELSE PBPROG_out <= '1' AFTER (tdevice_PPBLOCK - 1 ns)/1; END IF; END IF; END PROCESS ProtPROG; UNL : PROCESS(UNLOCKDONE_in) BEGIN IF UNLOCKDONE_in = '0' THEN UNLOCKDONE_out <= '0'; ELSE IF LongTimming = TRUE THEN UNLOCKDONE_out <= '1' AFTER (tdevice_UNLOCK- 1 ns); ELSE UNLOCKDONE_out <= '1' AFTER (tdevice_UNLOCK- 1 ns)/1; END IF; END IF; END PROCESS UNL; --------------------------------------------------------------------------- -- Latch address on falling edge of WE# or CE# what ever comes later -- Latches data on rising edge of WE# or CE# what ever comes first -- also Write cycle decode --------------------------------------------------------------------------- BusCycleDecode : PROCESS(A, Din, write, WENeg, CENeg, OENeg, reseted, read) VARIABLE A_tmp : NATURAL RANGE 0 TO 16#FFF#; VARIABLE SA_tmp : NATURAL RANGE 0 TO SecNum; VARIABLE A_tmp1 : NATURAL RANGE 0 TO SecSize; VARIABLE CE : std_logic; BEGIN IF reseted = '1' THEN IF (falling_edge(WENeg) AND CENeg ='0' AND OENeg = '1') OR (falling_edge(CENeg) AND WENeg/= OENeg ) OR (falling_edge(OENeg) AND WENeg ='1' AND CENeg = '0') OR (A'EVENT AND WENeg = '1' AND CENeg = '0' AND OENeg = '0') THEN A_tmp := to_nat(A(11 downto 0)); SA_tmp := to_nat(A(HiAddrBit downto 16)); A_tmp1 := to_nat(A(15 downto 0)); ELSIF (rising_edge(WENeg) OR rising_edge(CENeg)) AND write = '1' THEN D_tmp <= to_nat(Din(15 downto 0)); D_tmp1 <= to_nat(Din(8 downto 0)); END IF; IF rising_edge(write) OR rising_edge(read) OR falling_edge(OENeg) OR (A'EVENT AND WENeg = '1' AND CENeg = '0' AND OENeg = '0') THEN SecAddr <= SA_tmp; Address <= A_tmp1; WPage <= A_tmp1 / 256; IF (RPage /= (A_tmp1 / 16)) OR (CENeg /= CE) THEN RPchange <= true; ELSE RPchange <= false; END IF; RPage <= A_tmp1 / 16; CE := CENeg; Addr <= A_tmp; END IF; END IF; END PROCESS BusCycleDecode; --------------------------------------------------------------------------- -- Timing control for the Program/ Write Buffer Program Operations -- start/ suspend/ resume --------------------------------------------------------------------------- ProgTime : PROCESS(PSTART, PSUSP, PRES, reseted) VARIABLE cnt : NATURAL RANGE 0 TO 256 := 0; VARIABLE elapsed : time; VARIABLE duration : time; VARIABLE start : time; VARIABLE pow : time; VARIABLE wbpb : time; BEGIN IF LongTimming THEN pow := tdevice_POW; wbpb := tdevice_WBPBW;--per word ELSE pow := tdevice_POW / 1; wbpb := tdevice_WBPBW / 1; --per word END IF; IF rising_edge(reseted) THEN PDONE <= '1'; -- reset done, programing immediately terminated ELSIF reseted = '1' THEN IF rising_edge(PSTART) AND PDONE = '1' THEN IF NOT( ((DYB(SA) = '0' OR PPB(SA) = '0') AND OTP_ACT = '0' AND PPB_ACT = '0' AND LOCK_ACT = '0' AND PASS_ACT = '0') OR --password protection mode (PASS_ACT = '1' AND LockReg(2) = '0') OR (Ers_queue(SA) = '1' AND ESP_ACT = '1') OR (LockReg(6) = '0' AND OTP_ACT = '1') OR (FactoryAddr = '1' AND OTP_ACT = '1') OR (WPNeg = '0' AND (SA = ProtSecNum)) )THEN IF PCNT < 256 THEN --buffer cnt := PCNT + 1; duration := cnt * wbpb; ELSE --Word program cnt := 1; duration := cnt * pow; --per word END IF; elapsed := 0 ns; PDONE <= '0', '1' AFTER duration; start := NOW; ELSE PERR <= '1', '0' AFTER 20 us; END IF; ELSIF rising_edge(PSUSP) AND PDONE = '0' THEN elapsed := NOW - start; duration := duration - elapsed; PDONE <= '0'; ELSIF rising_edge(PRES) AND PDONE = '0' THEN start := NOW; PDONE <= '0', '1' AFTER duration; END IF; END IF; END PROCESS ProgTime; --------------------------------------------------------------------------- -- Timing control for the Blank Check --------------------------------------------------------------------------- BCTime :PROCESS(BCSTART, reseted) VARIABLE bco : time; BEGIN IF LongTimming THEN bco := tdevice_BC; ELSE bco := tdevice_BC / 1000; END IF; IF reseted = '1' THEN IF rising_edge(BCSTART) AND BCDONE = '1' THEN BCDONE <= '0', '1' AFTER bco; END IF; END IF; END PROCESS; --------------------------------------------------------------------------- -- Timing control for the Erase Operations --------------------------------------------------------------------------- ErsTime :PROCESS(ESTART, ESUSP, ERES, Ers_Queue, reseted) VARIABLE cnt : NATURAL RANGE 0 TO SecNum + 1 := 0; VARIABLE elapsed : time; VARIABLE duration : time; VARIABLE start : time; VARIABLE seo : time; VARIABLE bco : time; BEGIN IF LongTimming THEN seo := tdevice_SEO; ELSE seo := tdevice_SEO / 10; END IF; IF rising_edge(reseted) THEN EDONE <= '1'; -- reset done, ERASE immediately terminated ELSIF reseted = '1' THEN IF rising_edge(ESTART) AND EDONE = '1' THEN cnt := 0; FOR i IN Ers_Queue'RANGE LOOP IF (Ers_Queue(i) = '1' AND DYB(i) = '1' AND PPB(i) = '1' AND NOT(WPNeg = '0' AND (SA = ProtSecNum)) AND PPB_ACT = '0') THEN cnt := cnt + 1; END IF; END LOOP; IF PPB_ACT = '1' THEN cnt := 1; END IF; IF cnt > 0 THEN elapsed := 0 ns; duration := cnt * seo; EDONE <= '0', '1' AFTER duration; start := NOW; ELSE EERR <= '1', '0' AFTER 100 us; END IF; ELSIF rising_edge(ESUSP) AND EDONE = '0' THEN elapsed := NOW - start; duration := duration - elapsed; EDONE <= '0'; ELSIF rising_edge(ERES) AND EDONE = '0' THEN start := NOW; EDONE <= '0', '1' AFTER duration; END IF; END IF; END PROCESS; --------------------------------------------------------------------------- -- Main Behavior Process -- combinational process for next state generation --------------------------------------------------------------------------- StateGen :PROCESS(write, Addr, D_tmp1, PDONE, EDONE, BCDONE, sSTART_T1, reseted, sREADY, PERR, EERR, STAT_ACT, RST, UNLOCKDONE_out, PBPROG_out ) VARIABLE PATTERN_1 : boolean := FALSE; VARIABLE PATTERN_2 : boolean := FALSE; VARIABLE A_PAT_1 : boolean := FALSE; VARIABLE BUFF_FLAG : BOOLEAN := FALSE; --DATA Low Byte VARIABLE DataLo : NATURAL RANGE 0 TO 16#FFF# := 0; VARIABLE tempLR : std_logic_vector(15 downto 0); --DATA WORD VARIABLE Data : NATURAL RANGE 0 TO MaxData := 0; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(write) THEN DataLo := D_tmp1; Data := D_tmp; PATTERN_1 := (Addr=16#555#) AND (DataLo = 16#AA#) ; PATTERN_2 := (Addr=16#2AA#) AND (DataLo = 16#55#) ; A_PAT_1 := (Addr=16#555#); END IF; IF falling_edge(RST) AND RESETNeg = '0' THEN LOCK_ACT <= '0'; PPB_ACT <= '0'; END IF; IF reseted /= '1' THEN next_state <= current_state; ELSE CASE current_state IS WHEN RESET => IF falling_edge(write) THEN IF (PATTERN_1) THEN next_state <= READUL1; ELSIF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= READSR; ELSIF (A_PAT_1 AND (DataLo=16#33#)) THEN next_state <= BLCK; ELSIF ((Addr=16#55#) AND (DataLo=16#98#))THEN next_state <= ID_CFI; ELSE next_state <= RESET; END IF; END IF; WHEN READUL1 => IF falling_edge(write) THEN IF (PATTERN_2) THEN next_state <= READUL2; ELSIF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= READSR; ELSE next_state <= RESET; END IF; END IF; WHEN READUL2 => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#A0#)) THEN next_state <= PG1; ELSIF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= READSR; ELSIF (DataLo=16#25#) THEN next_state <= WB; ELSIF (A_PAT_1 AND (DataLo=16#80#)) THEN next_state <= ER; ELSIF (A_PAT_1 AND (DataLo=16#90#)) THEN next_state <= ID_CFI; ELSIF (A_PAT_1 AND (DataLo=16#88#)) THEN next_state <= SSR; ELSIF (A_PAT_1 AND (DataLo = 16#40#)) THEN next_state <= LR; LOCK_ACT <= '1'; ELSIF (A_PAT_1 AND (DataLo = 16#60#)) THEN next_state <= PP; PASS_ACT <= '1'; ELSIF (A_PAT_1 AND (DataLo = 16#C0#)) THEN PPB_ACT <= '1'; next_state <= PPB_ASO; ELSIF (A_PAT_1 AND (DataLo = 16#50#)) THEN next_state <= PPBLB; ELSIF (A_PAT_1 AND (DataLo = 16#E0#)) THEN next_state <= DYB_ASO; ELSE next_state <= RESET; END IF; END IF; WHEN READSR => IF (STAT_ACT = '0') THEN next_state <= RESET; ELSE next_state <= READSR; END IF; WHEN PG1 => IF falling_edge(write) THEN next_state <= PG; ELSE next_state <= PG1; END IF; WHEN WB => IF falling_edge(write) THEN IF (SecAddr = SA) AND Data < 256 THEN next_state <= WB_D; BUFF_FLAG:= TRUE; ELSE next_state <= PG; --ABORT END IF; END IF; WHEN WB_D => IF falling_edge(write) THEN IF BUFF_FLAG THEN BUFF_FLAG:= FALSE; IF (SecAddr = SA) THEN -- fix WriteBufferPage WBPage IF (LCNT > 0) THEN next_state <= WB_D; ELSE next_state <= PBF; END IF; ELSE next_state <= PG; --ABORT END IF; ELSE IF (WPage = WBPage) THEN -- fix WriteBufferPage WBPage IF (LCNT > 0) THEN next_state <= WB_D; ELSE next_state <= PBF; END IF; ELSE next_state <= PG; --ABORT END IF; END IF; END IF; WHEN PBF => IF falling_edge(write) THEN IF (SecAddr = SA) AND (DataLo = 16#29#) THEN IF OTP_ACT= '1' THEN next_state <= SSRPG; ELSIF ESP_ACT = '1' THEN next_state <= ESPG; ELSE next_state <= PG; END IF; ELSE IF OTP_ACT= '1' THEN next_state <= SSRPG; ELSIF ESP_ACT = '1' THEN next_state <= ESPG; ELSE next_state <= PG; --ABORT END IF; END IF; END IF; WHEN PG => IF rising_edge(PDONE) OR falling_edge(PERR) THEN next_state <= RESET; ELSIF falling_edge(write) THEN IF (A_PAT_1 AND DataLo=16#70#) THEN next_state <= PGSR; ELSIF (((Addr=16#555# AND DataLo = 16#71#) OR (DataLo = 16#F0#)) AND StatusReg(7) = '1') THEN next_state <= RESET; END IF; IF PERR /= '1' THEN IF ( DataLo = 16#51#) THEN next_state <= PSR; ELSIF (PATTERN_1 AND StatusReg(7) = '1') THEN next_state <= WBUL1; END IF; END IF; END IF; WHEN PGSR => IF (STAT_ACT = '0') THEN IF (PDONE= '0') THEN IF PSUSP = '1' THEN next_state <= PSR; ELSE next_state <= PG; END IF; ELSE next_state <= RESET; END IF; ELSE next_state <= PGSR; END IF; WHEN WBUL1 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= WBUL2; ELSIF ((NOT(Addr=16#2AA#) OR NOT(DataLo = 16#55#)) AND StatusReg(3) = '1') THEN next_state <= PG; END IF; END IF; WHEN WBUL2 => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN next_state <= RESET; ELSIF ((NOT(Addr=16#555#) OR NOT(DataLo = 16#F0#)) AND StatusReg(3) = '1') THEN next_state <= PG; END IF; END IF; WHEN ID_CFI => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= CFISR; ELSIF (DataLo=16#F0#) THEN next_state <= RESET; ELSE next_state <= ID_CFI; END IF; END IF; WHEN CFISR => IF (STAT_ACT = '0') THEN next_state <= ID_CFI; ELSE next_state <= CFISR; END IF; WHEN ER => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= READSR; ELSIF PATTERN_1 THEN next_state <= ERUL1; ELSE next_state <= RESET; END IF; END IF; WHEN ERUL1 => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= READSR; ELSIF PATTERN_2 THEN next_state <= ERUL2; ELSE next_state <= RESET; END IF; END IF; WHEN ERUL2 => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= READSR; ELSIF ( A_PAT_1 AND DataLo=16#10# ) THEN next_state <= CER; CER_ACT <= '1'; ELSIF DataLo=16#30# THEN next_state <= SER; SER_ACT <= '1'; ELSE next_state <= RESET; END IF; END IF; WHEN CER => IF (falling_edge(write) AND A_PAT_1 AND DataLo=16#70#) THEN next_state <= ERSR; ELSIF rising_edge(EDONE) OR falling_edge(EERR) THEN next_state <= RESET; CER_ACT <= '0'; END IF; WHEN SER => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= ERSR; ELSIF ( DataLo=16#B0# AND EERR /= '1') THEN next_state <= ESR; ESR_ACT <= '1'; ELSIF ((DataLo=16#F0# OR (Addr = 16#555# AND DataLo = 16#71#)) AND StatusReg(7) = '1') THEN next_state <= RESET; SER_ACT <= '0'; END IF; ELSIF rising_edge(EDONE) OR falling_edge(EERR) THEN next_state <= RESET; SER_ACT <= '0'; END IF; WHEN BLCK => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= ERSR; ELSIF (((Addr=16#555# AND DataLo = 16#71#) OR (DataLo = 16#F0#)) AND StatusReg(7) = '1') THEN next_state <= RESET; END IF; ELSIF rising_edge(BCDONE) THEN next_state <= RESET; END IF; WHEN ERSR => IF (STAT_ACT = '0') THEN IF (CER_ACT = '1') THEN next_state <= CER; ELSIF (SER_ACT = '1' AND ESR_ACT = '0') THEN next_state <= SER; ELSIF (ESR_ACT = '1') THEN next_state <= ESR; ELSE next_state <= BLCK; END IF; ELSE next_state <= ERSR; END IF; WHEN ESR => IF (falling_edge(write) AND (A_PAT_1 AND (DataLo=16#70#))) THEN next_state <= ERSR; ELSIF (sSTART_T1 = '1') THEN next_state <= ES; ESR_ACT <= '0'; END IF; WHEN ES => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= ESSR; ELSIF (DataLo = 16#30#) THEN next_state <= SER; SER_ACT <= '1'; ELSIF PATTERN_1 THEN next_state <= ESUL1; END IF; END IF; WHEN ESSR => IF (STAT_ACT = '0') THEN IF (ES_DYB_ACT = '1') THEN next_state <= ESDYB; ELSE next_state <= ES; END IF; ELSE next_state <= ESSR; END IF; WHEN ESUL1 => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= ESSR; ELSIF PATTERN_2 THEN next_state <= ESUL2; ELSIF ((NOT(Addr=16#2AA#) OR NOT(DataLo = 16#55#)) AND StatusReg(3) = '1') THEN next_state <= ESPG; END IF; END IF; WHEN ESUL2 => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= ESSR; ELSIF DataLo = 16#25# THEN --fix SA next_state <= ES_WB; ELSIF A_PAT_1 AND DataLo = 16#A0# THEN next_state <= ESPG1; ELSIF (A_PAT_1 AND (DataLo = 16#E0#)) THEN next_state <= ESDYB; ES_DYB_ACT <= '1'; ELSIF (A_PAT_1 AND DataLo = 16#F0#) THEN next_state <= ES; ELSIF DataLo = 16#30# THEN next_state <= SER; SER_ACT <= '1'; ELSIF ((Addr/=16#555# OR DataLo /= 16#F0#) AND StatusReg(3) = '1') THEN next_state <= ESPG; END IF; END IF; WHEN ES_WB => IF falling_edge(write) THEN IF (SecAddr = SA) AND Data < 256 THEN next_state <= ES_WB_D; BUFF_FLAG:= TRUE; ELSE next_state <= ESPG; --ABORT END IF; END IF; WHEN ES_WB_D => IF falling_edge(write) THEN IF BUFF_FLAG THEN BUFF_FLAG:= FALSE; IF (SecAddr = SA) THEN -- fix WriteBufferPage WBPage IF (LCNT > 0) THEN next_state <= ES_WB_D; ELSE next_state <= PBF; END IF; ELSE next_state <= ESPG; --ABORT END IF; ELSE IF (WPage = WBPage) THEN -- fix WriteBufferPage WBPage IF (LCNT > 0) THEN next_state <= ES_WB_D; ELSE next_state <= PBF; END IF; ELSE next_state <= ESPG; --ABORT END IF; END IF; END IF; WHEN ESPG1 => IF falling_edge(write) THEN next_state <= ESPG; ELSE next_state <= ESPG1; END IF; WHEN ESPG => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= ESPGSR; ESPG_ACT <= '1'; ELSIF (((Addr=16#555# AND DataLo = 16#71#) OR (DataLo = 16#F0#)) AND StatusReg(7) = '1') THEN next_state <= ES; ELSIF ( PATTERN_1) THEN next_state <= ESUL1; ELSIF (DataLo = 16#B0# OR DataLo = 16#51#) THEN next_state <= ESPSR; END IF; ELSIF (rising_edge(PDONE) OR falling_edge(PERR)) THEN next_state <= ES; END IF; WHEN ESPGSR => IF (STAT_ACT = '0') THEN IF (ESPG_ACT = '1') THEN next_state <= ESPG; ESPG_ACT <= '0'; ELSE next_state <= ESPSR; END IF; ELSIF falling_edge(write) THEN next_state <= ESPG; ESPG_ACT <= '0'; ELSE next_state <= ESPGSR; END IF; WHEN ESPSR => IF (falling_edge(write) AND (A_PAT_1 AND (DataLo=16#70#))) THEN next_state <= ESPGSR; ELSIF (sSTART_T1 = '1') THEN next_state <= ESPS; END IF; WHEN ESPS => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= ESPSSR; ELSIF (DataLo = 16#30# OR DataLo = 16#50#) THEN next_state <= ESPG; ELSIF PATTERN_1 THEN next_state <= ESPSUL1; ELSIF (DataLo = 16#F0# OR (A_PAT_1 AND DataLo=16#71#))THEN next_state <= ESPS; END IF; END IF; WHEN ESPSSR => IF (STAT_ACT = '0') THEN next_state <= ESPS; ELSE next_state <= ESPSSR; END IF; WHEN ESPSUL1 => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= ESPSSR; ELSIF PATTERN_2 THEN next_state <= ESPSUL2; END IF; END IF; WHEN ESPSUL2 => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= ESPSSR; ELSIF (DataLo = 16#30# OR DataLo = 16#50#) THEN next_state <= ESPG; END IF; END IF; WHEN ESDYB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= ESSR; ELSIF (DataLo = 16#A0#) THEN next_state <= ESDYBSET; ELSIF (DataLo = 16#90#) THEN next_state <= ESDYBEXT; ELSIF (DataLo = 16#F0#) THEN next_state <= ES; ES_DYB_ACT <= '0'; END IF; END IF; WHEN ESDYBSET => IF falling_edge(write) THEN next_state <= ESDYB; END IF; WHEN ESDYBEXT => IF falling_edge(write) THEN IF (DataLo = 16#00# OR DataLo = 16#03#) THEN next_state <= ES; ES_DYB_ACT <= '0'; ELSE next_state <= ESDYB; END IF; END IF; WHEN PSR => IF (falling_edge(write) AND A_PAT_1 AND DataLo=16#70#) THEN next_state <= PGSR; ELSIF sSTART_T1 = '1' THEN next_state <= PS; END IF; WHEN PS => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= PSSR; ELSIF (DataLo = 16#50# OR DataLo = 16#30#) THEN next_state <= PG; END IF; END IF; WHEN PSSR => IF (STAT_ACT = '0') THEN next_state <= PS; ELSE next_state <= PSSR; END IF; WHEN SSR => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= SSRSR; ELSIF PATTERN_1 THEN next_state <= SSRUL1; ELSIF DataLo=16#F0# THEN next_state <= RESET; ELSE next_state <= SSR; END IF; END IF; WHEN SSRUL1 => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= SSRSR; ELSIF PATTERN_2 THEN next_state <= SSRUL2; ELSIF (((Addr/=16#2AA#) OR (DataLo /= 16#55#)) AND StatusReg(3) = '1') THEN next_state <= SSRPG; ELSIF DataLo=16#F0# THEN next_state <= RESET; ELSE next_state <= SSR; END IF; END IF; WHEN SSRUL2 => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#A0#))THEN next_state <= SSRPG1; ELSIF DataLo = 16#25# THEN --fix Sector Address SA next_state <= SSR_WB; ELSIF (A_PAT_1 AND (DataLo = 16#90#))THEN next_state <= SSREXT; ELSIF (((Addr/=16#555#) OR (DataLo /= 16#F0#)) AND StatusReg(3) = '1') THEN next_state <= SSRPG; ELSIF DataLo=16#F0# THEN next_state <= SSR; ELSE next_state <= SSR; END IF; END IF; WHEN SSR_WB => IF falling_edge(write) THEN next_state <= SSR_WB_D; BUFF_FLAG:= TRUE; END IF; WHEN SSR_WB_D => IF falling_edge(write) THEN IF BUFF_FLAG THEN BUFF_FLAG:= FALSE; IF (SecAddr = SA) THEN -- fix WriteBufferPage WBPage next_state <= SSR_WB_D; ELSE next_state <= SSRPG; --ABORT END IF; ELSE IF (WPage = WBPage) THEN -- fix WriteBufferPage WBPage IF (LCNT > 0) THEN next_state <= SSR_WB_D; ELSE next_state <= PBF; END IF; ELSE next_state <= SSRPG; --ABORT END IF; END IF; END IF; WHEN SSRPG => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= SSRSR; ELSIF (A_PAT_1 AND DataLo=16#71# AND StatusReg(7) = '1' ) THEN next_state <= SSR; ELSIF (PATTERN_1) THEN next_state <= SSRUL1; ELSIF (DataLo=16#F0#) THEN next_state <= RESET; END IF; ELSIF rising_edge(PDONE) OR falling_edge(PERR) THEN next_state <= SSR; END IF; WHEN SSRSR => IF (STAT_ACT = '0') THEN IF (PDONE = '0') THEN next_state <= SSRPG; ELSE next_state <= SSR; END IF; END IF; WHEN SSREXT => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN next_state <= RESET; ELSE next_state <= SSR; END IF; END IF; WHEN SSRPG1 => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#71#)) THEN next_state <= SSRPG1; ELSE next_state <= SSRPG; --set SS END IF; ELSE next_state <= SSRPG1; END IF; WHEN LR => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= LRSR; ELSIF (DataLo = 16#A0#) THEN next_state <= LRPG1; ELSIF (DataLo = 16#90#) THEN next_state <= LREXT; ELSIF (DataLo = 16#F0#) THEN LOCK_ACT <= '0'; next_state <= RESET; END IF; END IF; WHEN LRSR => IF (STAT_ACT = '0') THEN IF (PDONE= '0') THEN next_state <= LRPG; ELSE next_state <= LR; END IF; ELSE next_state <= LRSR; END IF; WHEN LRPG1 => IF falling_edge(write) THEN tempLR := to_slv(DataLo,16); IF NOT (tempLR(1) = '0' AND tempLR(2) = '0') THEN next_state <= LRPG; ELSE next_state <= LR; END IF; END IF; WHEN LRPG => IF (falling_edge(write) AND A_PAT_1 AND DataLo=16#70#) THEN next_state <= LRSR; ELSIF rising_edge(PDONE) OR falling_edge(PERR) THEN next_state <= LR; END IF; WHEN LREXT => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN next_state <= RESET; LOCK_ACT <= '0'; ELSE next_state <= LR; END IF; END IF; WHEN PP => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= PPSR; ELSIF (DataLo = 16#A0#) THEN next_state <= PPPG1; ELSIF (DataLo = 16#90#) THEN next_state <= PPEXT; ELSIF (DataLo = 16#F0#) THEN PASS_ACT <= '0'; next_state <= RESET; ELSIF (Addr mod 16#100# = 16#00#) AND (DataLo = 16#25#) THEN next_state <= PPWB25; END IF; END IF; WHEN PPPG1 => IF falling_edge(write) THEN next_state <= PPPG; END IF; WHEN PPPG => IF falling_edge(write) AND A_PAT_1 AND DataLo=16#70# THEN next_state <= PPSR; ELSIF rising_edge(PDONE) OR falling_edge(PERR) THEN next_state <= PP; END IF; WHEN PPSR => IF (STAT_ACT = '0') THEN IF (PDONE = '0') THEN next_state <= PPPG; ELSE next_state <= PP; END IF; ELSE next_state <= PPSR; END IF; WHEN PPWB25 => IF falling_edge(write) THEN IF (Addr mod 16#100# = 16#00#) AND (DataLo = 16#03#) THEN next_state <= PPD; ELSE next_state <= PP; END IF; END IF; WHEN PPD => IF falling_edge(write) THEN next_state <= PASSUNLOCK3; END IF; WHEN PASSUNLOCK3 => IF falling_edge(write) THEN next_state <= PASSUNLOCK4; END IF; WHEN PASSUNLOCK4 => IF falling_edge(write) THEN next_state <= PASSUNLOCK5; END IF; WHEN PASSUNLOCK5 => IF falling_edge(write) THEN next_state <= PASSUNLOCK6; END IF; WHEN PASSUNLOCK6 => IF falling_edge(write) THEN IF ( Addr = 16#00# ) AND DataLo = 16#29# THEN next_state <= PASSUNLOCK; ELSE next_state <= PP; END IF; END IF; WHEN PASSUNLOCK => IF rising_edge(UNLOCKDONE_out) THEN next_state <= PP; END IF; WHEN PPEXT => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN next_state <= RESET; PASS_ACT <= '0'; ELSE next_state <= PP; END IF; END IF; WHEN PPB_ASO => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= PPBSR; ELSIF (DataLo = 16#A0# OR DataLo = 16#80#) THEN next_state <= PPBPG1; ELSIF (DataLo = 16#90#) THEN next_state <= PPBEXT; ELSIF (DataLo = 16#F0#) THEN PPB_ACT <= '0'; next_state <= RESET; END IF; END IF; WHEN PPBSR => IF (STAT_ACT = '0') THEN IF (PDONE = '0') THEN next_state <= PPBPG; ELSIF (PPB_ACT_ER = '1') THEN next_state <= PPBER; ELSE next_state <= PPB_ASO; END IF; ELSE next_state <= PPBSR; END IF; WHEN PPBPG1 => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN next_state <= PPBPG; --PGMS ELSIF (DataLo = 16#F0#) THEN PPB_ACT <= '0'; next_state <= RESET; ELSIF (DataLo = 16#30#)AND (Addr=16#00#) THEN next_state <= PPBER; --SER PPB_ACT_ER <= '1'; ELSE next_state <= PPB_ASO; END IF; END IF; WHEN PPBPG => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= PPBSR; ELSIF (((Addr=16#555# AND DataLo = 16#71#) OR (DataLo = 16#F0#)) AND StatusReg(7) = '1') THEN next_state <= RESET; PPB_ACT <= '0'; END IF; ELSIF rising_edge(PDONE) OR falling_edge(PERR) THEN next_state <= PPB_ASO; END IF; WHEN PPBER => ---SER IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= PPBSR; ELSIF (((Addr=16#555# AND DataLo = 16#71#) OR (DataLo = 16#F0#)) AND StatusReg(7) = '1') THEN next_state <= RESET; PPB_ACT_ER <= '0'; PPB_ACT <= '0'; END IF; ELSIF rising_edge(EDONE) OR falling_edge(EERR) THEN next_state <= PPB_ASO; PPB_ACT_ER <= '0'; END IF; WHEN PPBEXT => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN next_state <= RESET; PPB_ACT <= '0'; ELSE next_state <= PPB_ASO; END IF; END IF; WHEN PPBLB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= PPBLBSR; ELSIF (DataLo = 16#A0#) THEN next_state <= PPBLBPG1; ELSIF (DataLo = 16#90#) THEN next_state <= PPBLBEXT; ELSIF (DataLo = 16#F0#) THEN next_state <= RESET; END IF; END IF; WHEN PPBLBSR => IF (STAT_ACT = '0') THEN next_state <= PPBLB; ELSE next_state <= PPBLBSR; END IF; WHEN PPBLBPG1 => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN next_state <= PPBLBSET; ELSE next_state <= PPBLB; END IF; END IF; WHEN PPBLBSET => --LR(2)=0; LR(5)=0 IF rising_edge(PBPROG_out) THEN next_state <= PPBLB; END IF; WHEN PPBLBEXT => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN next_state <= RESET; ELSE next_state <= PPBLB; END IF; END IF; WHEN DYB_ASO => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) THEN next_state <= DYBSR; ELSIF (DataLo = 16#A0#) THEN next_state <= DYBSET; ELSIF (DataLo = 16#90#) THEN next_state <= DYBEXT; ELSIF (DataLo = 16#F0#) THEN next_state <= RESET; END IF; END IF; WHEN DYBSR => IF (STAT_ACT = '0') THEN next_state <= DYB_ASO; ELSE next_state <= DYBSR; END IF; WHEN DYBSET => IF falling_edge(write) THEN IF (DataLo = 16#00# OR DataLo = 16#01#) THEN next_state <= DYB_ASO; ELSE next_state <= DYB_ASO; END IF; END IF; WHEN DYBEXT => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN next_state <= RESET; ELSE next_state <= DYB_ASO; END IF; END IF; END CASE; END IF; END PROCESS StateGen; --------------------------------------------------------------------------- --FSM Output generation and general functionality --------------------------------------------------------------------------- Functional : PROCESS(write, read, Addr, D_tmp, D_tmp1,Address, SecAddr, EDONE, sSTART_T1, RST, reseted, BCDONE, EERR, PDONE, sREADY, gOE_n, current_state, UNLOCKDONE_out, PERR, PBPROG_out ) --Flash Memory Array TYPE SecType IS ARRAY (0 TO SecSize) OF INTEGER RANGE -1 TO MaxData; TYPE MemArray IS ARRAY (0 TO SecNum) OF SecType; --Common Flash Interface Query codes TYPE CFItype IS ARRAY (16#10# TO 16#79#) OF NATURAL RANGE 0 TO 16#00FF#; --SecSi Sector TYPE SecSiType IS ARRAY ( 0 TO SecSiSize) OF INTEGER RANGE -1 TO MaxData; --WriteBuffer TYPE WBDataType IS ARRAY ( 0 TO 256) OF INTEGER RANGE -1 TO MaxData; TYPE WBAddrType IS ARRAY ( 0 TO 256) OF INTEGER RANGE -1 TO 256; -- Mem(SecAddr)(Address).... VARIABLE Mem : MemArray := (OTHERS => (OTHERS => MaxData)); VARIABLE CFI_array : CFItype := (OTHERS => 0); VARIABLE SecSi : SecSiType := (OTHERS => 0); VARIABLE WBData : WBDataType:= (OTHERS => 0); VARIABLE WBAddr : WBAddrType:= (OTHERS => -1); VARIABLE BaseLoc : NATURAL RANGE 0 TO SecSize := 0; VARIABLE cnt : NATURAL RANGE 0 TO 256 := 0; VARIABLE PATTERN_1 : boolean := FALSE; VARIABLE PATTERN_2 : boolean := FALSE; VARIABLE A_PAT_1 : boolean := FALSE; VARIABLE BUFF_FLAG : BOOLEAN := FALSE; VARIABLE oe : boolean := FALSE; --Status reg. VARIABLE Status : std_logic_vector(15 downto 0) := (OTHERS => '0'); VARIABLE PGMS_FLAG : PgmsTargetType; VARIABLE PassMATCH : PassUnlockType; -- text file input variables FILE mem_file : text is mem_file_name; FILE prot_file : text is prot_file_name; FILE secsi_file : text is secsi_file_name; VARIABLE S_ind : NATURAL RANGE 0 TO SecNum := 0; VARIABLE ind : NATURAL := 0; VARIABLE index : NATURAL RANGE 0 TO SecSize:=0; VARIABLE index_sec_si: NATURAL RANGE 0 TO SecSiSize:=0; VARIABLE buf : line; VARIABLE old_bit : std_logic_vector(15 downto 0); VARIABLE new_bit : std_logic_vector(15 downto 0); VARIABLE old_int : INTEGER RANGE -1 to MaxData; VARIABLE new_int : INTEGER RANGE -1 to MaxData; VARIABLE wr_cnt : NATURAL RANGE 0 TO 256; VARIABLE PassAddr : NATURAL RANGE 0 TO 3; VARIABLE old_PPB : std_logic_vector(15 downto 0); --DATA Low Byte VARIABLE DataLo : NATURAL RANGE 0 TO 16#FFF# := 0; --DATA WORD VARIABLE Data : NATURAL RANGE 0 TO MaxData := 0; VARIABLE PR_FLAG : BOOLEAN := FALSE; VARIABLE ER_FLAG : BOOLEAN := FALSE; VARIABLE temp : std_logic_vector(15 downto 0); VARIABLE SecSiAddr : NATURAL RANGE 0 TO SecSiSize := 0; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(write) THEN DataLo := D_tmp1; Data := D_tmp; PATTERN_1 := (Addr=16#555#) AND (DataLo=16#AA#) ; PATTERN_2 := (Addr=16#2AA#) AND (DataLo=16#55#) ; A_PAT_1 := (Addr=16#555#); END IF; oe := rising_edge(read) OR (read = '1' AND Address'EVENT); IF falling_edge(RST) AND RESETNeg = '0' THEN ESP_ACT <= '0'; PSP_ACT <= '0'; IF LockReg(2) = '0' THEN -- password unlock needed to unfreeze PPBLock PPBLock := '0';--Password Sector Protection ELSE PPBLock := '1';-- Pesistent Protection -- PPBLOck cleared after hardware reset END IF; DYB := (OTHERS => '1');-- unprotected state 01h after hardware reset UNLOCKDONE_in <= '0'; START_T1_in <= '0'; STAT_ACT <= '0'; Ers_Queue <= (OTHERS => '0'); StatusReg(7) := '1'; StatusReg(6 DOWNTO 0) := (OTHERS => '0'); END IF; IF reseted = '1' THEN CASE current_state IS WHEN RESET => OTP_ACT <= '0'; PSP_ACT <= '0'; ESP_ACT <= '0'; FactoryAddr <= '0'; StatusReg(7) := '1'; IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF (A_PAT_1 AND (DataLo=16#71#)) THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; ELSIF (A_PAT_1 AND (DataLo = 16#33#)) THEN BCSTART <= '1', '0' AFTER 1 ns; StatusReg (7) := '0'; StatusReg (5) := '0'; IF DYB(SecAddr) = '0' OR PPB(SecAddr) = '0' OR (WPNeg = '0' AND (SecAddr = ProtSecNum)) THEN StatusReg(1) := '1'; StatusReg(7) := '1'; END IF; SA <= SecAddr; STAT_ACT <= '0'; END IF; END IF; IF oe THEN DOut_zd(15 downto 0) <= READMEM(Mem(SecAddr)(Address)); END IF; --ready signal active RY_zd <= '1'; WHEN BLCK => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF (A_PAT_1 AND (DataLo=16#71#)) THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN DOut_zd(15 downto 0) <= (OTHERS => 'X'); END IF; IF rising_edge(BCDONE) THEN StatusReg(7) := '1'; StatusReg(5) := '0'; FOR j IN 0 TO SecSize LOOP IF Mem(SA)(j) /= MaxData THEN StatusReg (5) := '1'; END IF; END LOOP; STAT_ACT <= '0'; END IF; --busy signal active RY_zd <= '0'; WHEN READUL1 => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; END IF; END IF; WHEN READUL2 => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF (A_PAT_1 AND (DataLo = 16#88#)) THEN OTP_ACT <= '1'; FactoryAddr <= '0'; ELSIF (DataLo=16#25#) THEN --fix Sector Address SA SA <= SecAddr; END IF; END IF; WHEN READSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd(15 downto 0) <= StatusReg; STAT_ACT <= '0'; END IF; WHEN PG1 => IF falling_edge(write) THEN PSTART <= '1', '0' AFTER 1 ns; StatusReg(7) := '0'; IF DYB(SecAddr) = '0' OR PPB(SecAddr) = '0' OR (WPNeg = '0' AND (SecAddr = ProtSecNum)) THEN StatusReg(1) := '1'; StatusReg(7) := '1'; END IF; PSUSP <= '0'; PRES <= '0'; PCNT <= 256; PGMS_FLAG := MEMORY; PR_FLAG := FALSE; WBData(0) := -1; IF Viol = '0' THEN WBData(0) := Data; END IF; WBAddr(0) := Address MOD 256; WBPage <= WPage; SA <= SecAddr; temp := to_slv(Data, 16); Status(7) := NOT temp(7); WBAddr(1) := -1; END IF; WHEN WB | ES_WB => IF falling_edge(write) THEN IF (SecAddr = SA) AND Data < 256 THEN cnt := Data; PCNT <= cnt; LCNT <= cnt; BUFF_FLAG:= TRUE; ELSE StatusReg(3) := '1'; StatusReg(4) := '1'; END IF; END IF; WHEN WB_D | ES_WB_D => IF falling_edge(write) THEN IF BUFF_FLAG THEN BUFF_FLAG:= FALSE; IF (SecAddr = SA) THEN -- fix WriteBufferPage WBPage WBData(cnt) := -1; IF Viol = '0' THEN WBData(cnt) := Data; END IF; WBAddr(cnt) := Address MOD 256; IF cnt > 0 THEN cnt := cnt -1; END IF; --save last loaded data for data polling temp := to_slv(Data, 16); Status(7) := NOT temp(7); WBPage <= WPage; ELSE StatusReg(3) := '1'; StatusReg(4) := '1'; END IF; LCNT <= cnt; ELSE IF (WPage = WBPage) THEN WBData(cnt) := -1; IF Viol = '0' THEN WBData(cnt) := Data; END IF; WBAddr(cnt) := Address MOD 256; IF cnt > 0 THEN cnt := cnt -1; END IF; --save last loaded data for data polling temp := to_slv(Data, 16); Status(7) := NOT temp(7); ELSE StatusReg(3) := '1'; StatusReg(4) := '1'; END IF; LCNT <= cnt; END IF; END IF; WHEN PBF => IF falling_edge(write) THEN IF (SecAddr = SA) AND (DataLo = 16#29#) THEN PSTART <= '1', '0' AFTER 1 ns; IF DYB(SecAddr) = '0' OR PPB(SecAddr) = '0' OR (WPNeg = '0' AND (SecAddr = ProtSecNum)) THEN StatusReg(1) := '1'; END IF; StatusReg(7) := '0'; PSUSP <= '0'; PRES <= '0'; IF OTP_ACT = '1' THEN PGMS_FLAG := SSR; ELSE PGMS_FLAG := MEMORY; END IF; PR_FLAG := FALSE; ELSE StatusReg(3) := '1'; StatusReg(4) := '1'; END IF; END IF; WHEN WBUL1 => null; WHEN WBUL2 => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN PSP_ACT <= '0'; END IF; END IF; WHEN ID_CFI => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#70#)) AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF (A_PAT_1 AND (DataLo=16#71#)) THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN --ID_CFI RESET DOut_zd(15 downto 0) <= (OTHERS => '0'); IF ((Addr>=16#10#) AND (Addr <= 16#79#)) THEN DOut_zd(15 downto 0) <= to_slv(CFI_array(Addr) ,16); ELSIF Addr=16#00# THEN DOut_zd(15 downto 0) <= to_slv(16#0001#,16); ELSIF Addr=16#01# THEN DOut_zd(15 downto 0) <= to_slv(16#227E#,16); ELSIF Addr=16#02# THEN DOut_zd(15 downto 1) <= to_slv(0,15); IF ( DYB(SecAddr) = '1' AND PPB(SecAddr) = '1' ) THEN DOut_zd(0) <= '0';--unprotected (inverted statuses) ELSE DOut_zd(0) <= '1';-- protected(inverted statuses) END IF; ELSIF Addr=16#03# THEN DOut_zd(15 downto 8) <= to_slv(16#FF#,8); DOut_zd(7 downto 0) <= to_slv(16#20#,8); IF ProtSecNum > 0 THEN --Highest Address Sector Protected by WP# DOut_zd(4) <= '1'; ELSE DOut_zd(4) <= '0'; END IF; DOut_zd(7) <= '1';--SSR Region0(Factory) Lock bit IF LockReg(6) = '0' THEN --SSR Reg1(customer) Lock bit DOut_zd(6) <= '1'; --Lockable Line 2 Locked else DOut_zd(6) <= '0'; --Lockable Line 2 Not Locked END IF; ELSIF Addr>=16#04# and Addr<=16#0B# THEN DOut_zd(15 downto 0) <= to_slv(16#FFFF#,16); ELSIF Addr=16#0C# THEN DOut_zd(15 downto 4) <= to_slv(0,12); DOut_zd(3 downto 2 ) <= to_slv(0,2);--Classic cmd set DOut_zd(1) <= '1';--DQ bit polling supported DOut_zd(0) <= '1';--Status register supported ELSIF Addr = 16#0D# THEN DOut_zd(15 downto 0) <= to_slv(0,16); ELSIF Addr = 16#0E# THEN DOut_zd(15 downto 0) <= to_slv(16#2221#,16); ELSIF Addr = 16#0F# THEN DOut_zd(15 downto 0) <= to_slv(16#2201#,16); ELSE ASSERT FALSE REPORT "Invalid ID_CFI query address" SEVERITY warning; END IF; END IF; WHEN CFISR => IF (oe AND STAT_ACT = '1') THEN DOut_zd(15 downto 0) <= StatusReg; STAT_ACT <= '0'; END IF; WHEN ER => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; END IF; END IF; WHEN ERUL1 => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; END IF; END IF; WHEN ERUL2 => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF A_PAT_1 AND DataLo=16#10# THEN --Start Chip Erase ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; Ers_Queue <= (OTHERS => '1'); StatusReg(7 downto 0) := "00000000"; ER_FLAG := FALSE; ELSIF DataLo=16#30# THEN --put selected sector to sec. ers. queue --start timeout Ers_Queue(SecAddr) <= '1'; START_T1_in <= '0'; ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; StatusReg(7 downto 0) := "00000000"; ER_FLAG := FALSE; IF DYB(SecAddr) = '0' OR PPB(SecAddr) = '0' OR (WPNeg = '0' AND (SecAddr = ProtSecNum)) THEN StatusReg(1) := '1'; StatusReg(7) := '1'; END IF; END IF; END IF; WHEN CER => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; END IF; END IF; IF oe THEN ------------------------------------------------------- -- read status / embeded erase algorithm - Chip Erase ------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(2) := NOT Status(2); --toggle DOut_zd(15 downto 0) <= Status; END IF; IF EERR /= '1' THEN IF NOT ER_FLAG THEN ER_FLAG:= TRUE; FOR i IN 0 TO SecNum LOOP IF (DYB(i) = '1' AND PPB(i) = '1' AND NOT(WPNeg = '0' AND (SA = ProtSecNum))) THEN Mem(i) := (OTHERS => -1); END IF; END LOOP; END IF; IF EDONE = '1' THEN ER_FLAG:= FALSE; FOR i IN 0 TO SecNum LOOP IF (DYB(i) = '1' AND PPB(i) = '1' AND NOT(WPNeg = '0' AND (SA = ProtSecNum))) THEN Mem(i) := (OTHERS => MaxData); END IF; END LOOP; Ers_Queue <= (OTHERS => '0'); END IF; END IF; IF rising_edge(EDONE) THEN StatusReg(7) := '1'; END IF; IF (EERR'EVENT) THEN StatusReg(5) := '1'; END IF; -- busy signal active RY_zd <= '0'; WHEN ERSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd(15 downto 0) <= StatusReg; STAT_ACT <= '0'; END IF; WHEN ESR => IF falling_edge(WRITE) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; END IF; END IF; IF (sSTART_T1 = '1') THEN StatusReg(6) := '1'; StatusReg(7) := '1'; ESP_ACT <= '1'; START_T1_in <= '0'; ELSIF oe THEN ------------------------------------------------------- --read status / erase suspend timeout - stil erasing ------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; IF Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); --toggle END IF; DOut_zd(15 downto 0) <= Status; END IF; --busy signal active RY_zd <= '0'; WHEN SER => IF falling_edge(write) THEN IF (A_PAT_1) AND (DataLo = 16#70#) AND (STAT_ACT = '0') THEN STAT_ACT <= '1'; ELSIF (Addr = 16#555# AND DataLo = 16#71#) THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN ------------------------------------------------------- --read status Erase Busy ------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; IF Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); --toggle END IF; DOut_zd(15 downto 0) <= Status; END IF; IF EERR /= '1' THEN IF NOT ER_FLAG THEN ER_FLAG:= TRUE; FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND (DYB(i) = '1' AND PPB(i) = '1' AND NOT(WPNeg='0' AND (SA=ProtSecNum))) THEN Mem(i) := (OTHERS => -1); END IF; END LOOP; END IF; IF EDONE = '1' THEN ER_FLAG:= FALSE; FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND (DYB(i) = '1' AND PPB(i) = '1' AND NOT(WPNeg = '0' AND (SA = ProtSecNum))) THEN Mem(i) := (OTHERS => MaxData); END IF; END LOOP; Ers_Queue <= (OTHERS => '0'); StatusReg(7) := '1'; ELSIF falling_edge(write) THEN IF DataLo=16#B0# THEN START_T1_in <= '1'; ESUSP <= '1', '0' AFTER 1 ns; END IF; END IF; END IF; IF EERR'EVENT THEN StatusReg(5) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN ES => StatusReg(6) := '1'; ESUSP <= '0'; IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; IF DataLo = 16#30# THEN --resume erase StatusReg(6) := '0'; StatusReg(7) := '0'; ERES <= '1', '0' AFTER 1 ns; END IF; ELSIF oe THEN ----------------------------------------------------------- --read ----------------------------------------------------------- IF Ers_Queue(SecAddr) /= '1' THEN DOut_zd(15 downto 0) <= READMEM(Mem(SecAddr)(Address)); ELSE ------------------------------------------------------- --read status ------------------------------------------------------- Status(7) := '1'; -- Status(6) No toggle Status(5) := '0'; Status(2) := NOT Status(2); --toggle DOut_zd(15 downto 0) <= Status; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN ESSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd(15 downto 0) <= StatusReg; STAT_ACT <= '0'; END IF; WHEN ESUL1 => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF ((NOT(Addr=16#2AA#) OR NOT(DataLo = 16#55#)) AND StatusReg(3) = '1') THEN StatusReg(7) := '1'; END IF; END IF; WHEN ESUL2 => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF DataLo = 16#25# THEN --fix SA SA <= SecAddr; ESP_ACT <= '1'; ELSIF DataLo = 16#30# THEN --resume erase StatusReg(6) := '0'; StatusReg(7) := '0'; ERES <= '1', '0' AFTER 1 ns; END IF; END IF; WHEN ESPG1 => IF falling_edge(write) THEN StatusReg(6) := '1'; ESP_ACT <= '1'; PSTART <= '1', '0' AFTER 1 ns; StatusReg(7) := '0'; IF DYB(SecAddr) = '0' OR PPB(SecAddr) = '0' OR (WPNeg = '0' AND (SecAddr = ProtSecNum)) THEN StatusReg(1) := '1'; StatusReg(7) := '1'; END IF; PRES <= '0'; PSUSP <= '0'; PCNT <= 256; WBData(0) := -1; IF Viol = '0' THEN WBData(0) := Data; END IF; WBAddr(0) := Address MOD 256; WBPage <= WPage; SA <= SecAddr; PGMS_FLAG := MEMORY; PR_FLAG := FALSE; temp := to_slv(Data, 16); Status(7) := NOT temp(7); WBAddr(1) := -1; END IF; WHEN ESPGSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd <= StatusReg; STAT_ACT <= '0'; END IF; WHEN ESPSR => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; END IF; END IF; IF sSTART_T1 = '1' THEN StatusReg(7) := '1'; StatusReg(2) := '1'; START_T1_in <= '0'; ELSIF oe THEN ------------------------------------------------------- --read status / stil programming ------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; DOut_zd(15 downto 0) <= Status; END IF; --ready signal active RY_zd <= '0'; WHEN ESPS => StatusReg(2) := '1'; IF falling_edge(write) THEN IF (DataLo = 16#50# OR DataLo = 16#30#) THEN PRES <= '1', '0' AFTER 1 ns; StatusReg(2) := '0'; StatusReg(7) := '0'; ELSIF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; ELSIF oe THEN ----------------------------------------------------------- --read - program suspend ----------------------------------------------------------- IF SA = SecAddr AND WPage = WBPage THEN --read program suspended line --Invalid (not allowed) ASSERT false REPORT "Read from program suspended line " & "is NOT allowed" SEVERITY warning; ELSIF ESP_ACT = '1' AND Ers_Queue(SecAddr) = '1' THEN Status(7) := '1'; -- Status(6) No toggle Status(5) := '0'; Status(2) := NOT Status(2); --toggle DOut_zd(15 downto 0) <= Status; ELSE --read sector other than erase suspended one DOut_zd(15 downto 0) <= READMEM(Mem(SecAddr)(Address)); END IF; END IF; --ready signal active RY_zd <= '1'; WHEN ESPSSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd <= StatusReg; STAT_ACT <= '0'; END IF; WHEN ESPSUL1 => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; END IF; END IF; WHEN ESPSUL2 => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF (DataLo = 16#50# OR DataLo = 16#30#) THEN PRES <= '1', '0' AFTER 1 ns; StatusReg(2) := '0'; StatusReg(7) := '0'; END IF; END IF; WHEN ESDYB => ESP_ACT <= '1'; IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN DOut_zd(15 downto 1) <= (OTHERS => '0'); DOut_zd(0) <= DYB(SecAddr); END IF; WHEN ESDYBSET => ESP_ACT <= '1'; IF falling_edge(write) THEN IF DataLo = 16#00# THEN DYB(SecAddr) := '0'; ELSIF DataLo = 16#01# THEN DYB(SecAddr) := '1'; END IF; END IF; WHEN ESDYBEXT => NULL; WHEN PG | ESPG => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN IF StatusReg(3) = '1' THEN ----------------------------------------------------------- --read status / write buffer abort ----------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(1) := '1'; DOut_zd(15 downto 0) <= Status; ELSE ------------------------------------------------------- --read status ------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; DOut_zd(15 downto 0) <= Status; END IF; END IF; IF PERR /= '1' AND NOT falling_edge(PERR) AND StatusReg(3) /= '1' THEN IF NOT PR_FLAG THEN PR_FLAG:=TRUE; BaseLoc := WBPage * 256; IF PCNT < 256 THEN --buffer wr_cnt := PCNT; ELSE --Word program IF WBAddr(1) < 0 THEN wr_cnt := 0; END IF; END IF; FOR i IN wr_cnt downto 0 LOOP new_int := WBData(i); IF WBAddr(i) < 0 THEN old_int := -1; ELSIF PGMS_FLAG = MEMORY THEN --mem write old_int := Mem(SA)(BaseLoc+WBAddr(i)); END IF; IF new_int > -1 THEN new_bit := to_slv(new_int,16); IF (PGMS_FLAG = MEMORY) AND (old_int>-1) THEN old_bit := to_slv(old_int,16); FOR j IN 0 TO 15 LOOP IF old_bit(j) = '0' THEN new_bit(j) := '0'; END IF; END LOOP; ELSE new_bit(0) := 'X'; END IF; IF new_bit(0)/='X' THEN new_int := to_nat(new_bit); WBData(i) := new_int; ELSE WBData(i) := -1; END IF; ELSE WBData(i) := -1; END IF; END LOOP; FOR i IN wr_cnt downto 0 LOOP IF PGMS_FLAG = MEMORY THEN --mem write Mem(SA)(BaseLoc + WBAddr(i)) := -1; END IF; END LOOP; END IF; IF PDONE = '1' AND (NOT PERR'EVENT) THEN PR_FLAG :=FALSE; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 AND WBdata(i) > -1 THEN IF PGMS_FLAG = MEMORY THEN --mem write Mem(SA)(BaseLoc + WBAddr(i)) := WBData(i); END IF; END IF; WBData(i) := -1; END LOOP; ELSIF falling_edge(write) THEN IF DataLo = 16#51# OR DataLo = 16#B0# THEN START_T1_in <= '1'; END IF; END IF; END IF; IF PERR'EVENT THEN StatusReg(4) := '1'; END IF; IF rising_edge(PDONE) OR falling_edge(PERR) THEN StatusReg(7) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN PGSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd(15 downto 0) <= StatusReg; STAT_ACT <= '0'; END IF; IF rising_edge(PDONE) AND (NOT PERR'EVENT) THEN PR_FLAG :=FALSE; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 AND WBdata(i) > -1 THEN --mem write Mem(SA)(BaseLoc + WBAddr(i)) := WBData(i); END IF; WBData(i) := -1; END LOOP; StatusReg(7) := '1'; END IF; IF falling_edge(PERR) THEN StatusReg(7) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN PSR => PSUSP <= '1'; IF falling_edge(write) AND Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; END IF; IF sSTART_T1 = '1' THEN StatusReg(7) := '1'; StatusReg(2) := '1'; START_T1_in <= '0'; ELSIF oe THEN ------------------------------------------------------- --read status / stil programming ------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; DOut_zd(15 downto 0) <= Status; END IF; --busy signal active RY_zd <= '0'; WHEN PS => PSUSP <= '0'; IF falling_edge(write) THEN IF (DataLo = 16#50# OR DataLo = 16#30#) THEN PRES <= '1', '0' AFTER 1 ns; StatusReg(2) := '0'; StatusReg(7) := '0'; END IF; IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; ELSIF oe THEN ----------------------------------------------------------- --read - program suspend ----------------------------------------------------------- IF SA = SecAddr AND WPage = WBPage THEN --read program suspended line --Invalid (not allowed) ASSERT false REPORT "Read from program suspended line " & "is NOT allowed" SEVERITY warning; ELSE --read sector other than program suspended one DOut_zd(15 downto 0) <= READMEM(Mem(SecAddr)(Address)); END IF; END IF; --ready signal active RY_zd <= '1'; WHEN PSSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd <= StatusReg; STAT_ACT <= '0'; END IF; WHEN SSR => OTP_ACT <= '1'; FactoryAddr <= '0'; IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN --read SecSi Sector Region SecSiAddr := Address MOD (SecSiSize + 1); DOut_zd(15 downto 0) <= (OTHERS => 'X'); IF SecSi(SecSiAddr) /= -1 THEN DOut_zd(15 downto 0)<=to_slv(SecSi(SecSiAddr),16); END IF; END IF; --ready signal active RY_zd <= '1'; WHEN SSRUL1 => null; WHEN SSRUL2 => IF falling_edge(write) THEN IF DataLo = 16#25# THEN --activate SSR OTP_ACT <= '1'; FactoryAddr <= '0'; END IF; END IF; WHEN SSR_WB => IF falling_edge(write) THEN IF (SecAddr = SA) AND Data < 256 THEN cnt := Data; PCNT <= cnt; LCNT <= cnt; BUFF_FLAG:= TRUE; ELSE StatusReg(3) := '1'; StatusReg(4) := '1'; END IF; END IF; WHEN SSR_WB_D => IF falling_edge(write) THEN IF BUFF_FLAG THEN BUFF_FLAG:= FALSE; IF (SecAddr = SA) THEN -- fix WriteBufferPage WBPage WBData(cnt) := -1; IF Viol = '0' THEN WBData(cnt) := Data; END IF; WBAddr(cnt) := Address MOD 256; IF cnt > 0 THEN cnt := cnt -1; END IF; --save last loaded data for data polling temp := to_slv(Data, 16); Status(7) := NOT temp(7); WBPage <= 0; ELSE StatusReg(3) := '1'; StatusReg(4) := '1'; END IF; LCNT <= cnt; ELSE IF (WPage = WBPage) THEN WBData(cnt) := -1; IF Viol = '0' THEN WBData(cnt) := Data; END IF; WBAddr(cnt) := Address MOD 256; IF cnt > 0 THEN cnt := cnt -1; END IF; --save last loaded data for data polling temp := to_slv(Data, 16); Status(7) := NOT temp(7); ELSE ASSERT WPage<1 REPORT "Invalid Write Buffer Page selected in "& " SecSi" SEVERITY warning; StatusReg(3) := '1'; StatusReg(4) := '1'; END IF; LCNT <= cnt; END IF; END IF; WHEN SSRPG => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN ------------------------------------------------------- --read status ------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; DOut_zd(15 downto 0) <= Status; END IF; IF PERR /= '1' AND NOT falling_edge(PERR) THEN IF NOT PR_FLAG THEN PR_FLAG:=TRUE; BaseLoc := WBPage * 256; IF PCNT < 256 THEN --buffer wr_cnt := PCNT; ELSE --Word program IF WBAddr(1) < 0 THEN wr_cnt := 0; END IF; END IF; FOR i IN wr_cnt downto 0 LOOP new_int := WBData(i); IF WBAddr(i) < 0 THEN old_int := -1; ELSIF PGMS_FLAG = SSR THEN old_int := SecSi(BaseLoc+WBAddr(i)); END IF; IF new_int > -1 THEN new_bit := to_slv(new_int,16); IF (PGMS_FLAG = SSR AND old_int>-1) THEN old_bit := to_slv(old_int,16); FOR j IN 0 TO 15 LOOP IF old_bit(j) = '0' THEN new_bit(j) := '0'; END IF; END LOOP; ELSE new_bit(0) := 'X'; END IF; IF new_bit(0)/='X' THEN new_int := to_nat(new_bit); WBData(i) := new_int; ELSE WBData(i) := -1; END IF; ELSE WBData(i) := -1; END IF; END LOOP; FOR i IN wr_cnt downto 0 LOOP IF PGMS_FLAG = SSR THEN SecSi(BaseLoc + WBAddr(i)) := -1; END IF; END LOOP; END IF; IF PDONE = '1' AND (NOT PERR'EVENT) THEN PR_FLAG :=FALSE; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 AND WBdata(i) > -1 THEN IF PGMS_FLAG = SSR THEN --SecSi write SecSi(BaseLoc+WBAddr(i)) := WBData(i); END IF; END IF; WBData(i) := -1; END LOOP; END IF; END IF; IF PERR'EVENT THEN StatusReg(4) := '1'; END IF; IF rising_edge(PDONE) OR falling_edge(PERR) THEN StatusReg(7) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN SSRSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd(15 downto 0) <= StatusReg; STAT_ACT <= '0'; END IF; IF rising_edge(PDONE) AND (NOT PERR'EVENT) THEN PR_FLAG :=FALSE; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 AND WBdata(i) > -1 THEN IF PGMS_FLAG = SSR THEN --SecSi write SecSi(BaseLoc+WBAddr(i)) := WBData(i); END IF; END IF; WBData(i) := -1; END LOOP; StatusReg(7) := '1'; END IF; IF falling_edge(PERR) THEN StatusReg(7) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN SSREXT => IF (falling_edge(write) AND DataLo=16#00#) THEN OTP_ACT <='0'; FactoryAddr <= '0'; END IF; WHEN SSRPG1 => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; SA <= SecAddr; OTP_ACT <= '1'; FactoryAddr <= '0'; ------------------------------------------------------ --SecSi programming: TBD ------------------------------------------------------ PSTART <= '1', '0' AFTER 1 ns; StatusReg(7) := '0'; PSUSP <= '0'; PRES <= '0'; PCNT <= 256; PGMS_FLAG := SSR; PR_FLAG := FALSE; WBData(0) := -1; IF Viol = '0' THEN WBData(0) := Data; END IF; WBAddr(0) := Address MOD 256; WBPage <= 0; IF Address > 255 THEN FactoryAddr <= '1'; END IF; ASSERT Address < 256 REPORT "Invalid program address in SecSi region 2. "& "SecSi Factory region. "& "Address= "& to_int_str(Address) SEVERITY warning; temp := to_slv(Data, 16); Status(7) := NOT temp(7); WBAddr(1) := -1; END IF; WHEN LR => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; ELSIF (oe AND Addr = 16#00#) THEN DOut_zd(15 downto 0) <= LockReg; END IF; --ready signal active RY_zd <= '1'; WHEN LRSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd <= StatusReg; STAT_ACT <= '0'; END IF; IF rising_edge(PDONE) AND (NOT PERR'EVENT) THEN PR_FLAG :=FALSE; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 AND WBdata(i) > -1 THEN LockReg(6 downto 0) := to_slv(WBData(i),7); END IF; WBData(i) := -1; END LOOP; StatusReg(7) := '1'; END IF; IF falling_edge(PERR) THEN StatusReg(7) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN LRPG1 => IF falling_edge(write) THEN temp := to_slv(Data, 16); IF NOT(temp(1) = '0' AND temp(2) = '0') THEN PSTART <= '1', '0' AFTER 1 ns; StatusReg(7) := '0'; PSUSP <= '0'; PRES <= '0'; PCNT <= 256; IF temp(1) = '0' AND LockReg(2) = '0' THEN -- Can not program SPMLB if PPMLB programmed temp(1) := '1'; ELSIF temp(2) = '0' AND LockReg(1) = '0' THEN -- Can not program PPMLB if SPMLB programmed temp(2) := '1'; END IF; WBData(0) := -1; IF Viol = '0' THEN WBData(0) := to_nat(temp); END IF; WBAddr(0) := 0; --- Addr don't care XXX PGMS_FLAG := LREG; PR_FLAG := FALSE; WBPage <= WPage; SA <= SecAddr; temp := to_slv(Data, 16); Status(7) := NOT temp(7); WBAddr(1) := -1; END IF; END IF; WHEN LRPG => IF (falling_edge(write) AND Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0') THEN STAT_ACT <= '1'; ELSIF oe THEN ------------------------------------------------------- --read status ------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; DOut_zd(15 downto 0) <= Status; END IF; IF PERR /= '1' AND NOT falling_edge(PERR) THEN IF NOT PR_FLAG THEN PR_FLAG:=TRUE; BaseLoc := WBPage * 256; --Word program IF WBAddr(1) < 0 THEN wr_cnt := 0; END IF; FOR i IN wr_cnt downto 0 LOOP new_int := WBData(i); old_bit := LockReg; IF new_int > -1 THEN new_bit := to_slv(new_int,16); IF PGMS_FLAG = LREG AND old_bit(0)/='X' THEN FOR j IN 0 TO 6 LOOP IF old_bit(j) = '0' THEN new_bit(j) := '0'; END IF; END LOOP; ELSE new_bit(0) := 'X'; END IF; IF new_bit(0)/='X' THEN new_int := to_nat(new_bit); WBData(i) := new_int; ELSE WBData(i) := -1; END IF; ELSE WBData(i) := -1; END IF; END LOOP; LockReg(6 downto 0) := (OTHERS => 'X'); END IF; IF PDONE = '1' AND (NOT PERR'EVENT) THEN PR_FLAG :=FALSE; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 AND WBdata(i) > -1 THEN LockReg(6 downto 0) := to_slv(WBData(i),7); END IF; WBData(i) := -1; END LOOP; END IF; END IF; IF PERR'EVENT THEN StatusReg(4) := '1'; END IF; IF rising_edge(PDONE) OR falling_edge(PERR) THEN StatusReg(7) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN LREXT => NULL; WHEN PP => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; ELSIF oe THEN IF LockReg(2) /= '0' THEN DOut_zd(15 downto 0) <= Password(Address mod 4); ELSE DOut_zd(15 downto 0) <= (OTHERS => '1'); END IF; END IF; --ready signal active RY_zd <= '1'; WHEN PPPG1 => IF falling_edge(write) THEN PSTART <= '1', '0' AFTER 1 ns; StatusReg(7) := '0'; PSUSP <= '0'; PRES <= '0'; PCNT <= 256; WBData(0) := -1; IF Viol = '0' THEN WBData(0) := Data; END IF; WBAddr(0) := Address MOD 8; PGMS_FLAG := PASSW; PR_FLAG := FALSE; SA <= SecAddr; temp := to_slv(Data, 16); Status(7) := NOT temp(7); END IF; WHEN PPPG => IF (falling_edge(write) AND Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0') THEN STAT_ACT <= '1'; ELSIF oe THEN ------------------------------------------------------- --read status ------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; DOut_zd(15 downto 0) <= Status; END IF; IF PERR /= '1' AND NOT falling_edge(PERR) THEN IF NOT PR_FLAG THEN PR_FLAG:=TRUE; BaseLoc := WBPage * 256; --Word program IF WBAddr(1) < 0 THEN wr_cnt := 0; END IF; FOR i IN wr_cnt downto 0 LOOP new_int := WBData(i); old_bit := Password(WBAddr(i)); IF new_int > -1 THEN new_bit := to_slv(new_int,16); IF (PGMS_FLAG = PASSW AND old_bit(0)/='X') THEN FOR j IN 0 TO 15 LOOP IF old_bit(j) = '0' THEN new_bit(j) := '0'; END IF; END LOOP; ELSE new_bit(0) := 'X'; END IF; IF new_bit(0)/='X' THEN new_int := to_nat(new_bit); WBData(i) := new_int; ELSE WBData(i) := -1; END IF; ELSE WBData(i) := -1; END IF; END LOOP; FOR i IN wr_cnt downto 0 LOOP Password(WBAddr(i)) := (OTHERS => 'X'); END LOOP; END IF; IF PDONE = '1' AND (NOT PERR'EVENT) THEN PR_FLAG :=FALSE; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 AND WBdata(i) > -1 THEN Password(WBAddr(i)):=to_slv(WBData(i),16); END IF; WBData(i) := -1; END LOOP; END IF; END IF; IF PERR'EVENT THEN StatusReg(4) := '1'; END IF; IF rising_edge(PDONE) OR falling_edge(PERR) THEN StatusReg(7) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN PPSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd <= StatusReg; STAT_ACT <= '0'; END IF; IF rising_edge(PDONE) AND (NOT PERR'EVENT) THEN PR_FLAG :=FALSE; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 AND WBdata(i) > -1 THEN Password(WBAddr(i)):=to_slv(WBData(i),16); END IF; WBData(i) := -1; END LOOP; END IF; IF falling_edge(PERR) THEN StatusReg(7) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN PPWB25 => PassMATCH := (FALSE,FALSE,FALSE,FALSE); WHEN PPD | PASSUNLOCK3 | PASSUNLOCK4 | PASSUNLOCK5 => IF falling_edge(write) THEN PassAddr := (Address mod 16#100#) mod 4; PassMATCH(PassAddr) := to_nat(Password(PassAddr)) = Data; END IF; WHEN PASSUNLOCK6 => IF falling_edge(write) AND ( Addr = 16#00#) AND DataLo = 16#29# THEN UNLOCKDONE_in <= '0', '1' AFTER 1 ns; END IF; WHEN PASSUNLOCK => IF rising_edge(UNLOCKDONE_out) AND PassMATCH = (TRUE,TRUE,TRUE,TRUE) THEN PPBLock := '1'; END IF; WHEN PPEXT => NULL; WHEN PPB_ASO => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN DOut_zd(15 downto 1) <= (OTHERS => '0'); DOut_zd(0) <= PPB(SecAddr); END IF; --ready signal active RY_zd <= '1'; WHEN PPBSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd <= StatusReg; STAT_ACT <= '0'; END IF; IF PDONE = '1' AND (NOT PERR'EVENT) THEN PR_FLAG :=FALSE; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 AND WBdata(i) > -1 THEN IF PGMS_FLAG = PPB_BIT THEN IF PPBLock = '1' THEN PPB(SA) := '0'; ELSE old_PPB := to_slv(WBData(i),16); PPB(SA) := old_PPB(0); END IF; END IF; END IF; WBData(i) := -1; END LOOP; END IF; IF rising_edge(PDONE) OR falling_edge(PERR) THEN StatusReg(7) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN PPBPG1 => IF falling_edge(write) THEN IF DataLo=16#30# AND Addr=16#00# THEN StatusReg(7) := '0'; ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; SA <= SecAddr; IF PPBLock = '0' THEN StatusReg(7) := '1'; END IF; ELSIF (DataLo = 16#F0#) THEN PSTART <= '0'; StatusReg(7) := '1'; ELSIF (DataLo = 16#00#) THEN PSTART <= '1', '0' AFTER 1 ns; StatusReg(7) := '0'; IF PPBLock = '0' THEN StatusReg(7) := '1'; END IF; PSUSP <= '0'; PRES <= '0'; PCNT <= 256; WBAddr(0) := 0; --- Addr don't care XXX WBData(0) := -1; IF Viol = '0' THEN WBData(0) := 1; END IF; PGMS_FLAG := PPB_BIT; PR_FLAG := FALSE; WBPage <= WPage; SA <= SecAddr; temp := to_slv(Data, 16); Status(7) := NOT temp(7); ELSE null; END IF; END IF; WHEN PPBPG => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; ELSIF oe THEN ------------------------------------------------------- --read status ------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; DOut_zd(15 downto 0) <= Status; END IF; IF PERR /= '1' AND NOT falling_edge(PERR) THEN IF NOT PR_FLAG AND StatusReg(7) /= '1' THEN PR_FLAG:=TRUE; BaseLoc := WBPage * 256; --Word program IF WBAddr(1) < 0 THEN wr_cnt := 0; END IF; FOR i IN wr_cnt downto 0 LOOP new_int := WBData(i); IF WBAddr(i) < 0 THEN old_int := -1; ELSIF PGMS_FLAG = PPB_BIT THEN old_bit(0) := PPB(SA); END IF; IF new_int > -1 THEN new_bit := to_slv(new_int,16); IF PGMS_FLAG = PPB_BIT THEN IF old_bit(0) = '0' THEN new_bit(0) := '0'; --PPB_FLAG END IF; new_bit(15 downto 1) := (others => '0'); ELSE new_bit(0) := 'X'; END IF; IF new_bit(0)/='X' THEN new_int := to_nat(new_bit); WBData(i) := new_int; ELSE WBData(i) := -1; END IF; ELSE WBData(i) := -1; END IF; END LOOP; IF PGMS_FLAG = PPB_BIT THEN PPB(SA) := 'X'; END IF; END IF; IF PDONE = '1' AND (NOT PERR'EVENT) THEN PR_FLAG :=FALSE; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 AND WBdata(i) > -1 THEN IF PGMS_FLAG = PPB_BIT THEN IF PPBLock = '1' THEN PPB(SA) := '0'; ELSE old_PPB := to_slv(WBData(i),16); PPB(SA) := old_PPB(0); END IF; END IF; END IF; WBData(i) := -1; END LOOP; END IF; END IF; IF PERR'EVENT THEN StatusReg(4) := '1'; END IF; IF rising_edge(PDONE) OR falling_edge(PERR) THEN StatusReg(7) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN PPBER => IF falling_edge(write) THEN IF Addr = 16#555# AND DataLo = 16#70# AND STAT_ACT = '0' THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN ------------------------------------------------------- --read status Erase Busy ------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; IF Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); --toggle END IF; DOut_zd(15 downto 0) <= Status; END IF; IF EERR /= '1' AND StatusReg(7) /= '1' THEN IF NOT ER_FLAG THEN ER_FLAG:= TRUE; IF PPBLock = '1' THEN PPB := (OTHERS => 'X'); END IF; END IF; IF EDONE = '1' THEN ER_FLAG:= FALSE; IF PPBLock = '1' THEN PPB := (OTHERS => '1'); END IF; StatusReg(7) := '1'; END IF; END IF; IF EERR'EVENT THEN StatusReg(5) := '1'; END IF; --busy signal active RY_zd <= '0'; WHEN PPBEXT => NULL; WHEN PPBLB => IF falling_edge(write) THEN IF (A_PAT_1) AND (DataLo = 16#70#) AND (STAT_ACT = '0') THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN DOut_zd(15 downto 1) <= (OTHERS => '0'); DOut_zd(0) <= PPBLock; END IF; WHEN PPBLBSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd <= StatusReg; STAT_ACT <= '0'; END IF; WHEN PPBLBPG1 => IF falling_edge(write) THEN IF (DataLo = 16#00#) THEN PBPROG_in <= '0', '1' AFTER 1 ns; END IF; END IF; WHEN PPBLBSET => IF rising_edge(PBPROG_out) THEN PPBLock := '0'; PBPROG_in <= '0'; END IF; WHEN PPBLBEXT => NULL; WHEN DYB_ASO => IF falling_edge(write) THEN IF (A_PAT_1) AND (DataLo = 16#70#) AND (STAT_ACT = '0') THEN STAT_ACT <= '1'; ELSIF Addr = 16#555# AND DataLo = 16#71# THEN StatusReg(5 DOWNTO 3) := "000"; StatusReg(1) := '0'; STAT_ACT <= '0'; END IF; END IF; IF oe THEN DOut_zd(15 downto 1) <= (OTHERS => '0'); DOut_zd(0) <= DYB(SecAddr); END IF; WHEN DYBSR => IF (oe AND STAT_ACT = '1') THEN DOut_zd <= StatusReg; STAT_ACT <= '0'; END IF; WHEN DYBSET => IF falling_edge(write) THEN IF DataLo = 16#00# THEN DYB(SecAddr) := '0'; ELSIF DataLo = 16#01# THEN DYB(SecAddr) := '1'; END IF; END IF; WHEN DYBEXT => NULL; END CASE; END IF; --Output Disable Control IF (gOE_n = '1') OR (RESETNeg = '0'AND RST = '0') THEN DOut_zd <= (OTHERS => 'Z'); END IF; --Preload Control ------------------------------------------------------------------------------- -- File Read Section ------------------------------------------------------------------------------- IF NOW = 0 ns THEN LockReg(15 downto 9) := ( OTHERS => '1'); LockReg(8) := '0'; LockReg(7) := 'X'; LockReg(6 downto 0) := ( OTHERS => '1'); PPB := (OTHERS => '1');-- unprotected state DYB := (OTHERS => '1');-- unprotected state Password := (OTHERS => ( OTHERS => '1')); ------------------------------------------------------------------------------- -----s29gl128s sector protection preload file format------- ------------------ ------------------------------------------------------------------------------- -- / - comment -- @aaa - stands for sector address -- b - is 1 for protected sector , 0 for unprotect. -- If > SecNum SecSi is protected/unprotected -- only first 1-4 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- IF (prot_file_name /= "none" AND UserPreload ) THEN ind := 0; FactoryProt <= '0'; WHILE (not ENDFILE (prot_file)) LOOP READLINE (prot_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 4)); --address ELSE IF ind > SecNum THEN --SecSi Factory protect preload IF buf(1) = '1' THEN FactoryProt <= '1'; END IF; ELSE -- Standard Sector preload IF buf(1) = '1' THEN PPB(ind) := '0';-- protected state '0' END IF; ind := ind + 1; END IF; END IF; END LOOP; END IF; ------------------------------------------------------------------------------- -----s29gl128s SecSi preload file format- ----------------------------------- ------------------------------------------------------------------------------- -- / - comment -- @aaa - stands for address -- dddd - is word to be written at SecSi(aaa++) -- (aaa is incremented at every load) -- only first 1-4 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- IF (SecSi_file_name /= "none" AND UserPreload ) THEN SecSi := (OTHERS => MaxData); ind := 0; WHILE (not ENDFILE (SecSi_file)) LOOP READLINE (SecSi_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 4)); --address ELSE IF ind <= SecSiSize THEN SecSi(ind) := h(buf(1 TO 4)); ind := ind + 1; END IF; END IF; END LOOP; END IF; ------------------------------------------------------------------------------- -----s29gl128s memory preload file format ----------------------------------- ------------------------------------------------------------------------------- -- / - comment -- @aaaaaaa - stands for address within sector -- dd -
is byte to be written at Mem(*)(aaaaaaa++) -- (aaaaaaa is incremented at every load) -- only first 1-7 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- IF (mem_file_name /= "none" ) THEN ind := 0; S_ind := 0; Mem := (OTHERS => (OTHERS => MaxData)); -- load sector 0 WHILE (not ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 7)); --address ELSE IF ind=0 THEN S_ind := 0; index := 0; Mem(S_ind)(index) := h(buf(1 to 4)); ind := ind + 1; ELSIF ind < SecSize+1 THEN S_ind := 0; index := ind; Mem(S_ind)(index) := h(buf(1 to 4)); ind := ind + 1; ELSIF ind <= AddrRANGE THEN S_ind := NATURAL(ind / (SecSize +1)); index := ind - S_ind*(SecSize+1); Mem(S_ind)(index) := h(buf(1 to 4)); ind := ind + 1; ELSE REPORT " Memory address out of range" SEVERITY warning; END IF; END IF; END LOOP; END IF; ----------------------------------------------------------------------- --CFI array data ----------------------------------------------------------------------- --CFI query identification string CFI_array(16#10#) := 16#0051#; CFI_array(16#11#) := 16#0052#; CFI_array(16#12#) := 16#0059#; CFI_array(16#13#) := 16#0002#; CFI_array(16#14#) := 16#0000#; CFI_array(16#15#) := 16#0040#; CFI_array(16#16#) := 16#0000#; CFI_array(16#17#) := 16#0000#; CFI_array(16#18#) := 16#0000#; CFI_array(16#19#) := 16#0000#; CFI_array(16#1A#) := 16#0000#; --System interface string CFI_array(16#1B#) := 16#0027#; CFI_array(16#1C#) := 16#0036#; CFI_array(16#1D#) := 16#0000#; CFI_array(16#1E#) := 16#0000#; CFI_array(16#1F#) := 16#0008#; CFI_array(16#20#) := 16#0009#; CFI_array(16#21#) := 16#0008#; CFI_array(16#22#) := 16#000F#; CFI_array(16#23#) := 16#0002#; CFI_array(16#24#) := 16#0002#; CFI_array(16#25#) := 16#0003#; CFI_array(16#26#) := 16#0003#; --Device Geometry Definition CFI_array(16#27#) := 16#0018#; CFI_array(16#28#) := 16#0001#; CFI_array(16#29#) := 16#0000#; CFI_array(16#2A#) := 16#0009#; CFI_array(16#2B#) := 16#0000#; CFI_array(16#2C#) := 16#0001#; CFI_array(16#2D#) := 16#007F#; CFI_array(16#2E#) := 16#0000#; CFI_array(16#2F#) := 16#0000#; CFI_array(16#30#) := 16#0002#; CFI_array(16#31#) := 16#0000#; CFI_array(16#32#) := 16#0000#; CFI_array(16#33#) := 16#0000#; CFI_array(16#34#) := 16#0000#; CFI_array(16#35#) := 16#0000#; -- CFI_array(16#36#) := 16#0000#; CFI_array(16#37#) := 16#0000#; CFI_array(16#38#) := 16#0000#; CFI_array(16#39#) := 16#0000#; CFI_array(16#3A#) := 16#0000#; CFI_array(16#3B#) := 16#0000#; CFI_array(16#3C#) := 16#0000#; --primary vendor-specific extended query CFI_array(16#40#) := 16#0050#; CFI_array(16#41#) := 16#0052#; CFI_array(16#42#) := 16#0049#; CFI_array(16#43#) := 16#0031#; CFI_array(16#44#) := 16#0035#; CFI_array(16#45#) := 16#001C#; CFI_array(16#46#) := 16#0002#; CFI_array(16#47#) := 16#0001#; CFI_array(16#48#) := 16#0000#; CFI_array(16#49#) := 16#0008#; CFI_array(16#4A#) := 16#0000#; CFI_array(16#4B#) := 16#0000#; CFI_array(16#4C#) := 16#0003#; CFI_array(16#4D#) := 16#0000#; CFI_array(16#4E#) := 16#0000#; IF TimingModel(16) = '1' THEN CFI_array(16#4F#) := 16#0005#;--top boot ELSIF TimingModel(16) = '2' THEN CFI_array(16#4F#) := 16#0004#;--bottom END IF; CFI_array(16#50#) := 16#0001#; CFI_array(16#51#) := 16#0000#; CFI_array(16#52#) := 16#0009#; CFI_array(16#53#) := 16#008F#; CFI_array(16#54#) := 16#0005#; CFI_array(16#55#) := 16#0006#; CFI_array(16#56#) := 16#0006#; CFI_array(16#78#) := 16#0006#; CFI_array(16#79#) := 16#0009#; END IF; END PROCESS Functional; ------------------------------------------------------------------------------- -----***timing processes*** ------------------------------------------------------------------------------- Start_T1_time : PROCESS (START_T1_in) BEGIN IF rising_edge ( START_T1_in ) THEN IF LongTimming = TRUE THEN sSTART_T1 <= '0', '1' AFTER tdevice_START_T1; ELSE sSTART_T1 <= '0', '1' AFTER tdevice_START_T1/1; END IF; ELSE sSTART_T1 <= '0'; END IF; END PROCESS Start_T1_time; READY_time : PROCESS (READY_in) BEGIN IF rising_edge ( READY_in ) THEN IF LongTimming = TRUE THEN sREADY <= '0', '1' AFTER (tdevice_READY - 1 ns); ELSE sREADY <= '0', '1' AFTER (tdevice_READY - 1 ns)/10; END IF; ELSE sREADY <= '0'; END IF; END PROCESS READY_time; ------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------- DOutPassThrough : PROCESS(DOut_zd) VARIABLE ValidData : std_logic_vector(15 downto 0); VARIABLE CEDQ_t : TIME; VARIABLE OEDQ_t : TIME; VARIABLE ADDRDQ_t : TIME; BEGIN IF DOut_zd(0) /= 'Z' THEN OPENLATCH := TRUE; CEDQ_t := -CENeg'LAST_EVENT + tpd_CENeg_DQ0(trz0); OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_DQ0(trz0); ADDRDQ_t := -A'LAST_EVENT + tpd_A0_DQ0(tr01);-- FROMOE := (OEDQ_t >= CEDQ_t) AND (OEDQ_t > 0 ns); FROMCE := (CEDQ_t > OEDQ_t) AND (CEDQ_t > 0 ns); ValidData := "XXXXXXXXXXXXXXXX"; IF ((ADDRDQ_t > 0 ns) AND (((ADDRDQ_t > CEDQ_t) AND FROMCE) OR ((ADDRDQ_t > OEDQ_t) AND FROMOE))) THEN DOut_Pass <= ValidData, DOut_zd AFTER ADDRDQ_t; ELSE DOut_Pass <= DOut_zd; END IF; ELSE OPENLATCH := FALSE; DOut_Pass <= DOut_zd; END IF; END PROCESS DOutPassThrough; ----------------------------------------------------------------------- -- Path Delay Section ----------------------------------------------------------------------- RY_OUT: PROCESS(RY_zd) VARIABLE RY_tmp : std_logic; VARIABLE RY_GlitchData : VitalGlitchDataType; BEGIN IF RY_zd = '1' THEN RY_tmp := 'Z'; ELSE RY_tmp := RY_zd; END IF; VitalPathDelay01( OutSignal => RY, OutSignalName => "RY/BY#", OutTemp => RY_tmp, Mode => VitalTransport, GlitchData => RY_GlitchData, Paths => ( 0 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_RY, PathCondition => TRUE), 1 => (InputChangeTime => WENeg'LAST_EVENT, PathDelay => tpd_WENeg_RY, PathCondition => TRUE), 2 => (InputChangeTime => sREADY'LAST_EVENT, -- Device ready after PathDelay => VitalZeroDelay01, -- reset PathCondition => EDONE = '1' OR PDONE = '1'), 3 => (InputChangeTime => EDONE'LAST_EVENT, PathDelay => VitalZeroDelay01, PathCondition => EDONE = '1'), 4 => (InputChangeTime => PDONE'LAST_EVENT, PathDelay => VitalZeroDelay01, PathCondition => PDONE = '1') ) ); END PROCESS RY_Out; --------------------------------------------------------------------------- -- Path Delay Section for DOut signal --------------------------------------------------------------------------- D_Out_PathDelay_Gen : FOR i IN DOut_Pass'RANGE GENERATE PROCESS(DOut_Pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_Pass(i), GlitchData => D0_GlitchData, Mode => VitalTransport, Paths => ( 0 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_DQ0, PathCondition => NOT OPENLATCH OR (OPENLATCH AND FROMCE)), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ0, PathCondition => NOT OPENLATCH OR (OPENLATCH AND FROMOE)), 2 => (InputChangeTime => RESETNeg'LAST_EVENT, PathDelay => tpd_RESETNeg_DQ0, PathCondition => RESETNeg='0'), 3 => (InputChangeTime => A'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => DOut_pass(i) /= 'X' AND RPchange), 4 => (InputChangeTime => A'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ1), PathCondition => DOut_pass(i)/= 'X' AND (NOT RPchange)) ) ); END PROCESS; END GENERATE D_Out_PathDelay_Gen; END BLOCK behavior; END vhdl_behavioral;