------------------------------------------------------------------------------- -- File name : s29gl064a_s3_s4.vhd ------------------------------------------------------------------------------- -- Copyright (C) 2005-2006 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V1.0 D. Lukovic 05 Jun 01 Initial release -- V1.1 I.Milutinovic 06 Feb 27 Implemented new LongTimming option -- ------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FLASH -- Technology: Flash Memory -- Part: S29GL064A_S3 -- S29GL064A_S4 -- -- Description: 64Mbit (x16) Page Mode Flash Memory -- Permanent Incremental Lock Security device ------------------------------------------------------------------------------- -- Known Bugs: -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY s29gl064a_s3_s4 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; --address tipd_A10 : VitalDelayType01 := VitalZeroDelay01; --lines tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A18 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A19 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A20 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A21 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- DQ15/A-1 tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; --WP#/ACC -- tpd delays tpd_A0_DQ0 : VitalDelayType01 := UnitDelay01;--tACC tpd_A0_DQ1 : VitalDelayType01 := UnitDelay01;--tPACC tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tCE,tCE,tDF,-,tDF,-) tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tOE,tOE,tDF,-,tDF,-) tpd_RESETNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(-,-,0,-,0,-) tpd_CENeg_RY : VitalDelayType01 := UnitDelay01; --tBUSY tpd_WENeg_RY : VitalDelayType01 := UnitDelay01; --tBUSY --tsetup values tsetup_A0_CENeg : VitalDelayType := UnitDelay; --tAS edge \ tsetup_A0_OENeg : VitalDelayType := UnitDelay; --tASO edge \ tsetup_DQ0_CENeg : VitalDelayType := UnitDelay; --tDS edge / --thold values thold_CENeg_RESETNeg: VitalDelayType := UnitDelay; --tRH edge / thold_A0_CENeg : VitalDelayType := UnitDelay; --tAH edge \ thold_A0_OENeg : VitalDelayType := UnitDelay; --tAHT edge \ thold_DQ0_CENeg : VitalDelayType := UnitDelay; --tDH edge / thold_OENeg_WENeg_noedge_negedge : VitalDelayType := UnitDelay; --tOEH edge / thold_OENeg_WENeg_noedge_posedge : VitalDelayType := UnitDelay; --tOEH edge / --tpw values: pulse width tpw_RESETNeg_negedge: VitalDelayType := UnitDelay; --tRP tpw_OENeg_posedge : VitalDelayType := UnitDelay; --tOEPH tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP tpw_WENeg_posedge : VitalDelayType := UnitDelay; --tWPH tpw_CENeg_negedge : VitalDelayType := UnitDelay; --tCP tpw_CENeg_posedge : VitalDelayType := UnitDelay; --tCEPH tpw_A0_negedge : VitalDelayType := UnitDelay; --tWC tRC -- tdevice values: values for internal delays --Effective Write Buffer Program Operation tWHWH1 tdevice_WBPB : VitalDelayType := 15000 ns; --Program Operation tdevice_POB : VitalDelayType := 60 us; --Sector Erase Operation tWHWH2 tdevice_SEO : VitalDelayType := 500 ms; --Timing Limit Exceeded tdevice_HANG : VitalDelayType := 400 ms; --erase suspend timeout tdevice_START_ET1 : VitalDelayType := 5 us; --program suspend timeout tdevice_START_PT1 : VitalDelayType := 5 us; --Permanent lock algorithm duration tdevice_PLS : VitalDelayType := 150 us; --sector erase command sequence timeout tdevice_CTMOUT : VitalDelayType := 50 us; --device ready after Hardware reset(during embeded algorithm) tdevice_READY : VitalDelayType := 20 us; --tReady -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING := "none";--"s29gl064a_s3_s4.mem"; prot_file_name : STRING := "none";--"s29gl064a_s3_s4_prot.mem"; secsi_file_name : STRING := "none";--"s29gl064a_s3_s4_secsi.mem"; UserPreload : BOOLEAN := FALSE; --TRUE; LongTimming : BOOLEAN := TRUE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A21 : IN std_ulogic := 'U'; -- A20 : IN std_ulogic := 'U'; -- A19 : IN std_ulogic := 'U'; -- A18 : IN std_ulogic := 'U'; -- A17 : IN std_ulogic := 'U'; -- A16 : IN std_ulogic := 'U'; -- A15 : IN std_ulogic := 'U'; -- A14 : IN std_ulogic := 'U'; -- A13 : IN std_ulogic := 'U'; --address A12 : IN std_ulogic := 'U'; --lines A11 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A8 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- A6 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A1 : IN std_ulogic := 'U'; -- A0 : IN std_ulogic := 'U'; -- DQ15 : INOUT std_ulogic := 'U'; -- DQ15/A-1 DQ14 : INOUT std_ulogic := 'U'; -- DQ13 : INOUT std_ulogic := 'U'; -- DQ12 : INOUT std_ulogic := 'U'; -- DQ11 : INOUT std_ulogic := 'U'; -- DQ10 : INOUT std_ulogic := 'U'; -- DQ9 : INOUT std_ulogic := 'U'; -- data DQ8 : INOUT std_ulogic := 'U'; -- lines DQ7 : INOUT std_ulogic := 'U'; -- DQ6 : INOUT std_ulogic := 'U'; -- DQ5 : INOUT std_ulogic := 'U'; -- DQ4 : INOUT std_ulogic := 'U'; -- DQ3 : INOUT std_ulogic := 'U'; -- DQ2 : INOUT std_ulogic := 'U'; -- DQ1 : INOUT std_ulogic := 'U'; -- DQ0 : INOUT std_ulogic := 'U'; -- CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U';--WP#/ACC RY : OUT std_ulogic := 'U'--RY/BY# ); ATTRIBUTE VITAL_LEVEL0 of s29gl064a_s3_s4 : ENTITY IS TRUE; END s29gl064a_s3_s4; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of s29gl064a_s3_s4 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT PartID : STRING := "s29gl064a_s3_s4"; CONSTANT MaxData : NATURAL := 16#FFFF#; --65535 CONSTANT SecSize : NATURAL := 16#7FFF#; --32767 CONSTANT SecSiSize : NATURAL := 127; CONSTANT SecNum : NATURAL := 127; --may be changed to 64 for debug CONSTANT HiAddrBit : NATURAL := 21; CONSTANT AddrRANGE : NATURAL := 16#3FFFFF#; -- interconnect path delay signals SIGNAL A21_ipd : std_ulogic := 'U'; SIGNAL A20_ipd : std_ulogic := 'U'; SIGNAL A19_ipd : std_ulogic := 'U'; SIGNAL A18_ipd : std_ulogic := 'U'; SIGNAL A17_ipd : std_ulogic := 'U'; SIGNAL A16_ipd : std_ulogic := 'U'; SIGNAL A15_ipd : std_ulogic := 'U'; SIGNAL A14_ipd : std_ulogic := 'U'; SIGNAL A13_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL CENeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; SIGNAL WPNeg_ipd : std_ulogic := 'U'; --- internal delays SIGNAL WBPO_in : std_ulogic := '0'; SIGNAL WBPO_out : std_ulogic := '0'; SIGNAL PO_in : std_ulogic := '0'; SIGNAL PO_out : std_ulogic := '0'; SIGNAL SEO_in : std_ulogic := '0'; SIGNAL SEO_out : std_ulogic := '0'; SIGNAL HANG_out : std_ulogic := '0'; --Program/Erase Timing Limit SIGNAL HANG_in : std_ulogic := '0'; SIGNAL sSTART_ET1 : std_ulogic := '0'; --Start TimeOut SIGNAL START_ET1_in : std_ulogic := '0'; SIGNAL sSTART_PT1 : std_ulogic := '0'; --Start TimeOut SIGNAL START_PT1_in : std_ulogic := '0'; SIGNAL sCTMOUT : std_ulogic := '0'; --Sector Erase TimeOut SIGNAL CTMOUT_in : std_ulogic := '0'; SIGNAL READY_in : std_ulogic := '0'; SIGNAL sREADY : std_ulogic := '0'; --Device ready after reset SIGNAL PLS_in : std_ulogic := '0'; SIGNAL sPLS : std_ulogic := '0'; --Permanent locking done SIGNAL sSTART_ET1t : std_ulogic := '0'; --Start TimeOut SIGNAL START_ET1_int : std_ulogic := '0'; SIGNAL sSTART_PT1t : std_ulogic := '0'; --Start TimeOut SIGNAL START_PT1_int : std_ulogic := '0'; SIGNAL sCTMOUTt : std_ulogic := '0'; --Sector Erase TimeOut SIGNAL CTMOUT_int : std_ulogic := '0'; SIGNAL READY_int : std_ulogic := '0'; SIGNAL sREADYt : std_ulogic := '0'; --Device ready after reset SIGNAL PLS_int : std_ulogic := '0'; SIGNAL sPLSt : std_ulogic := '0'; --Permanent locking done BEGIN --------------------------------------------------------------------------- -- Internal Delays --------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays WBPB :VitalBuf(WBPO_out,WBPO_in, (tdevice_WBPB ,UnitDelay)); POB :VitalBuf(PO_out, PO_in, (tdevice_POB ,UnitDelay)); SEO :VitalBuf(SEO_out, SEO_in, (tdevice_SEO ,UnitDelay)); HANG :VitalBuf(HANG_out,HANG_in, (tdevice_HANG ,UnitDelay)); START_ET1:VitalBuf(sSTART_ET1t, START_ET1_int, (tdevice_START_ET1 - 3 ns,UnitDelay)); START_PT1:VitalBuf(sSTART_PT1t, START_PT1_int, (tdevice_START_PT1 - 3 ns,UnitDelay)); CTMOUT :VitalBuf(sCTMOUTt, CTMOUT_int, (tdevice_CTMOUT - 4 ns ,UnitDelay)); READY :VitalBuf(sREADYt, READY_int, (tdevice_READY ,UnitDelay)); PLS :VitalBuf(sPLSt, PLS_int, (tdevice_PLS ,UnitDelay)); --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (A21_ipd, A21, tipd_A21); w_2 : VitalWireDelay (A20_ipd, A20, tipd_A20); w_3 : VitalWireDelay (A19_ipd, A19, tipd_A19); w_4 : VitalWireDelay (A18_ipd, A18, tipd_A18); w_5 : VitalWireDelay (A17_ipd, A17, tipd_A17); w_6 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_7 : VitalWireDelay (A15_ipd, A15, tipd_A15); w_8 : VitalWireDelay (A14_ipd, A14, tipd_A14); w_9 : VitalWireDelay (A13_ipd, A13, tipd_A13); w_10 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_11 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_12 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_13 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_14 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_15 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_16 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_17 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_18 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_19 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_20 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_21 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_22 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_23 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15); w_24 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14); w_25 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13); w_26 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12); w_27 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11); w_28 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10); w_29 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9); w_30 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8); w_31 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7); w_32 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6); w_33 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5); w_34 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4); w_35 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_36 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_37 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_38 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_39 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_40 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_41 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg); w_42 : VitalWireDelay (WPNeg_ipd, WPNeg, tipd_WPNeg); w_44 : VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg); END BLOCK; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior: BLOCK PORT ( A : IN std_logic_vector(HiAddrBit downto 0) := (OTHERS => 'U'); DIn : IN std_logic_vector(15 downto 0) := (OTHERS => 'U'); DOut : OUT std_ulogic_vector(15 downto 0) := (OTHERS => 'Z'); CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; RY : OUT std_ulogic := 'U' ); PORT MAP ( A(21) => A21_ipd, A(20) => A20_ipd, A(19) => A19_ipd, A(18) => A18_ipd, A(17) => A17_ipd, A(16) => A16_ipd, A(15) => A15_ipd, A(14) => A14_ipd, A(13) => A13_ipd, A(12) => A12_ipd, A(11) => A11_ipd, A(10) => A10_ipd, A(9) => A9_ipd, A(8) => A8_ipd, A(7) => A7_ipd, A(6) => A6_ipd, A(5) => A5_ipd, A(4) => A4_ipd, A(3) => A3_ipd, A(2) => A2_ipd, A(1) => A1_ipd, A(0) => A0_ipd, DIn(15) => DQ15_ipd, DIn(14) => DQ14_ipd, DIn(13) => DQ13_ipd, DIn(12) => DQ12_ipd, DIn(11) => DQ11_ipd, DIn(10) => DQ10_ipd, DIn(9) => DQ9_ipd, DIn(8) => DQ8_ipd, DIn(7) => DQ7_ipd, DIn(6) => DQ6_ipd, DIn(5) => DQ5_ipd, DIn(4) => DQ4_ipd, DIn(3) => DQ3_ipd, DIn(2) => DQ2_ipd, DIn(1) => DQ1_ipd, DIn(0) => DQ0_ipd, DOut(15) => DQ15, DOut(14) => DQ14, DOut(13) => DQ13, DOut(12) => DQ12, DOut(11) => DQ11, DOut(10) => DQ10, DOut(9) => DQ9, DOut(8) => DQ8, DOut(7) => DQ7, DOut(6) => DQ6, DOut(5) => DQ5, DOut(4) => DQ4, DOut(3) => DQ3, DOut(2) => DQ2, DOut(1) => DQ1, DOut(0) => DQ0, CENeg => CENeg_ipd, OENeg => OENeg_ipd, WENeg => WENeg_ipd, RESETNeg => RESETNeg_ipd, WPNeg => WPNeg_ipd, RY => RY ); -- State Machine : State_Type TYPE state_type IS ( RESET, Z001, PREL_SETBWB, PREL_ULBYPASS, PREL_ULBYPASS_RESET, CFI, AS, AS_CFI, A0SEEN, OTP, OTP_Z001, OTP_PREL, OTP_A0SEEN, OTP_AS, OTP_AS_CFI, C8, C8_Z001, C8_PREL, ERS, SERS, ESPS, WBPGMS_WBCNT, WBPGMS_WBLSTA, WBPGMS_WBLOAD, WBPGMS_CONFB, WBPGMS_WBABORT, WBPGMS_Z001, WBPGMS_PREL, SERS_EXEC, ESP, ESP_Z001, ESP_PREL, ESP_CFI, ESP_A0SEEN, ESP_AS, ESP_AS_CFI, PGMS, PSPS, PSP, PSP_CFI, PSP_Z001, PSP_PREL, PSP_AS, PSP_AS_CFI, PLS_Z001, PLS_WAIT, PLS_VER1 ); -- states SIGNAL current_state : state_type; SIGNAL next_state : state_type; -- powerup SIGNAL PoweredUp : std_logic := '0'; --zero delay signals SIGNAL DOut_zd : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL DOut_Pass : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL RY_zd : std_logic := 'Z'; --FSM control signals SIGNAL ULBYPASS : std_logic := '0'; --Unlock Bypass Active SIGNAL OTP_ACT : std_logic := '0'; --SecSi access SIGNAL PSP_ACT : std_logic := '0'; --Program Suspend SIGNAL ESP_ACT : std_logic := '0'; --Erase Suspend SIGNAL LCNT : NATURAL RANGE 0 TO 31:= 0; --Load Counter --number of location to be writen in Write Buffer: 0-15 bytes. --if 16 word/byte programming SIGNAL PCNT : NATURAL RANGE 0 TO 16:= 0; --Model should never hang!!!!!!!!!!!!!!! SIGNAL HANG : std_logic := '0'; SIGNAL PDONE : std_logic := '1'; --Prog. Done SIGNAL PSTART : std_logic := '0'; --Start Programming SIGNAL PSUSP : std_logic := '0'; --Suspend programming SIGNAL PRES : std_logic := '0'; --Resume Programming --Program location is in protected sector SIGNAL PERR : std_logic := '0'; SIGNAL EDONE : std_logic := '1'; --Ers. Done SIGNAL ESTART : std_logic := '0'; --Start Erase SIGNAL ESUSP : std_logic := '0'; --Suspend Erase SIGNAL ERES : std_logic := '0'; --Resume Erase --All sectors selected for erasure are protected SIGNAL EERR : std_logic := '0'; --Sectors selected for erasure SIGNAL ERS_QUEUE : std_logic_vector(SecNum downto 0) := (OTHERS => '0'); --Command Register SIGNAL write : std_logic := '0'; SIGNAL read : std_logic := '0'; --Sector Address SIGNAL SecAddr : NATURAL RANGE 0 TO SecNum := 0; SIGNAL SA : NATURAL RANGE 0 TO SecNum := 0; SIGNAL WBPage : NATURAL; --Address within sector SIGNAL Address : NATURAL RANGE 0 TO SecSize := 0; SIGNAL Addr2 : std_logic_vector(7 downto 0) := (OTHERS => '0'); SIGNAL D_tmp0 : NATURAL RANGE 0 TO 16#FF#; SIGNAL D_tmp1 : NATURAL RANGE 0 TO MaxData; --A21:A11 Don't Care SIGNAL Addr : NATURAL RANGE 0 TO 16#7FF# := 0; SIGNAL WPage : NATURAL RANGE 0 TO 16#7FF# := 0; SIGNAL RPage : NATURAL RANGE 0 TO 16#2000# := 0; SIGNAL RPChange : boolean := true; --glitch protection SIGNAL gWE_n : std_logic := '1'; SIGNAL gCE_n : std_logic := '1'; SIGNAL gOE_n : std_logic := '1'; SIGNAL RST : std_logic := '1'; SIGNAL reseted : std_logic := '0'; SHARED VARIABLE Sec_Prot: std_logic_vector(SecNum downto 0) := (OTHERS => '0'); --SecSi ProtectionStatus SIGNAl FactoryProt : std_logic := '0'; --timing check violation SIGNAL Viol : X01 := '0'; SIGNAL pls_flag : std_logic := '0'; SIGNAL pls_flag2 : std_logic := '0'; --Address of the Protected Sector SIGNAL ProtSecNum : NATURAL ; --Access time variables SHARED VARIABLE OPENLATCH : BOOLEAN; SHARED VARIABLE FROMCE : BOOLEAN; SHARED VARIABLE FROMOE : BOOLEAN; FUNCTION READMEM(Data : INTEGER RANGE -1 TO MaxData) RETURN STD_LOGIC_VECTOR IS VARIABLE ReadData : STD_LOGIC_VECTOR(15 downto 0); BEGIN IF Data = -1 THEN ReadData := (OTHERS=>'X'); ELSE ReadData := to_slv(Data,16); END IF; RETURN ReadData; END READMEM; BEGIN --------------------------------------------------------------------------- --Power Up time 100 ns; --------------------------------------------------------------------------- PoweredUp <= '1' AFTER 100 ns; RST <= RESETNeg AFTER 500 ns; --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS(A, Din, CENeg, OENeg, WENeg, RESETNeg, WPNeg) -- Timing Check Variables VARIABLE Tviol_A0_CENeg : X01 := '0'; VARIABLE TD_A0_CENeg : VitalTimingDataType; VARIABLE Tviol_A0_WENeg : X01 := '0'; VARIABLE TD_A0_WENeg : VitalTimingDataType; VARIABLE Tviol_A0_OENeg : X01 := '0'; VARIABLE TD_A0_OENeg : VitalTimingDataType; VARIABLE Tviol_DQ0_WENeg : X01 := '0'; VARIABLE TD_DQ0_WENeg : VitalTimingDataType; VARIABLE Tviol_DQ0_CENeg : X01 := '0'; VARIABLE TD_DQ0_CENeg : VitalTimingDataType; VARIABLE Tviol_CENeg_RESETNeg : X01 := '0'; VARIABLE TD_CENeg_RESETNeg : VitalTimingDataType; VARIABLE Tviol_OENeg_RESETNeg : X01 := '0'; VARIABLE TD_OENeg_RESETNeg : VitalTimingDataType; VARIABLE Tviol_OENeg_WENeg : X01 := '0'; VARIABLE TD_OENeg_WENeg : VitalTimingDataType; VARIABLE Tviol_OENeg_WENeg_R: X01 := '0'; VARIABLE TD_OENeg_WENeg_R : VitalTimingDataType; VARIABLE Pviol_RESETNeg : X01 := '0'; VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_OENeg : X01 := '0'; VARIABLE PD_OENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CENeg : X01 := '0'; VARIABLE PD_CENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg : X01 := '0'; VARIABLE PD_WENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A0 : X01 := '0'; VARIABLE PD_A0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN --------------------------------------------------------------------------- -- Timing Check Section --------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Setup/Hold Check between A and CENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => CENeg, RefSignalName => "CE#", SetupHigh => tsetup_A0_CENeg, SetupLow => tsetup_A0_CENeg, HoldHigh => thold_A0_CENeg, HoldLow => thold_A0_CENeg, CheckEnabled => WENeg = '0' AND OENeg = '1', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CENeg, Violation => Tviol_A0_CENeg ); -- Setup/Hold Check between A and WENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => tsetup_A0_CENeg, SetupLow => tsetup_A0_CENeg, HoldHigh => thold_A0_CENeg, HoldLow => thold_A0_CENeg, CheckEnabled => CENeg = '0' AND OENeg = '1', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_WENeg, Violation => Tviol_A0_WENeg ); -- Setup/Hold Check between A and OENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => OENeg, RefSignalName => "OE#", SetupHigh => tsetup_A0_OENeg, SetupLow => tsetup_A0_OENeg, HoldHigh => thold_A0_OENeg, HoldLow => thold_A0_OENeg, CheckEnabled => PDONE = '0' OR EDONE = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_OENeg, Violation => Tviol_A0_OENeg ); -- Setup/Hold Check between DQ and CENeg VitalSetupHoldCheck ( TestSignal => DQ0, TestSignalName => "DQ", RefSignal => CENeg, RefSignalName => "CE#", SetupHigh => tsetup_DQ0_CENeg, SetupLow => tsetup_DQ0_CENeg, HoldHigh => thold_DQ0_CENeg, HoldLow => thold_DQ0_CENeg, CheckEnabled => WENeg = '0' AND OENeg = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_CENeg, Violation => Tviol_DQ0_CENeg ); -- Setup/Hold Check between DQ and WENeg VitalSetupHoldCheck ( TestSignal => DQ0, TestSignalName => "DQ", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => tsetup_DQ0_CENeg, SetupLow => tsetup_DQ0_CENeg, HoldHigh => thold_DQ0_CENeg, HoldLow => thold_DQ0_CENeg, CheckEnabled => CENeg = '0' AND OENeg = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_WENeg, Violation => Tviol_DQ0_WENeg ); -- Hold Check between CENeg and RESETNeg VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CE#", RefSignal => RESETNeg, RefSignalName => "RESET#", HoldHigh => thold_CENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_RESETNeg, Violation => Tviol_CENeg_RESETNeg ); -- Hold Check between OENeg and RESETNeg VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OE#", RefSignal => RESETNeg, RefSignalName => "RESET#", HoldHigh => thold_CENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_RESETNeg, Violation => Tviol_OENeg_RESETNeg ); VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OE#", RefSignal => WENeg, RefSignalName => "WE#", HoldHigh => thold_OENeg_WENeg_noedge_posedge,--toeh HoldLow => thold_OENeg_WENeg_noedge_posedge,--toeh CheckEnabled => PDONE = '0' OR EDONE = '0',--toggle RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_WENeg, Violation => Tviol_OENeg_WENeg ); -- Hold Check between OENeg and WENeg VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OE#", RefSignal => WENeg, RefSignalName => "WE#", HoldHigh => thold_OENeg_WENeg_noedge_negedge,--toeh HoldLow => thold_OENeg_WENeg_noedge_negedge,--toeh CheckEnabled => PDONE = '1' AND EDONE = '1', --read RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_WENeg_R, Violation => Tviol_OENeg_WENeg_R ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESET#", PulseWidthLow => tpw_RESETNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg, Violation => Pviol_RESETNeg ); -- PulseWidth Check for OENeg VitalPeriodPulseCheck ( TestSignal => OENeg, TestSignalName => "OE#", PulseWidthHigh => tpw_OENeg_posedge, CheckEnabled => PDONE = '0' OR EDONE = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_OENeg, Violation => Pviol_OENeg ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WE#", PulseWidthHigh => tpw_WENeg_posedge, PulseWidthLow => tpw_WENeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg, Violation => Pviol_WENeg ); -- PulseWidth Check for CENeg VitalPeriodPulseCheck ( TestSignal => CENeg, TestSignalName => "CE#", PulseWidthHigh => tpw_CENeg_posedge, PulseWidthLow => tpw_CENeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_CENeg, Violation => Pviol_CENeg ); -- PulseWidth Check for A VitalPeriodPulseCheck ( TestSignal => A(0), TestSignalName => "A", PulseWidthHigh => tpw_A0_negedge, PulseWidthLow => tpw_A0_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_A0, Violation => Pviol_A0 ); Violation := Tviol_A0_CENeg OR Tviol_A0_WENeg OR Tviol_A0_OENeg OR Tviol_DQ0_WENeg OR Tviol_DQ0_CENeg OR Tviol_CENeg_RESETNeg OR Tviol_OENeg_RESETNeg OR Tviol_OENeg_WENeg_R OR Tviol_OENeg_WENeg OR Pviol_RESETNeg OR Pviol_OENeg OR Pviol_CENeg OR Pviol_WENeg OR Pviol_A0 ; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS VITALTimingCheck; --------------------------------------------------------------------------- -- sequential process for reset control and FSM state transition --------------------------------------------------------------------------- StateTransition : PROCESS(next_state, RESETNeg, RST, sREADY, PDone, EDone, PoweredUp) VARIABLE R : std_logic := '0'; --prog or erase in progress VARIABLE E : std_logic := '0'; --reset timming error BEGIN IF PoweredUp = '1' THEN --Hardware reset timing control IF falling_edge(RESETNeg) THEN E := '0'; IF (PDONE = '0' OR EDONE = '0') THEN --if program or erase in progress READY_in <= '1'; R := '1'; ELSE READY_in <= '0'; R := '0'; --prog or erase not in progress END IF; ELSIF rising_edge(RESETNeg) AND RST = '1' THEN --RESET# pulse < tRP READY_in <= '0'; R := '0'; E := '1'; END IF; IF RESETNeg = '1' AND ( R = '0' OR (R = '1' AND sREADY = '1')) THEN current_state <= next_state; READY_in <= '0'; E := '0'; R := '0'; reseted <= '1'; ELSIF (R = '0' AND RESETNeg = '0' AND RST = '0') OR (R = '1' AND RESETNeg = '0' AND RST = '0' AND sREADY = '0') OR (R = '1' AND RESETNeg = '1' AND RST = '0' AND sREADY = '0') THEN current_state <= RESET; --reset start reseted <= '0'; END IF; ELSE current_state <= RESET; --reset reseted <= '0'; E := '0'; R := '0'; END IF; END PROCESS StateTransition; --------------------------------------------------------------------------- --Glitch Protection: Inertial Delay does not propagate pulses <5ns --------------------------------------------------------------------------- gWE_n <= WENeg AFTER 3 ns; gCE_n <= CENeg AFTER 3 ns; gOE_n <= OENeg AFTER 3 ns; --latch address on rising edge and data on falling edge of write write_dc: PROCESS (gWE_n, gCE_n, gOE_n, RESETNeg, reseted) BEGIN IF RESETNeg /= '0' AND reseted ='1' THEN IF (gWE_n = '0') AND (gCE_n = '0') AND (gOE_n = '1') THEN write <= '1'; ELSIF (gWE_n = '1' OR gCE_n = '1') AND gOE_n = '1' THEN write <= '0'; ELSE write <= 'X'; END IF; END IF; IF ((gWE_n = '1') AND (gCE_n = '0') AND (gOE_n = '0')) THEN read <= '1'; ELSE read <= '0'; END IF; END PROCESS write_dc; --------------------------------------------------------------------------- --Process that reports warning when changes on signals WE#, CE#, OE# are --discarded --------------------------------------------------------------------------- PulseWatch : PROCESS (WENeg, CENeg, OENeg, gWE_n, gCE_n, gOE_n) BEGIN IF NOW > 0 ns THEN IF (WENeg'EVENT AND gWE_n = WENeg) OR (CENeg'EVENT AND gCE_n = CENeg) OR (OENeg'EVENT AND gOE_n = OENeg) THEN ASSERT false REPORT "Glitch detected on write control signals" SEVERITY warning; END IF; END IF; END PROCESS PulseWatch; --------------------------------------------------------------------------- -- Latch address on falling edge of WE# or CE# what ever comes later -- Latches data on rising edge of WE# or CE# what ever comes first -- also Write cycle decode --------------------------------------------------------------------------- BusCycleDecode : PROCESS(A, Din, write, WENeg, CENeg, OENeg, reseted) VARIABLE A_tmp : NATURAL RANGE 0 TO 16#7FF#; VARIABLE SA_tmp : NATURAL RANGE 0 TO SecNum; VARIABLE A_tmp1 : NATURAL RANGE 0 TO SecSize; VARIABLE A_tmp2 : std_logic_vector ( 7 downto 0 ) := ( OTHERS => '0'); VARIABLE CE : std_logic; BEGIN IF reseted = '1' THEN IF (falling_edge(WENeg) AND CENeg ='0' AND OENeg = '1') OR (falling_edge(CENeg) AND WENeg/= OENeg ) OR (falling_edge(OENeg) AND WENeg ='1' AND CENeg = '0') OR (A'EVENT AND WENeg = '1' AND CENeg = '0' AND OENeg = '0') THEN A_tmp := to_nat(A(10 downto 0)); SA_tmp := to_nat(A(HiAddrBit downto 15)); A_tmp2 := A(7 downto 0); A_tmp1 := to_nat(A(14 downto 0)); ELSIF (rising_edge(WENeg) OR rising_edge(CENeg)) AND write = '1' THEN D_tmp0 <= to_nat(Din(7 downto 0)); D_tmp1 <= to_nat(Din); END IF; IF rising_edge(write) OR falling_edge(OENeg) OR ((A'EVENT ) AND WENeg = '1' AND CENeg = '0' AND OENeg = '0') THEN SecAddr <= SA_tmp; Address <= A_tmp1; WPage <= A_tmp1 / 16; IF (RPage /= (A_tmp1 / 4)) OR (CENeg /= CE) THEN RPchange <= true; ELSE RPchange <= false; END IF; RPage <= A_tmp1 / 4; CE := CENeg; Addr <= A_tmp; Addr2 <= A_tmp2; END IF; END IF; END PROCESS BusCycleDecode; --------------------------------------------------------------------------- -- Timing control for the Program/ Write Buffer Program Operations -- start/ suspend/ resume --------------------------------------------------------------------------- ProgTime : PROCESS(PSTART, PSUSP, PRES, ESP_ACT, OTP_ACT, reseted) VARIABLE cnt : NATURAL RANGE 0 TO SecNum + 1 := 0; VARIABLE elapsed : time; VARIABLE duration : time; VARIABLE start : time; VARIABLE pob : time; VARIABLE wbpb : time; BEGIN IF LongTimming THEN pob := tdevice_POB; wbpb := tdevice_WBPB; ELSE pob := tdevice_POB / 20; wbpb := tdevice_WBPB / 10; END IF; IF rising_edge(reseted) THEN PDONE <= '1'; --reset done, programing terminated ELSIF reseted = '1' THEN IF rising_edge(PSTART) AND PDONE = '1' THEN IF NOT(Sec_Prot(SA) = '1' OR (Ers_queue(SA) = '1' AND ESP_ACT = '1') OR (FactoryProt = '1' AND OTP_ACT = '1')) THEN IF PCNT < 16 THEN --buffer cnt := PCNT + 1; duration := cnt * wbpb; ELSE --Word/Byte program cnt := 1; duration := cnt * pob - 3 ns; END IF; elapsed := 0 ns; PDONE <= '0', '1' AFTER duration; start := NOW; ELSE PERR <= '1', '0' AFTER 1 us; END IF; ELSIF rising_edge(PSUSP) AND PDONE = '0' THEN elapsed := NOW - start; duration := duration - elapsed; PDONE <= '0'; ELSIF rising_edge(PRES) AND PDONE = '0' THEN start := NOW; PDONE <= '0', '1' AFTER duration; END IF; END IF; END PROCESS ProgTime; --------------------------------------------------------------------------- -- Timing control for the Erase Operations --------------------------------------------------------------------------- ErsTime :PROCESS(ESTART, ESUSP, ERES, Ers_Queue, reseted) VARIABLE cnt : NATURAL RANGE 0 TO SecNum + 1 := 0; VARIABLE elapsed : time; VARIABLE duration : time; VARIABLE start : time; VARIABLE seo : time; BEGIN IF LongTimming THEN seo := tdevice_SEO; ELSE seo := tdevice_SEO / 1000; END IF; IF rising_edge(reseted) THEN EDONE <= '1'; -- reset done, ERASE terminated ELSIF reseted = '1' THEN IF rising_edge(ESTART) AND EDONE = '1' THEN cnt := 0; FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN cnt := cnt + 1; END IF; END LOOP; IF cnt > 0 THEN elapsed := 0 ns; duration := cnt * seo; EDONE <= '0', '1' AFTER duration; start := NOW; ELSE EERR <= '1', '0' AFTER 100 us; END IF; ELSIF rising_edge(ESUSP) AND EDONE = '0' THEN elapsed := NOW - start; duration := duration - elapsed; EDONE <= '0'; ELSIF rising_edge(ERES) AND EDONE = '0' THEN start := NOW; EDONE <= '0', '1' AFTER duration; END IF; END IF; END PROCESS; --------------------------------------------------------------------------- -- Main Behavior Process -- combinational process for next state generation --------------------------------------------------------------------------- StateGen :PROCESS(write, Addr, D_tmp0, ULBYPASS, PDONE, EDONE, HANG, sCTMOUT, sSTART_ET1, sSTART_PT1, reseted, sREADY , PERR, sPLS, EERR) VARIABLE PATTERN_1 : boolean := FALSE; VARIABLE PATTERN_2 : boolean := FALSE; VARIABLE A_PAT_1 : boolean := FALSE; VARIABLE A_PAT_2 : boolean := FALSE; --DATA Low Byte VARIABLE DataLo : NATURAL RANGE 0 TO MaxData := 0; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(write) THEN DataLo := D_tmp0; PATTERN_1 := (Addr=16#555#) AND (DataLo = 16#AA#) ; PATTERN_2 := (Addr=16#2AA#) AND (DataLo = 16#55#) ; A_PAT_1 := ((Addr=16#555#) AND (ULBYPASS = '0')) OR (ULBYPASS = '1'); A_PAT_2 := (Addr2(6)='0' AND Addr2(3)='0' AND Addr2(2)='0' AND Addr2(1)='1' AND Addr2(0)='0'); END IF; IF reseted /= '1' THEN next_state <= current_state; ELSE CASE current_state IS WHEN RESET => IF falling_edge(write) THEN IF (PATTERN_1) THEN next_state <= Z001; ELSIF ((Addr=16#55#) AND (DataLo=16#98#)) THEN next_state <= CFI; ELSIF (A_PAT_2 AND (DataLo = 16#60#)) AND pls_flag2 = '1' THEN next_state <= PLS_WAIT; ELSIF (DataLo=16#60#) THEN next_state <= PLS_Z001; ELSE next_state <= RESET; END IF; END IF; WHEN Z001 => IF falling_edge(write) THEN IF (PATTERN_2) THEN next_state <= PREL_SETBWB; ELSE next_state <= RESET; END IF; END IF; WHEN PREL_SETBWB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#20#)) THEN next_state <= PREL_ULBYPASS; ELSIF (A_PAT_1 AND (DataLo=16#90#)) THEN next_state <= AS; ELSIF (A_PAT_1 AND (DataLo=16#A0#)) THEN next_state <= A0SEEN; ELSIF (A_PAT_1 AND (DataLo=16#88#)) THEN next_state <= OTP; ELSIF (A_PAT_1 AND (DataLo=16#80#)) THEN next_state <= C8; ELSIF (DataLo=16#25#) THEN next_state <= WBPGMS_WBCNT; ELSE next_state <= RESET; END IF; END IF; WHEN PREL_ULBYPASS => IF falling_edge(write) THEN IF (A_PAT_1 AND DataLo=16#20#) THEN next_state <= PREL_ULBYPASS; ELSIF (A_PAT_1 AND (DataLo=16#90#)) THEN next_state <= PREL_ULBYPASS_RESET; ELSIF (A_PAT_1 AND (DataLo=16#A0#)) THEN next_state <= A0SEEN; ELSE next_state <= PREL_ULBYPASS; END IF; END IF; WHEN PREL_ULBYPASS_RESET => IF falling_edge(write) THEN IF (DataLo=16#00#) THEN IF ESP_ACT = '1' THEN next_state <= ESP; ELSE next_state <= RESET; END IF; ELSE next_state <= PREL_ULBYPASS; END IF; END IF; WHEN CFI => IF falling_edge(write) THEN IF (Addr=16#55#) AND (DataLo=16#98#) THEN next_state <= CFI; ELSIF (DataLo=16#F0#) THEN next_state <= RESET; ELSE next_state <= CFI; END IF; END IF; WHEN AS => IF falling_edge(write) THEN IF (DataLo=16#F0#) THEN next_state <= RESET; ELSIF ((Addr=16#55#) AND (DataLo=16#98#)) THEN next_state <= AS_CFI; ELSE next_state <= AS; END IF; END IF; WHEN AS_CFI => IF falling_edge(write) THEN IF (DataLo=16#F0#) THEN next_state <= RESET; ELSE next_state <= AS_CFI; END IF; END IF; WHEN A0SEEN => IF falling_edge(write) THEN next_state <= PGMS; ELSE next_state <= A0SEEN; END IF; WHEN OTP => IF falling_edge(write) THEN IF PATTERN_1 THEN next_state <= OTP_Z001; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= OTP_PREL; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_PREL => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#90#))THEN next_state <= OTP_AS; ELSIF DataLo = 16#25# THEN --fix Sector Address SA next_state <= WBPGMS_WBCNT; ELSIF (A_PAT_1 AND (DataLo = 16#A0#))THEN next_state <= OTP_A0SEEN; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_AS => IF falling_edge(write) THEN IF (DataLo=16#00#) THEN IF PSP_ACT = '1' THEN next_state <= PSP; ELSIF ESP_ACT = '1' THEN next_state <= ESP; ELSE next_state <= RESET; END IF; ELSIF (Addr=16#55#) AND (DataLo=16#98#) THEN next_state <= OTP_AS_CFI; ELSIF DataLo=16#F0# THEN next_state <= OTP; ELSE next_state <= OTP_AS; END IF; END IF; WHEN OTP_AS_CFI => IF falling_edge(write) THEN IF (DataLo=16#F0#) THEN next_state <= OTP; ELSE next_state <= OTP_AS_CFI; END IF; END IF; WHEN OTP_A0SEEN => IF falling_edge(write) THEN IF (SecAddr = 0 AND (Address >= 0 AND Address <= 16#FF#)) THEN next_state <= PGMS; --set OTP ELSE next_state <= OTP; END IF; END IF; WHEN C8 => IF falling_edge(write) THEN IF PATTERN_1 THEN next_state <= C8_Z001; ELSE next_state <= RESET; END IF; END IF; WHEN C8_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= C8_PREL; ELSE next_state <= RESET; END IF; END IF; WHEN C8_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo=16#10# THEN next_state <= ERS; ELSIF DataLo=16#30# THEN next_state <= SERS; ELSE next_state <= RESET; END IF; END IF; WHEN ERS => IF rising_edge(EDONE) OR falling_edge(EERR) THEN next_state <= RESET; END IF; WHEN SERS => IF sCTMOUT = '1' THEN next_state <= SERS_EXEC; ELSIF falling_edge(write) THEN IF (DataLo = 16#B0#) THEN next_state <= ESP; -- ESP according to datasheet ELSIF (DataLo=16#30#) THEN next_state <= SERS; ELSE next_state <= RESET; END IF; END IF; WHEN ESPS => IF (sSTART_ET1 = '1') THEN next_state <= ESP; END IF; WHEN WBPGMS_WBCNT => IF falling_edge(write) THEN IF (SecAddr = SA)AND (DataLo < 16) THEN next_state <= WBPGMS_WBLSTA; ELSE next_state <= WBPGMS_WBABORT; END IF; END IF; WHEN WBPGMS_WBLSTA => IF falling_edge(write) THEN IF (SecAddr = SA) THEN -- fix WriteBufferPage WBPage IF (LCNT > 0) THEN next_state <= WBPGMS_WBLOAD; ELSE next_state <= WBPGMS_CONFB; END IF; ELSE next_state <= WBPGMS_WBABORT; END IF; END IF; WHEN WBPGMS_WBLOAD => IF falling_edge(write) THEN IF (WPage = WBPage) THEN IF (LCNT > 0) THEN next_state <= WBPGMS_WBLOAD; ELSE next_state <= WBPGMS_CONFB; END IF; ELSE next_state <= WBPGMS_WBABORT; END IF; END IF; WHEN WBPGMS_CONFB => IF falling_edge(write) THEN IF (SecAddr = SA) AND (DataLo = 16#29#) THEN next_state <= PGMS; ELSE next_state <= WBPGMS_WBABORT; END IF; END IF; WHEN WBPGMS_WBABORT => IF falling_edge(write) THEN IF PATTERN_1 THEN next_state <= WBPGMS_Z001; END IF; END IF; WHEN WBPGMS_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= WBPGMS_PREL; ELSE next_state <= WBPGMS_WBABORT; END IF; END IF; WHEN WBPGMS_PREL => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN IF ESP_ACT ='1' THEN next_state <= ESP; ELSIF OTP_ACT ='1' THEN next_state <= OTP; ELSE next_state <= RESET; END IF; ELSE next_state <= WBPGMS_WBABORT; END IF; END IF; WHEN SERS_EXEC => IF rising_edge(EDONE) OR falling_edge(EERR) THEN next_state <= RESET; ELSIF EERR /= '1' THEN IF falling_edge(write) THEN IF DataLo=16#B0# THEN next_state <= ESPS; END IF; END IF; END IF; WHEN ESP => IF falling_edge(write) THEN IF DataLo = 16#30# THEN next_state <= SERS_EXEC; ELSE IF Addr = 16#55# AND DataLo = 16#98# THEN next_state <= ESP_CFI; ELSIF PATTERN_1 THEN next_state <= ESP_Z001; END IF; END IF; END IF; WHEN ESP_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= ESP_PREL; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#20# THEN next_state <= PREL_ULBYPASS; --set ULBYPASS ELSIF DataLo = 16#25# THEN --fix SA next_state <= WBPGMS_WBCNT; --set ESP ELSIF A_PAT_1 AND DataLo = 16#A0# THEN next_state <= ESP_A0SEEN; ELSIF A_PAT_1 AND DataLo = 16#88# THEN next_state <= OTP; --set ESP ELSIF A_PAT_1 AND DataLo = 16#90# THEN next_state <= ESP_AS; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_CFI => IF falling_edge(write) THEN IF Addr = 16#55# AND DataLo = 16#98# THEN null; ELSIF DataLo = 16#F0# THEN next_state <= ESP; ELSE next_state <= ESP_CFI; END IF; END IF; WHEN ESP_A0SEEN => IF falling_edge(write) THEN next_state <= PGMS; --set ESP END IF; WHEN ESP_AS => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN -- resret ULBYPASS next_state <= ESP; ELSIF ((Addr=16#55#) AND (DataLo=16#98#)) THEN next_state <= ESP_AS_CFI; END IF; END IF; WHEN ESP_AS_CFI => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN next_state <= ESP; END IF; END IF; WHEN PGMS => IF rising_edge(PDONE) OR falling_edge(PERR) THEN IF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSIF OTP_ACT = '1' THEN next_state <= OTP; ELSIF ESP_ACT = '1' THEN next_state <= ESP; ELSE next_state <= RESET; END IF; ELSIF OTP_ACT = '1' THEN null; ELSIF falling_edge(write) AND PERR /= '1' THEN IF DataLo = 16#B0# THEN next_state <= PSPS; END IF; END IF; WHEN PSPS => IF sSTART_PT1 = '1' THEN next_state <= PSP; END IF; WHEN PSP => IF falling_edge(write) THEN IF DataLo = 16#30# THEN next_state <= PGMS; ELSIF Addr = 16#55# AND DataLo = 16#98# THEN next_state <= PSP_CFI; ELSIF PATTERN_1 THEN next_state <= PSP_Z001; END IF; END IF; WHEN PSP_CFI => IF falling_edge(write) THEN IF Addr = 16#55# AND DataLo = 16#98# THEN null; ELSIF DataLo =16#F0# THEN next_state <= PSP; END IF; END IF; WHEN PSP_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= PSP_PREL; END IF; END IF; WHEN PSP_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#90# THEN next_state <= PSP_AS; ELSIF A_PAT_1 AND DataLo =16#88# THEN next_state <= OTP; --set PSP ELSE next_state <= PSP; END IF; END IF; WHEN PSP_AS => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN -- resret ULBYPASS next_state <= PSP; ELSIF ((Addr=16#55#) AND (DataLo=16#98#)) THEN next_state <= PSP_AS_CFI; END IF; END IF; WHEN PSP_AS_CFI => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN next_state <= PSP; ELSE next_state <= PSP_AS_CFI; END IF; END IF; WHEN PLS_Z001 => IF falling_edge(write) THEN IF (A_PAT_2 AND (DataLo = 16#60#)) THEN next_state <= PLS_WAIT; ELSE next_state <= RESET; END IF; END IF; WHEN PLS_WAIT => IF sPLS = '1' THEN next_state <= PLS_VER1; END IF; WHEN PLS_VER1 => IF falling_edge(write) THEN IF (A_PAT_2 AND (DataLo = 16#40#)) THEN next_state <= RESET; ELSE next_state <= PLS_VER1; END IF; END IF; END CASE; END IF; END PROCESS StateGen; WP_CTRL: PROCESS(WPNeg) VARIABLE Sec_Prot_reg : std_logic_vector(SecNum downto 0) := (OTHERS => '0'); BEGIN --Hardware Write Protection IF falling_edge(WPNeg) THEN Sec_Prot_reg(SecNum downto 0) := Sec_Prot(SecNum downto 0); Sec_Prot(SecNum downto 0) := (OTHERS => '1'); ELSIF rising_edge(WPNeg) THEN Sec_Prot(SecNum downto 0) := Sec_Prot_reg(SecNum downto 0); END IF; END PROCESS WP_CTRL; --------------------------------------------------------------------------- --FSM Output generation and general funcionality --------------------------------------------------------------------------- Functional : PROCESS(write, read, Addr, D_tmp0, D_tmp1, Address, SecAddr, PDONE, EDONE, HANG, sSTART_ET1, sSTART_PT1, sCTMOUT, RST, reseted, sREADY, sPLS, gOE_n, current_state) --Flash Memory Array TYPE SecType IS ARRAY (0 TO SecSize) OF INTEGER RANGE -1 TO MaxData; TYPE MemArray IS ARRAY (0 TO SecNum) OF SecType; --Common Flash Interface Query codes TYPE CFItype IS ARRAY (16#10# TO 16#50#) OF NATURAL RANGE 0 TO 16#FF#; --SecSi Sector TYPE SecSiType IS ARRAY ( 0 TO SecSiSize) OF INTEGER RANGE -1 TO MaxData; --WriteBuffer TYPE WBDataType IS ARRAY ( 0 TO 15) OF INTEGER RANGE -1 TO MaxData; TYPE WBAddrType IS ARRAY ( 0 TO 15) OF INTEGER RANGE -1 TO 31; -- Mem(SecAddr)(Address).... VARIABLE Mem : MemArray := (OTHERS => (OTHERS => MaxData)); VARIABLE CFI_array : CFItype := (OTHERS => 0); VARIABLE SecSi : SecSiType := (OTHERS => 0); VARIABLE WBData : WBDataType:= (OTHERS => 0); VARIABLE WBAddr : WBAddrType:= (OTHERS => -1); VARIABLE BaseLoc : NATURAL RANGE 0 TO SecSize := 0; VARIABLE cnt : NATURAL RANGE 0 TO 31 := 0; VARIABLE PATTERN_1 : boolean := FALSE; VARIABLE PATTERN_2 : boolean := FALSE; VARIABLE A_PAT_1 : boolean := FALSE; VARIABLE A_PAT_2 : boolean := FALSE; VARIABLE oe : boolean := FALSE; --Status reg. VARIABLE Status : std_logic_vector(7 downto 0) := (OTHERS => '0'); -- text file input variables FILE mem_file : text is mem_file_name; FILE prot_file : text is prot_file_name; FILE secsi_file : text is secsi_file_name; VARIABLE S_ind : NATURAL RANGE 0 TO SecNum := 0; VARIABLE ind : NATURAL := 0; VARIABLE index : NATURAL RANGE 0 TO SecSize:=0; VARIABLE buf : line; VARIABLE old_bit : std_logic_vector(15 downto 0); VARIABLE new_bit : std_logic_vector(15 downto 0); VARIABLE old_int : INTEGER RANGE -1 to MaxData; VARIABLE new_int : INTEGER RANGE -1 to MaxData; VARIABLE wr_cnt : NATURAL RANGE 0 TO 31; --DATA Word VARIABLE DataW : NATURAL RANGE 0 TO MaxData := 0; --DATA Low Byte VARIABLE DataLo : NATURAL RANGE 0 TO 16#FF# := 0; VARIABLE temp : std_logic_vector(7 downto 0); VARIABLE SecSiAddr : NATURAL RANGE 0 TO SecSiSize := 0; VARIABLE k : NATURAL := 0; VARIABLE SGrA : NATURAL := 0; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(write) THEN DataLo := D_tmp0; DataW := D_tmp1; PATTERN_1 := (Addr=16#555#) AND (DataLo=16#AA#) ; PATTERN_2 := (Addr=16#2AA#) AND (DataLo=16#55#) ; A_PAT_1 := ((Addr=16#555#) AND (ULBYPASS='0')) OR (ULBYPASS='1'); A_PAT_2 := (Addr2(6)='0' AND Addr2(3)='0' AND Addr2(2)='0' AND Addr2(1)='1' AND Addr2(0)='0'); END IF; oe := rising_edge(read) OR (read = '1' AND Address'EVENT); IF reseted = '1' THEN CASE current_state IS WHEN RESET => OTP_ACT <= '0'; PSP_ACT <= '0'; ESP_ACT <= '0'; IF falling_edge(write) THEN IF ((Addr=16#55#) AND (DataLo=16#98#))THEN ULBYPASS <= '0'; ELSIF (A_PAT_2 AND (DataLo = 16#60#)) AND pls_flag2 = '1' THEN PLS_in <= '1'; SA <= SecAddr; pls_flag2 <= '0'; END IF; pls_flag2 <= '0'; ELSIF oe THEN IF (A_PAT_2 AND (SecAddr = SA) AND pls_flag = '1') THEN DOut_zd(15 downto 0) <= to_slv(16#0001#,16); ASSERT false REPORT "Protection verified." SEVERITY note; pls_flag <= '0'; ELSE DOut_zd(15 downto 0) <= READMEM(Mem(SecAddr)(Address)); ASSERT pls_flag = '0' REPORT "Protection of sector group wasn't verified." SEVERITY warning; pls_flag <= '0'; pls_flag2 <= '0'; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN Z001 => null; WHEN PREL_SETBWB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#20#)) THEN ULBYPASS <= '1'; ELSIF (A_PAT_1 AND (DataLo = 16#90#)) THEN ULBYPASS <= '0'; ELSIF (A_PAT_1 AND (DataLo = 16#88#)) THEN ULBYPASS <= '0'; OTP_ACT <= '1'; ELSIF (DataLo=16#25#) THEN --fix Sector Address SA SA <= SecAddr; END IF; END IF; WHEN PREL_ULBYPASS => IF falling_edge(write) THEN IF (A_PAT_1 AND DataLo=16#20#) THEN ULBYPASS <= '1'; ELSIF (A_PAT_1 AND (DataLo=16#90#)) THEN ULBYPASS <= '0'; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN PREL_ULBYPASS_RESET => IF falling_edge(write) AND (DataLo = 16#00# ) THEN ULBYPASS <= '0'; END IF; WHEN CFI | AS_CFI | OTP_AS_CFI => IF falling_edge(write) THEN IF (DataLo=16#F0#) THEN ULBYPASS <= '0'; END IF; ELSIF oe THEN DOut_zd(15 downto 0) <= (OTHERS => '0'); IF ((Addr>=16#10#) AND (Addr <= 16#50#)) THEN DOut_zd(7 downto 0) <= to_slv(CFI_array(Addr) ,8); ELSE ASSERT FALSE REPORT "Invalid CFI query address" SEVERITY warning; END IF; END IF; WHEN AS | ESP_AS | PSP_AS => IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN ULBYPASS <= '0'; END IF; ELSIF oe THEN IF Addr = 0 THEN DOut_zd(15 downto 0) <= to_slv(1,16); ELSIF Addr = 1 THEN DOut_zd(15 downto 0) <= to_slv(16#227E#,16); ELSIF Addr = 2 THEN DOut_zd(7 downto 1) <= to_slv(0,7); DOut_zd(0) <= Sec_Prot(SecAddr); ELSIF Addr = 3 THEN DOut_zd(7 downto 0) <= to_slv(9,8); IF FactoryProt = '1' THEN DOut_zd(7) <= '1'; END IF; ELSIF Addr = 16#E# THEN DOut_zd(15 downto 0) <= to_slv(16#223E#,16); ELSIF Addr = 16#F# THEN IF TimingModel(16) = '3' THEN DOut_zd(15 downto 0) <= to_slv(16#2201#,16); ELSE DOut_zd(15 downto 0) <= to_slv(16#2200#,16); END IF; END IF; END IF; WHEN A0SEEN => IF falling_edge(write) THEN PSTART <= '1', '0' AFTER 1 ns; PSUSP <= '0'; PRES <= '0'; PCNT <= 16; WBData(0) := -1; IF Viol = '0' THEN WBData(0) := DataW; END IF; WBAddr(0) := Address MOD 16; WBPage <= WPage; SA <= SecAddr; temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); END IF; WHEN OTP => OTP_ACT <= '1'; IF oe THEN --read SecSi Sector Region SecSiAddr := Address MOD (SecSiSize + 1); DOut_zd(15 downto 0) <= (OTHERS => 'X'); IF SecSi(SecSiAddr) /= -1 THEN DOut_zd(15 downto 0) <= to_slv(SecSi(SecSiAddr),16); END IF; END IF; --ready signal active RY_zd <= '1'; WHEN OTP_Z001 => null; WHEN OTP_PREL => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#90#))THEN ULBYPASS <= '0'; ELSIF DataLo = 16#25# THEN --fix Sector Address SA SA <= 0; ASSERT SecAddr=0 REPORT "Invalid sector address in SecSi mode" SEVERITY warning; --activate OTP OTP_ACT <= '1'; END IF; END IF; WHEN OTP_AS => IF falling_edge(write) THEN IF DataLo=16#00# THEN OTP_ACT <='0'; IF (PSP_ACT = '1' OR ESP_ACT = '1') THEN ULBYPASS <= '0'; END IF; ELSIF DataLo=16#F0# THEN OTP_ACT <='1'; END IF; ELSIF oe THEN IF Addr = 0 THEN DOut_zd(15 downto 0) <= to_slv(1,16); ELSIF Addr = 1 THEN DOut_zd(15 downto 0) <= to_slv(16#227E#,16); ELSIF Addr = 2 THEN DOut_zd(7 downto 1) <= to_slv(0,7); DOut_zd(0) <= Sec_Prot(SecAddr); ELSIF Addr = 3 THEN DOut_zd(7 downto 0) <= to_slv(9,8); IF FactoryProt = '1' THEN DOut_zd(7) <= '1'; END IF; ELSIF Addr = 16#E# THEN DOut_zd(15 downto 0) <= to_slv(16#223E#,16); ELSIF Addr = 16#F# THEN IF TimingModel(16) = '3' THEN DOut_zd(15 downto 0) <= to_slv(16#2201#,16); ELSE DOut_zd(15 downto 0) <= to_slv(16#2200#,16); END IF; END IF; END IF; WHEN OTP_A0SEEN => IF falling_edge(write) THEN OTP_ACT <= '1'; ----------------------------------------------------------- --SecSi programming: TBD ----------------------------------------------------------- PSTART <= '1', '0' AFTER 1 ns; PSUSP <= '0'; PRES <= '0'; PCNT <= 16; WBData(0) := -1; IF Viol = '0' THEN WBData(0) := DataW; END IF; WBAddr(0) := Address MOD 16; WBPage <= WPage MOD 8; SA <= 0; ASSERT SecAddr =0 REPORT "Invalid sector Address in SecSi" SEVERITY warning; ASSERT Address < 128 REPORT "Invalid program address in SecSi region. "& "Adress= "& to_int_str(Address) SEVERITY warning; temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); END IF; WHEN C8 => null; WHEN C8_Z001 => null; WHEN C8_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#10# THEN --Start Chip Erase ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; Ers_Queue <= (OTHERS => '1'); Status := "00001000"; ELSIF DataLo=16#30# THEN --put selected sector to sec. ers. queue --start timeout Ers_Queue <= (OTHERS => '0'); Ers_Queue(SecAddr) <= '1'; CTMOUT_in <= '0', '1' AFTER 1 ns; END IF; END IF; WHEN ERS => IF oe THEN ----------------------------------------------------------- -- read status / embeded erase algorithm - Chip Erase ----------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; END IF; IF EERR /= '1' THEN FOR i IN 0 TO SecNum LOOP IF Sec_Prot(i) /= '1' THEN Mem(i) := (OTHERS => -1); END IF; END LOOP; IF EDONE = '1' THEN FOR i IN 0 TO SecNum LOOP IF Sec_Prot(i) /= '1' THEN Mem(i) := (OTHERS => MaxData); END IF; END LOOP; END IF; END IF; -- busy signal active RY_zd <= '0'; WHEN SERS => IF sCTMOUT = '1' THEN CTMOUT_in <= '0'; START_ET1_in <= '0'; ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; IF oe THEN --read status END IF; ELSIF falling_edge(write) THEN IF (DataLo = 16#B0#) THEN --need to start erase process prior to suspend ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; --suspend timeout (should be 0 according to datasheet) ESUSP <= '1' AFTER 2 ns, '0' AFTER 3 ns; ELSIF (DataLo=16#30#) THEN CTMOUT_in <= '0', '1' AFTER 1 ns; Ers_Queue(SecAddr) <= '1'; END IF; ELSIF oe THEN ----------------------------------------------------------- --read status - sector erase timeout ----------------------------------------------------------- Status(3) := '0'; DOut_zd(7 downto 0) <= Status; END IF; --ready signal active RY_zd <= '0'; WHEN ESPS => ESUSP <= '1'; IF (sSTART_ET1 = '1') THEN ESP_ACT <= '1'; START_ET1_in <= '0'; ELSIF oe THEN ----------------------------------------------------------- --read status / erase suspend timeout - stil erasing ----------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; IF Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); --toggle END IF; DOut_zd(7 downto 0) <= Status; END IF; --busy signal active RY_zd <= '0'; WHEN WBPGMS_WBCNT => IF falling_edge(write) THEN IF (SecAddr = SA)AND (DataLo < 16) THEN cnt := DataLo; PCNT <= cnt; LCNT <= cnt; END IF; END IF; WHEN WBPGMS_WBLSTA => IF falling_edge(write) THEN IF (SecAddr = SA) THEN -- fix WriteBufferPage WBPage WBData(cnt) := -1; IF Viol = '0' THEN WBData(cnt) := DataW; END IF; WBAddr(cnt) := Address MOD 16; IF cnt > 0 THEN cnt := cnt -1; END IF; --save last loaded data for data polling temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); IF OTP_ACT = '1' THEN WBPage <= WPage MOD 8; ELSE WBPage <= WPage; END IF; IF OTP_ACT = '1' THEN --if SecSi entered, there are ASSERT WPage<8 --128 words at most to be written REPORT "Invalid Write Buffer Page selected "& " in SecSi" SEVERITY warning; END IF; END IF; LCNT <= cnt; END IF; WHEN WBPGMS_WBLOAD => IF falling_edge(write) THEN IF (WPage = WBPage)THEN WBData(cnt) := -1; IF Viol = '0' THEN WBData(cnt) := DataW; END IF; WBAddr(cnt) := Address MOD 16; IF cnt > 0 THEN cnt := cnt - 1; END IF; --save last loaded data for data polling temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); END IF; LCNT <= cnt; END IF; WHEN WBPGMS_CONFB => IF falling_edge(write) THEN IF (SecAddr = SA) AND (DataLo = 16#29#) THEN PSTART <= '1', '0' AFTER 1 ns; PSUSP <= '0'; PRES <= '0'; END IF; END IF; WHEN WBPGMS_WBABORT => IF oe THEN --------------------------------------------------------------- --read status / write buffer abort --------------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(1) := '1'; DOut_zd(7 downto 0) <= Status; END IF; --busy signal active RY_zd <= '0'; WHEN WBPGMS_Z001 => null; WHEN WBPGMS_PREL => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN PSP_ACT <= '0'; END IF; END IF; WHEN SERS_EXEC => IF oe THEN ----------------------------------------------------------- --read status Erase Busy ----------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; IF Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); --toggle END IF; DOut_zd(7 downto 0) <= Status; END IF; IF EERR /= '1' THEN FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN Mem(i) := (OTHERS => -1); END IF; END LOOP; IF EDONE = '1' THEN FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN Mem(i) := (OTHERS => MaxData); END IF; END LOOP; ELSIF falling_edge(write) THEN IF DataLo=16#B0# THEN START_ET1_in <= '1'; END IF; END IF; END IF; --busy signal active RY_zd <= '0'; WHEN ESP => ESUSP <= '0'; IF falling_edge(write) THEN IF DataLo = 16#30# THEN --resume erase ERES <= '1', '0' AFTER 1 ns; END IF; ELSIF oe THEN ----------------------------------------------------------- --read ----------------------------------------------------------- IF Ers_Queue(SecAddr) /= '1' THEN DOut_zd(15 downto 0) <= READMEM(Mem(SecAddr)(Address)); ELSE ------------------------------------------------------- --read status ------------------------------------------------------- Status(7) := '1'; -- Status(6) No toggle Status(5) := '0'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN ESP_Z001 => null; WHEN ESP_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#20# THEN ULBYPASS <= '1'; ELSIF DataLo = 16#25# THEN --fix SA SA <= SecAddr; ESP_ACT <= '1'; ELSIF A_PAT_1 AND DataLo = 16#88# THEN ESP_ACT <= '1'; END IF; END IF; WHEN ESP_CFI | ESP_AS_CFI => IF falling_edge(write) THEN IF Addr = 16#55# AND DataLo = 16#98# THEN null; ELSIF DataLo = 16#F0# THEN ESP_ACT <= '1'; ELSE ESP_ACT <= '1'; END IF; ELSIF oe THEN DOut_zd(15 downto 0) <= (OTHERS => '0'); IF ((Addr >= 16#10#) AND (Addr<=16#50#)) THEN DOut_zd(7 downto 0) <= to_slv(CFI_array(Addr) ,8); ELSE ASSERT FALSE REPORT "Invalid CFI query address" SEVERITY warning; END IF; END IF; WHEN ESP_A0SEEN => IF falling_edge(write) THEN ESP_ACT <= '1'; PSTART <= '1', '0' AFTER 1 ns; PRES <= '0'; PSUSP <= '0'; PCNT <= 16; WBData(0) := -1; IF Viol = '0' THEN WBData(0) := DataW; END IF; WBAddr(0) := Address MOD 16; WBPage <= WPage; SA <= SecAddr; temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); END IF; WHEN PGMS => IF oe THEN ----------------------------------------------------------- --read status ----------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; DOut_zd(7 downto 0) <= Status; END IF; IF PERR /= '1' THEN BaseLoc := WBPage * 16; IF PCNT < 16 THEN --buffer wr_cnt := PCNT; ELSE --Word/Byte program wr_cnt := 0; END IF; FOR i IN wr_cnt downto 0 LOOP new_int := WBData(i); IF WBAddr(i) < 0 THEN old_int := -1; ELSIF OTP_ACT /= '1' THEN --mem write old_int := Mem(SA)(BaseLoc+WBAddr(i)); ELSE old_int := SecSi(BaseLoc+WBAddr(i)); END IF; IF new_int > -1 THEN new_bit := to_slv(new_int,16); IF old_int > -1 THEN old_bit := to_slv(old_int,16); FOR j IN 0 TO 15 LOOP IF old_bit(j) = '0' THEN new_bit(j) := '0'; END IF; END LOOP; new_int := to_nat(new_bit); END IF; WBData(i) := new_int; ELSE WBData(i) := -1; END IF; END LOOP; FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) < 0 THEN REPORT "write buffer violation" SEVERITY warning; ELSIF OTP_ACT /= '1' THEN --mem write Mem(SA)(BaseLoc + WBAddr(i)) := -1; ELSE SecSi(BaseLoc + WBAddr(i)) := -1; END IF; END LOOP; IF HANG /= '1' AND PDONE = '1' AND (NOT PERR'EVENT) THEN FOR i IN wr_cnt downto 0 LOOP IF WBAddr(i) > -1 THEN IF OTP_ACT /= '1' THEN --mem write Mem(SA)(BaseLoc + WBAddr(i)) := WBData(i); ELSE --SecSi write SecSi(BaseLoc+WBAddr(i)) := WBData(i); END IF; ELSE ASSERT false REPORT "WriteBuffer Address error" SEVERITY warning; END IF; WBData(i) := -1; END LOOP; ELSIF falling_edge(write) THEN IF DataLo = 16#B0# THEN START_PT1_in <= '1'; END IF; END IF; END IF; --busy signal active RY_zd <= '0'; WHEN PSPS => PSUSP <= '1'; IF sSTART_PT1 = '1' THEN START_PT1_in <= '0'; ELSIF oe THEN ----------------------------------------------------------- --read status / stil programming ----------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; DOut_zd(7 downto 0) <= Status; END IF; --busy signal active RY_zd <= '0'; WHEN PSP => PSUSP <= '0'; IF falling_edge(write) THEN IF DataLo = 16#30# THEN PRES <= '1', '0' AFTER 1 ns; END IF; ELSIF oe THEN ----------------------------------------------------------- --read - program suspend ----------------------------------------------------------- IF SecAddr = SA THEN --read program suspended sector --Invalid (not allowed) ASSERT false REPORT "Read from program suspended sector " & "is NOT allowed" SEVERITY warning; ELSIF ESP_ACT = '1' AND Ers_Queue(SecAddr) = '1' THEN Status(7) := '1'; Status(5) := '0'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; ELSE --read sector other than program suspended one DOut_zd(15 downto 0) <= READMEM(Mem(SecAddr)(Address)); END IF; END IF; --ready signal active RY_zd <= '1'; WHEN PSP_CFI | PSP_AS_CFI => IF oe THEN DOut_zd(15 downto 0) <= (OTHERS => '0'); IF ((Addr >= 16#10#) AND (Addr <= 16#50#)) THEN DOut_zd(7 downto 0) <= to_slv(CFI_array(Addr),8); ELSE ASSERT FALSE REPORT "Invalid CFI query address" SEVERITY warning; END IF; END IF; WHEN PSP_Z001 => null; WHEN PSP_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo =16#88# THEN PSP_ACT <= '1'; END IF; END IF; WHEN PLS_Z001 => IF falling_edge(write) THEN IF (A_PAT_2 AND DataLo =16#60#) THEN PLS_in <= '1'; SA <= SecAddr; END IF; END IF; WHEN PLS_WAIT => pls_flag <= '0'; pls_flag2 <= '0'; IF sPLS = '1' THEN IF SA <= 3 THEN Sec_Prot(SA) := '1'; ELSIF ((SA >= 4) AND (SA <= 123))THEN SGrA := NATURAL(SA /4); Sec_Prot((4*SGrA+3) DOWNTO (4*SGrA)) := "1111"; ELSIF (SA >= 124) AND (SA <= 127) THEN Sec_Prot(SA) := '1'; END IF; ASSERT false REPORT "Seted group of sectors protected!" SEVERITY note; END IF; WHEN PLS_VER1 => IF sPLS = '1' THEN PLS_in <= '0'; pls_flag <= '1'; pls_flag2 <= '1'; ASSERT false REPORT "Expecting read for protection verifing." SEVERITY note; END IF; END CASE; END IF; --Output Disable Control IF (gOE_n = '1') OR (RESETNeg = '0'AND RST = '0') THEN DOut_zd <= (OTHERS => 'Z'); END IF; --Preload Control ------------------------------------------------------------------------------- -- File Read Section ------------------------------------------------------------------------------- IF NOW = 0 ns THEN IF (prot_file_name /= "none" AND UserPreload ) THEN ------------------------------------------------------------------- -----s29gl064_s3_s4 sector protect preload file format ------------ ------------------------------------------------------------------- -- / - comment -- @ss - stands for sector number -- d - is bit to be written at SecProt(ss++) -- (sec is incremented at every load) -- only first 1-4 columns are loaded. NO empty lines !!!!!!!!!!!! ------------------------------------------------------------------- ------------------------------------------------------------------- ind := 0; Sec_Prot := (OTHERS => '0'); WHILE (not ENDFILE (prot_file)) LOOP -- Always load as top, convert if bottom READLINE (prot_file, buf); IF buf(1)='/' THEN --comment NEXT; ELSIF buf(1) = '@' THEN --address ind := h(buf(2 to 3)); ELSE IF (buf(1) = '1') AND (ind <= SecNum) THEN Sec_Prot(ind) := '1'; ELSIF (( ind > SecNum ) AND ( buf(1) = '1' )) THEN FactoryProt <= '1'; END IF; ind := ind + 1; END IF; END LOOP; FOR i IN 1 TO 30 LOOP IF Sec_Prot(4*i+3 DOWNTO 4*i) /= "0000" AND Sec_Prot(4*i+3 DOWNTO 4*i) /= "1111" THEN -- every 4-group sectors protect bit must equal REPORT "Bad preload " & to_int_str(i) & "th sector protect group" SEVERITY warning; END IF; END LOOP; END IF; ------------------------------------------------------------------------------- -----s29gl064a_s3_s4 SecSi preload file format------ -------------------------- ------------------------------------------------------------------------------- -- / - comment -- @aa - stands for address within sector -- dd -
is word to be written at SecSi(aa++) -- (aa is incremented at every load) -- only first 1-4 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- IF (SecSi_file_name /= "none" AND UserPreload ) THEN SecSi := (OTHERS => MaxData); ind := 0; WHILE (not ENDFILE (SecSi_file)) LOOP READLINE (SecSi_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 3)); --address ELSE IF ind <= SecSiSize THEN SecSi(ind) := h(buf(1 TO 4)); ind := ind + 1; ELSE REPORT " SecSi address out of range" SEVERITY warning; END IF; END IF; END LOOP; END IF; ------------------------------------------------------------------------------- -----s29gl064a_s3_s4 memory preload file format ------------------------------- ------------------------------------------------------------------------------- -- / - comment -- @aaaaaa - stands for address within sector -- dd -
is word to be written at Mem(*)(aaaaaa++) -- (aaaaaa is incremented at every load) -- only first 1-7 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- IF (mem_file_name /= "none" ) THEN ind := 0; S_ind := 0; Mem := (OTHERS => (OTHERS => MaxData)); -- load sector 0 WHILE (not ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 7)); --address ELSE IF ind=0 THEN S_ind := 0; index := 0; Mem(S_ind)(index) := h(buf(1 to 4)); ind := ind + 1; ELSIF ind < SecSize+1 THEN S_ind := 0; index := ind; Mem(S_ind)(index) := h(buf(1 to 4)); ind := ind + 1; ELSIF ind <= AddrRANGE THEN S_ind := NATURAL(ind / (SecSize +1)); index := ind - S_ind*(SecSize+1); Mem(S_ind)(index) := h(buf(1 to 4)); ind := ind + 1; ELSE REPORT " Memory address out of range" SEVERITY warning; END IF; END IF; END LOOP; END IF; ----------------------------------------------------------------------- --CFI array data ----------------------------------------------------------------------- --CFI query identification string CFI_array(16#10#) := 16#51#; CFI_array(16#11#) := 16#52#; CFI_array(16#12#) := 16#59#; CFI_array(16#13#) := 16#02#; CFI_array(16#14#) := 16#00#; CFI_array(16#15#) := 16#40#; CFI_array(16#16#) := 16#00#; CFI_array(16#17#) := 16#00#; CFI_array(16#18#) := 16#00#; CFI_array(16#19#) := 16#00#; CFI_array(16#1A#) := 16#00#; --system interface string CFI_array(16#1B#) := 16#27#; CFI_array(16#1C#) := 16#36#; CFI_array(16#1D#) := 16#00#; CFI_array(16#1E#) := 16#00#; CFI_array(16#1F#) := 16#07#; CFI_array(16#20#) := 16#07#; CFI_array(16#21#) := 16#0A#; CFI_array(16#22#) := 16#00#; CFI_array(16#23#) := 16#01#; CFI_array(16#24#) := 16#05#; CFI_array(16#25#) := 16#04#; CFI_array(16#26#) := 16#00#; --device geometry definition CFI_array(16#27#) := 16#17#; CFI_array(16#28#) := 16#02#; CFI_array(16#29#) := 16#00#; CFI_array(16#2A#) := 16#05#; CFI_array(16#2B#) := 16#00#; CFI_array(16#2C#) := 16#01#; CFI_array(16#2D#) := 16#7F#; CFI_array(16#2E#) := 16#00#; CFI_array(16#2F#) := 16#20#; CFI_array(16#30#) := 16#00#; CFI_array(16#31#) := 16#7E#; CFI_array(16#32#) := 16#00#; CFI_array(16#33#) := 16#00#; CFI_array(16#34#) := 16#01#; CFI_array(16#35#) := 16#00#; CFI_array(16#36#) := 16#00#; CFI_array(16#37#) := 16#00#; CFI_array(16#38#) := 16#00#; CFI_array(16#39#) := 16#00#; CFI_array(16#3A#) := 16#00#; CFI_array(16#3B#) := 16#00#; CFI_array(16#3C#) := 16#00#; --primary vendor-specific extended query CFI_array(16#40#) := 16#50#; CFI_array(16#41#) := 16#52#; CFI_array(16#42#) := 16#49#; CFI_array(16#43#) := 16#31#; CFI_array(16#44#) := 16#33#; CFI_array(16#45#) := 16#08#; CFI_array(16#46#) := 16#02#; CFI_array(16#47#) := 16#01#; CFI_array(16#48#) := 16#00#; CFI_array(16#49#) := 16#04#; CFI_array(16#4A#) := 16#00#; CFI_array(16#4B#) := 16#00#; CFI_array(16#4C#) := 16#01#; CFI_array(16#4D#) := 16#B5#; CFI_array(16#4E#) := 16#C5#; CFI_array(16#50#) := 16#01#; END IF; END PROCESS Functional; Start_PT1_time : PROCESS (START_PT1_in) BEGIN IF rising_edge ( START_PT1_in ) THEN IF LongTimming = TRUE THEN sSTART_PT1 <= '0', '1' AFTER tdevice_START_PT1; ELSE sSTART_PT1 <= '0', '1' AFTER tdevice_START_PT1/1; END IF; ELSE sSTART_PT1 <= '0'; END IF; END PROCESS Start_PT1_time; Start_ET1_time : PROCESS (START_ET1_in) BEGIN IF rising_edge ( START_ET1_in ) THEN IF LongTimming = TRUE THEN sSTART_ET1 <= '0', '1' AFTER tdevice_START_ET1; ELSE sSTART_ET1 <= '0', '1' AFTER tdevice_START_ET1/1; END IF; ELSE sSTART_ET1 <= '0'; END IF; END PROCESS Start_ET1_time; CTMOUT_time : PROCESS (CTMOUT_in) BEGIN IF rising_edge ( CTMOUT_in ) THEN IF LongTimming = TRUE THEN sCTMOUT <= '0', '1' AFTER (tdevice_CTMOUT - 1 ns); ELSE sCTMOUT <= '0', '1' AFTER (tdevice_CTMOUT - 1 ns)/5; END IF; ELSE sCTMOUT <= '0'; END IF; END PROCESS CTMOUT_time; READY_time : PROCESS (READY_in) BEGIN IF rising_edge ( READY_in ) THEN IF LongTimming = TRUE THEN sREADY <= '0', '1' AFTER (tdevice_READY - 1 ns); ELSE sREADY <= '0', '1' AFTER (tdevice_READY - 1 ns)/10; END IF; ELSE sREADY <= '0'; END IF; END PROCESS READY_time; PLS_time : PROCESS (PLS_in) BEGIN IF rising_edge ( PLS_in ) THEN IF LongTimming = TRUE THEN sPLS <= '0', '1' AFTER (tdevice_PLS - 1 ns); ELSE sPLS <= '0', '1' AFTER (tdevice_PLS - 1 ns)/10; END IF; ELSE sPLS <= '0'; END IF; END PROCESS PLS_time; DOutPassThrough : PROCESS(DOut_zd) VARIABLE ValidData : std_logic_vector(15 downto 0); VARIABLE CEDQ_t : TIME; VARIABLE OEDQ_t : TIME; VARIABLE ADDRDQ_t : TIME; BEGIN IF DOut_zd(0) /= 'Z' THEN OPENLATCH := TRUE; CEDQ_t := -CENeg'LAST_EVENT + tpd_CENeg_DQ0(trz0); OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_DQ0(trz0); ADDRDQ_t := -A'LAST_EVENT + tpd_A0_DQ0(tr01); FROMOE := (OEDQ_t >= CEDQ_t) AND (OEDQ_t > 0 ns); FROMCE := (CEDQ_t > OEDQ_t) AND (CEDQ_t > 0 ns); ValidData := "XXXXXXXXXXXXXXXX"; IF ((ADDRDQ_t > 0 ns) AND (((ADDRDQ_t > CEDQ_t) AND FROMCE) OR ((ADDRDQ_t > OEDQ_t) AND FROMOE))) THEN DOut_Pass <= ValidData, DOut_zd AFTER ADDRDQ_t; ELSE DOut_Pass <= DOut_zd; END IF; ELSE OPENLATCH := FALSE; DOut_Pass <= DOut_zd; END IF; END PROCESS DOutPassThrough; ----------------------------------------------------------------------- -- Path Delay Section ----------------------------------------------------------------------- RY_OUT: PROCESS(RY_zd) VARIABLE RY_tmp : std_logic; VARIABLE RY_GlitchData : VitalGlitchDataType; BEGIN IF RY_zd = '1' THEN RY_tmp := 'Z'; ELSE RY_tmp := RY_zd; END IF; VitalPathDelay01( OutSignal => RY, OutSignalName => "RY/BY#", OutTemp => RY_tmp, Mode => VitalTransport, GlitchData => RY_GlitchData, Paths => ( 0 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_RY, PathCondition => TRUE), 1 => (InputChangeTime => WENeg'LAST_EVENT, PathDelay => tpd_WENeg_RY, PathCondition => TRUE), 2 => (InputChangeTime => sREADY'LAST_EVENT, PathDelay => VitalZeroDelay01, PathCondition => EDONE = '1'), 3 => (InputChangeTime => EDONE'LAST_EVENT, PathDelay => VitalZeroDelay01, PathCondition => EDONE = '1'), 4 => (InputChangeTime => PDONE'LAST_EVENT, PathDelay => VitalZeroDelay01, PathCondition => PDONE = '1') ) ); END PROCESS RY_Out; --------------------------------------------------------------------------- -- Path Delay Section for DOut signal --------------------------------------------------------------------------- D_Out_PathDelay_Gen : FOR i IN DOut_Pass'RANGE GENERATE PROCESS(DOut_Pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_Pass(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_DQ0, PathCondition => NOT OPENLATCH OR (OPENLATCH AND FROMCE)), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ0, PathCondition => NOT OPENLATCH OR (OPENLATCH AND FROMOE)), 2 => (InputChangeTime => RESETNeg'LAST_EVENT, PathDelay => tpd_RESETNeg_DQ0, PathCondition => RESETNeg='0'), 3 => (InputChangeTime => A'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => DOut_pass(i) /= 'X' AND RPchange), 4 => (InputChangeTime => A'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ1), PathCondition => DOut_pass(i) /= 'X' AND (NOT RPchange)) ) ); END PROCESS; END GENERATE D_Out_PathDelay_Gen; END BLOCK behavior; END vhdl_behavioral;