-------------------------------------------------------------------------------- -- File Name: am41dl3244g.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2004 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 M.Radmanovic 04 Jan 28 Inital Release -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: AMD -- Technology: Flash Memory -- Part: AM41DL3244G -- -- Description: Stacked Multi-Chip Package Flash Memory and SRAM -- 32 Megabit(4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, -- Simultaneous Operation Flash Memory and 4 Mbit -- (512 K x 8-Bit/256 K x 16-Bit) Pseudo Static RAM -- -------------------------------------------------------------------------------- -- Known Bugs: -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY AM41DL3244G IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; --address tipd_A10 : VitalDelayType01 := VitalZeroDelay01; --lines tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A18 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A19 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A20 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- DQ15/A-1 tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; --WP#/ACC tipd_CIOFNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CIOSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SA : VitalDelayType01 := VitalZeroDelay01; tipd_UBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE2 : VitalDelayType01 := VitalZeroDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING := "none";--"am41dl3244g.mem"; sram_file_name : STRING := "none";--"am41dl3244g_sram.mem"; prot_file_name : STRING := "none";--"am41dl3244g_prot.mem"; secsi_file_name : STRING := "none";--"am41dl3244g_secsi.mem"; UserPreload : BOOLEAN := FALSE; --TRUE; LongTimming : BOOLEAN := TRUE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A20 : IN std_ulogic := 'U'; -- A19 : IN std_ulogic := 'U'; -- A18 : IN std_ulogic := 'U'; -- A17 : IN std_ulogic := 'U'; -- A16 : IN std_ulogic := 'U'; -- A15 : IN std_ulogic := 'U'; -- A14 : IN std_ulogic := 'U'; -- A13 : IN std_ulogic := 'U'; --address A12 : IN std_ulogic := 'U'; --lines A11 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A8 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- A6 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A1 : IN std_ulogic := 'U'; -- A0 : IN std_ulogic := 'U'; -- DQ15 : INOUT std_logic := 'U'; -- DQ15/A-1 DQ14 : INOUT std_logic := 'U'; -- DQ13 : INOUT std_logic := 'U'; -- DQ12 : INOUT std_logic := 'U'; -- DQ11 : INOUT std_logic := 'U'; -- DQ10 : INOUT std_logic := 'U'; -- DQ9 : INOUT std_logic := 'U'; -- data DQ8 : INOUT std_logic := 'U'; -- lines DQ7 : INOUT std_logic := 'U'; -- DQ6 : INOUT std_logic := 'U'; -- DQ5 : INOUT std_logic := 'U'; -- DQ4 : INOUT std_logic := 'U'; -- DQ3 : INOUT std_logic := 'U'; -- DQ2 : INOUT std_logic := 'U'; -- DQ1 : INOUT std_logic := 'U'; -- DQ0 : INOUT std_logic := 'U'; -- CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; --WP#/ACC CIOFNeg : IN std_ulogic := 'U'; CIOSNeg : IN std_ulogic := 'U'; SA : IN std_ulogic := 'U'; LBNeg : IN std_ulogic := 'U'; UBNeg : IN std_ulogic := 'U'; CE1Neg : IN std_ulogic := 'U'; CE2 : IN std_ulogic := 'U'; RY : OUT std_ulogic := 'U' --RY/BY# ); ATTRIBUTE VITAL_LEVEL0 of AM41DL3244G : ENTITY IS TRUE; END AM41DL3244G; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY Flash32M IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; --address tipd_A10 : VitalDelayType01 := VitalZeroDelay01; --lines tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A18 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A19 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A20 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- DQ15/A-1 tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; --WP#/ACC tipd_CIOFNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_RESETNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; tpd_A0_DQ0 : VitalDelayType01 := UnitDelay01;--tACC tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tCE,tCE,tDF,-,tDF,-) tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tOE,tOE,tDF,-,tDF,-) tpd_CIOFNeg_DQ15 : VitalDelayType01Z := UnitDelay01Z; tpd_WENeg_RY : VitalDelayType01Z := UnitDelay01Z; --tBUSY --tsetup values tsetup_A0_CENeg : VitalDelayType := UnitDelay; --tAS edge \ tsetup_A0_OENeg : VitalDelayType := UnitDelay; --tASO edge \ tsetup_DQ0_CENeg : VitalDelayType := UnitDelay; --tDS edge / --thold values thold_CENeg_RESETNeg: VitalDelayType := UnitDelay; --tRH edge / thold_OENeg_WENeg : VitalDelayType := UnitDelay; --tOEH edge / thold_A0_CENeg : VitalDelayType := UnitDelay; --tAH edge \ thold_A0_OENeg : VitalDelayType := UnitDelay; --tAHT edge \ thold_DQ0_CENeg : VitalDelayType := UnitDelay; --tDH edge / thold_WENeg_OENeg : VitalDelayType := UnitDelay; --tGHWL edge / thold_CIOFNeg_CENeg : VitalDelayType := UnitDelay; --tELFL edge \ --tpw values: pulse width tpw_RESETNeg_negedge : VitalDelayType := UnitDelay; --tRP tpw_OENeg_posedge : VitalDelayType := UnitDelay; --tOEPH tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP tpw_WENeg_posedge : VitalDelayType := UnitDelay; --tWPH tpw_CENeg_negedge : VitalDelayType := UnitDelay; --tCP tpw_CENeg_posedge : VitalDelayType := UnitDelay; --tCEPH tpw_A0_negedge : VitalDelayType := UnitDelay; --tWC tRC -- tdevice values: values for internal delays --Program Operation tdevice_POB : VitalDelayType := 5 us; --Sector Erase Operation tWHWH2 tdevice_SEO : VitalDelayType := 400 ms; --Timing Limit Exceeded tdevice_HANG : VitalDelayType := 400 ms; --? --program/erase suspend timeout tdevice_START : VitalDelayType := 5 us; --sector erase command sequence timeout tdevice_TCTMOUT : VitalDelayType := 50 us; --device ready after Hardware reset(during embeded algorithm) tdevice_TREADY : VitalDelayType := 20 us; --tReady -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING := "none";--"am41dl3244g.mem"; prot_file_name : STRING := "none";--"am41dl3244g_prot.mem"; secsi_file_name : STRING := "none";--"am41dl3244g_secsi.mem"; UserPreload : BOOLEAN := FALSE; --TRUE; LongTimming : BOOLEAN := TRUE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A20 : IN std_ulogic := 'U'; -- A19 : IN std_ulogic := 'U'; -- A18 : IN std_ulogic := 'U'; -- A17 : IN std_ulogic := 'U'; -- A16 : IN std_ulogic := 'U'; -- A15 : IN std_ulogic := 'U'; -- A14 : IN std_ulogic := 'U'; -- A13 : IN std_ulogic := 'U'; --address A12 : IN std_ulogic := 'U'; --lines A11 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A8 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- A6 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A1 : IN std_ulogic := 'U'; -- A0 : IN std_ulogic := 'U'; -- DQ15 : INOUT std_ulogic := 'U'; -- DQ15/A-1 DQ14 : INOUT std_ulogic := 'U'; -- DQ13 : INOUT std_ulogic := 'U'; -- DQ12 : INOUT std_ulogic := 'U'; -- DQ11 : INOUT std_ulogic := 'U'; -- DQ10 : INOUT std_ulogic := 'U'; -- DQ9 : INOUT std_ulogic := 'U'; -- data DQ8 : INOUT std_ulogic := 'U'; -- lines DQ7 : INOUT std_ulogic := 'U'; -- DQ6 : INOUT std_ulogic := 'U'; -- DQ5 : INOUT std_ulogic := 'U'; -- DQ4 : INOUT std_ulogic := 'U'; -- DQ3 : INOUT std_ulogic := 'U'; -- DQ2 : INOUT std_ulogic := 'U'; -- DQ1 : INOUT std_ulogic := 'U'; -- DQ0 : INOUT std_ulogic := 'U'; -- CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; --WP#/ACC CIOFNeg : IN std_ulogic := 'U'; RY : OUT std_ulogic := 'U' --RY/BY# ); ATTRIBUTE VITAL_LEVEL0 of Flash32M : ENTITY IS TRUE; END Flash32M; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of Flash32M IS ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT PartID : STRING := "Flash32M"; CONSTANT MaxData : NATURAL := 16#FF#; --255; CONSTANT SecSize : NATURAL := 16#FFFF#; --65535 CONSTANT SecSiSize : NATURAL := 255; CONSTANT SecNum : NATURAL := 70; CONSTANT HiAddrBit : NATURAL := 20; CONSTANT AddrRANGE : NATURAL := 16#3FFFFF#; -- interconnect path delay signals SIGNAL A20_ipd : std_ulogic := 'U'; SIGNAL A19_ipd : std_ulogic := 'U'; SIGNAL A18_ipd : std_ulogic := 'U'; SIGNAL A17_ipd : std_ulogic := 'U'; SIGNAL A16_ipd : std_ulogic := 'U'; SIGNAL A15_ipd : std_ulogic := 'U'; SIGNAL A14_ipd : std_ulogic := 'U'; SIGNAL A13_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL CENeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; SIGNAL WPNeg_ipd : std_ulogic := 'U'; SIGNAL CIOFNeg_ipd : std_ulogic := 'U'; --- internal delays SIGNAL WBPO_in : std_ulogic := '0'; SIGNAL WBPO_out : std_ulogic := '0'; SIGNAL PO_in : std_ulogic := '0'; SIGNAL PO_out : std_ulogic := '0'; SIGNAL SEO_in : std_ulogic := '0'; SIGNAL SEO_out : std_ulogic := '0'; SIGNAL HANG_out : std_ulogic := '0'; --Program/Erase Timing Limit SIGNAL HANG_in : std_ulogic := '0'; SIGNAL START_T1 : std_ulogic := '0'; --Start TimeOut SIGNAL START_T1_in : std_ulogic := '0'; SIGNAL CTMOUT : std_ulogic := '0'; --Sector Erase TimeOut SIGNAL CTMOUT_in : std_ulogic := '0'; SIGNAL READY_in : std_ulogic := '0'; SIGNAL READY : std_ulogic := '0'; -- Device ready after reset BEGIN --------------------------------------------------------------------------- -- Internal Delays --------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays POB :VitalBuf(PO_out, PO_in, (tdevice_POB ,UnitDelay)); SEO :VitalBuf(SEO_out, SEO_in, (tdevice_SEO ,UnitDelay)); HANG :VitalBuf(HANG_out,HANG_in, (tdevice_HANG ,UnitDelay)); START :VitalBuf(START_T1,START_T1_in,(tdevice_START ,UnitDelay)); TCTMOUT:VitalBuf(CTMOUT, CTMOUT_in, (tdevice_TCTMOUT - 1 ns ,UnitDelay)); TREADY :VitalBuf(READY, READY_in, (tdevice_TREADY ,UnitDelay)); --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_0 : VitalWireDelay (A20_ipd, A20, tipd_A20); w_1 : VitalWireDelay (A19_ipd, A19, tipd_A19); w_2 : VitalWireDelay (A18_ipd, A18, tipd_A18); w_3 : VitalWireDelay (A17_ipd, A17, tipd_A17); w_4 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_5 : VitalWireDelay (A15_ipd, A15, tipd_A15); w_6 : VitalWireDelay (A14_ipd, A14, tipd_A14); w_7 : VitalWireDelay (A13_ipd, A13, tipd_A13); w_8 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_9 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_10 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_11 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_12 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_13 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_14 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_15 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_16 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_17 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_18 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_19 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_20 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_21 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15); w_22 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14); w_23 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13); w_24 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12); w_25 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11); w_26 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10); w_27 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9); w_28 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8); w_29 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7); w_30 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6); w_31 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5); w_32 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4); w_33 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_34 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_35 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_36 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_37 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_38 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_39 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg); w_40 : VitalWireDelay (WPNeg_ipd, WPNeg, tipd_WPNeg); w_41 : VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg); w_42 : VitalWireDelay (CIOFNeg_ipd, CIOFNeg, tipd_CIOFNeg); END BLOCK; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior: BLOCK PORT ( A : IN std_logic_vector(HiAddrBit downto 0) := (OTHERS => 'U'); DIn : IN std_logic_vector(15 downto 0) := (OTHERS => 'U'); DOut : OUT std_ulogic_vector(15 downto 0) := (OTHERS => 'Z'); CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; CIOFNeg : IN std_ulogic := 'U'; RY : OUT std_ulogic := 'U' ); PORT MAP ( A(20) => A20_ipd, A(19) => A19_ipd, A(18) => A18_ipd, A(17) => A17_ipd, A(16) => A16_ipd, A(15) => A15_ipd, A(14) => A14_ipd, A(13) => A13_ipd, A(12) => A12_ipd, A(11) => A11_ipd, A(10) => A10_ipd, A(9) => A9_ipd, A(8) => A8_ipd, A(7) => A7_ipd, A(6) => A6_ipd, A(5) => A5_ipd, A(4) => A4_ipd, A(3) => A3_ipd, A(2) => A2_ipd, A(1) => A1_ipd, A(0) => A0_ipd, DIn(15) => DQ15_ipd, DIn(14) => DQ14_ipd, DIn(13) => DQ13_ipd, DIn(12) => DQ12_ipd, DIn(11) => DQ11_ipd, DIn(10) => DQ10_ipd, DIn(9) => DQ9_ipd, DIn(8) => DQ8_ipd, DIn(7) => DQ7_ipd, DIn(6) => DQ6_ipd, DIn(5) => DQ5_ipd, DIn(4) => DQ4_ipd, DIn(3) => DQ3_ipd, DIn(2) => DQ2_ipd, DIn(1) => DQ1_ipd, DIn(0) => DQ0_ipd, DOut(15) => DQ15, DOut(14) => DQ14, DOut(13) => DQ13, DOut(12) => DQ12, DOut(11) => DQ11, DOut(10) => DQ10, DOut(9) => DQ9, DOut(8) => DQ8, DOut(7) => DQ7, DOut(6) => DQ6, DOut(5) => DQ5, DOut(4) => DQ4, DOut(3) => DQ3, DOut(2) => DQ2, DOut(1) => DQ1, DOut(0) => DQ0, CENeg => CENeg_ipd, OENeg => OENeg_ipd, WENeg => WENeg_ipd, RESETNeg => RESETNeg_ipd, WPNeg => WPNeg_ipd, CIOFNeg => CIOFNeg_ipd, RY => RY ); -- State Machine : State_Type TYPE state_type IS ( RESET, Z001, PREL_SETBWB, PREL_ULBYPASS, RES_ULBYPASS, CFI, AS, A0SEEN, OTP, OTP_Z001, OTP_PREL, OTP_AS, OTP_A0SEEN, C8, C8_Z001, C8_PREL, ERS, SERS, ESPS, SERS_EXEC, ESP, ESP_Z001, ESP_PREL, ESP_CFI, ESP_A0SEEN, ESP_AS, PGMS ); --Flash Memory Array TYPE SecType IS ARRAY (0 TO SecSize) OF INTEGER RANGE -1 TO MaxData; TYPE MemArray IS ARRAY (0 TO SecNum) OF SecType; -- alias, four bank architecture TYPE Bank IS (ABank, BBank); -- states SIGNAL current_state : state_type; -- SIGNAL next_state : state_type; -- -- powerup SIGNAL PoweredUp : std_logic := '0'; --zero delay signals SIGNAL DOut_zd : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL DOut_Pass : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL RY_zd : std_logic := 'Z'; --FSM control signals SIGNAL ULBYPASS : std_logic := '0'; --Unlock Bypass Active SIGNAL ESP_ACT : std_logic := '0'; --Erase Suspend SIGNAL OTP_ACT : std_logic := '0'; --SecSi access --Model should never hang!!!!!!!!!!!!!!! SIGNAL HANG : std_logic := '0'; SIGNAL PDONE : std_logic := '1'; --Prog. Done SIGNAL PSTART : std_logic := '0'; --Start Programming --Program location is in protected sector SIGNAL PERR : std_logic := '0'; SIGNAL EDONE : std_logic := '1'; --Ers. Done SIGNAL ESTART : std_logic := '0'; --Start Erase SIGNAL ESUSP : std_logic := '0'; --Suspend Erase SIGNAL ERES : std_logic := '0'; --Resume Erase --All sectors selected for erasure are protected SIGNAL EERR : std_logic := '0'; --Sectors selected for erasure SIGNAL ERS_QUEUE : std_logic_vector(SecNum downto 0) := (OTHERS => '0'); SHARED VARIABLE BankID : Bank; SHARED VARIABLE BankASEL : Bank; SHARED VARIABLE BankPROGRAM : Bank; SHARED VARIABLE BankUBPASS : Bank; SHARED VARIABLE BankERASE : std_logic_vector(1 downto 0); --Command Register SIGNAL write : std_logic := '0'; SIGNAL read : std_logic := '0'; --Sector Address SIGNAL SecAddr : NATURAL RANGE 0 TO SecNum := 0; SIGNAL SA : NATURAL RANGE 0 TO SecNum := 0; --Address within sector SIGNAL Address : NATURAL RANGE 0 TO SecSize := 0; SIGNAL D_tmp0 : NATURAL RANGE 0 TO MaxData; SIGNAL D_tmp1 : NATURAL RANGE 0 TO MaxData; --A21:A11 Don't Care SIGNAL Addr : NATURAL RANGE 0 TO 16#7FF# := 0; --glitch protection SIGNAL gWE_n : std_logic := '1'; SIGNAL gCE_n : std_logic := '1'; SIGNAL gOE_n : std_logic := '1'; SIGNAL RST : std_logic := '1'; SIGNAL reseted : std_logic := '0'; -- Mem(SecAddr)(Address).... SHARED VARIABLE Mem : MemArray := (OTHERS =>(OTHERS=> MaxData)); SHARED VARIABLE Sec_Prot : std_logic_vector(SecNum downto 0) := (OTHERS => '0'); -- Access time variables SHARED VARIABLE OPENLATCH : BOOLEAN; SHARED VARIABLE FROMCE : BOOLEAN; SHARED VARIABLE FROMOE : BOOLEAN; --SecSi ProtectionStatus SIGNAl FactoryProt : std_logic := '1'; SIGNAL ProtSecNum : NATURAL ; SIGNAL ProtSecNum1 : NATURAL ; -- timing check violation SIGNAL Viol : X01 := '0'; PROCEDURE ADDRHILO( VARIABLE AddrLOW : INOUT NATURAL RANGE 0 to ADDRRange; VARIABLE AddrHIGH : INOUT NATURAL RANGE 0 to ADDRRange; VARIABLE SectorID : NATURAL; VARIABLE BOOT : INTEGER) IS BEGIN IF BOOT = 0 THEN --bottom IF (SectorID <= 7) THEN AddrLOW := SectorID*16#02000#; AddrHIGH := SectorID*16#02000# + 16#01FFF#; ELSE AddrLOW := (SectorID-7)*16#10000#; AddrHIGH := (SectorID-7)*16#10000#+16#0FFFF#; END IF; ELSE --top IF (SectorID < 63) THEN AddrLOW := SectorID*16#10000#; AddrHIGH := SectorID*16#10000# + 16#0FFFF#; ELSE AddrLOW := (SectorID - 63)*16#2000# + 16#3F0000#; AddrHIGH := (SectorID - 63)*16#2000# + 16#3F0000# + 16#01FFF#; END IF; END IF; END AddrHILO; FUNCTION READAS(BOOT : INTEGER) RETURN STD_LOGIC_VECTOR IS VARIABLE ReadData : STD_LOGIC_VECTOR(7 downto 0); BEGIN IF BOOT = 1 THEN ReadData := to_slv(16#5C#,8); ELSE ReadData := to_slv(16#5F#,8); END IF; RETURN ReadData; END READAS; FUNCTION READMEM(Data : INTEGER RANGE -1 TO MaxData) RETURN STD_LOGIC_VECTOR IS VARIABLE ReadData : STD_LOGIC_VECTOR(7 downto 0); BEGIN IF Data = -1 THEN ReadData := (OTHERS=>'X'); ELSE ReadData := to_slv(Data,8); END IF; RETURN ReadData; END READMEM; FUNCTION ReturnSectorID(ADDR : NATURAL; BOOT : INTEGER) RETURN NATURAL IS VARIABLE result : NATURAL; VARIABLE conv : NATURAL; BEGIN conv := ADDR / 16#8000#; IF BOOT = 0 THEN --bottom IF ( conv = 0 ) THEN result := ADDR / 16#1000#; ELSE result := 7 + conv; END IF; ELSE --top IF ( conv <= 62 ) THEN result := conv; ELSE result := 63 + (ADDR - 16#1F8000#)/16#1000#; END IF; END IF; RETURN result; END ReturnSectorID; FUNCTION ReturnSectorID1(ADDR : NATURAL; BOOT : INTEGER) RETURN NATURAL IS VARIABLE result : NATURAL; VARIABLE conv : NATURAL; BEGIN conv := ADDR / 16#10000#; IF BOOT = 0 THEN --bottom IF ( conv = 0 ) THEN result := ADDR / 16#2000#; ELSIF ( conv >= 1 ) THEN result := 7 + conv; END IF; ELSE --top IF ( conv <= 62 ) THEN result := conv; ELSE result := 63 + (ADDR - 16#3F0000#)/16#2000#; END IF; END IF; RETURN result; END ReturnSectorID1; FUNCTION BusyBankE ( BankERASE : std_logic_vector; BankID : BANK ) RETURN BOOLEAN IS VARIABLE result : BOOLEAN; BEGIN result := ((BankID = BBank) AND BankERASE(0) = '1') OR ((BankID = ABank) AND BankERASE(1) = '1'); RETURN result; END BusyBankE; PROCEDURE BankE( VARIABLE BankERASE : INOUT std_logic_vector; BankID : BANK; SetBankVars : boolean ) IS BEGIN IF ( SetBankVars ) THEN IF BankID = BBank THEN BankERASE(0) := '1'; ELSE--ABank BankERASE(1) := '1'; END IF; ELSE BankERASE := "00"; END IF; END; FUNCTION ReturnBank(ADDR : NATURAL; BOOT : INTEGER) RETURN BANK IS VARIABLE result : INTEGER; BEGIN result := ADDR / 16#40000#; IF (BOOT = 0 AND (result = 0 OR result = 1 OR result = 2 OR result = 3)) OR (BOOT = 1 AND (result = 7 OR result = 6 OR result = 5 OR result = 4)) THEN RETURN ABank; ELSE RETURN BBank; END IF; END ReturnBank; BEGIN --------------------------------------------------------------------------- --protected sectors --------------------------------------------------------------------------- ProtSecNum <= 69 WHEN TimingModel(12) = 'T' ELSE 1; ProtSecNum1 <= 70 WHEN TimingModel(12) = 'T' ELSE 0; ---------------------------------------------------------------------------- --Power Up time 100 ns; --------------------------------------------------------------------------- PoweredUp <= '1' AFTER 100 ns; RST <= RESETNeg AFTER 500 ns; --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS(A, Din, CENeg, OENeg, WENeg, RESETNeg, WPNeg) -- Timing Check Variables VARIABLE Tviol_A0_CENeg : X01 := '0'; VARIABLE TD_A0_CENeg : VitalTimingDataType; VARIABLE Tviol_A0_WENeg : X01 := '0'; VARIABLE TD_A0_WENeg : VitalTimingDataType; VARIABLE Tviol_A0_OENeg : X01 := '0'; VARIABLE TD_A0_OENeg : VitalTimingDataType; VARIABLE Tviol_CIOFNeg_WENeg : X01 := '0'; VARIABLE TD_CIOFNeg_WENeg : VitalTimingDataType; VARIABLE Tviol_DQ0_WENeg : X01 := '0'; VARIABLE TD_DQ0_WENeg : VitalTimingDataType; VARIABLE Tviol_DQ0_CENeg : X01 := '0'; VARIABLE TD_DQ0_CENeg : VitalTimingDataType; VARIABLE Tviol_CENeg_RESETNeg : X01 := '0'; VARIABLE TD_CENeg_RESETNeg : VitalTimingDataType; VARIABLE Tviol_OENeg_RESETNeg : X01 := '0'; VARIABLE TD_OENeg_RESETNeg : VitalTimingDataType; VARIABLE Tviol_OENeg_WENeg : X01 := '0'; VARIABLE TD_OENeg_WENeg : VitalTimingDataType; VARIABLE Tviol_WENeg_OENeg : X01 := '0'; VARIABLE TD_WENeg_OENeg : VitalTimingDataType; VARIABLE Tviol_CIOFNeg_CENeg : X01 := '0'; VARIABLE TD_CIOFNeg_CENeg : VitalTimingDataType; VARIABLE Pviol_RESETNeg : X01 := '0'; VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_OENeg : X01 := '0'; VARIABLE PD_OENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CENeg : X01 := '0'; VARIABLE PD_CENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg : X01 := '0'; VARIABLE PD_WENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A0 : X01 := '0'; VARIABLE PD_A0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN --------------------------------------------------------------------------- -- Timing Check Section --------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Setup/Hold Check between A and CENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => CENeg, RefSignalName => "CE#", SetupHigh => tsetup_A0_CENeg, SetupLow => tsetup_A0_CENeg, HoldHigh => thold_A0_CENeg, HoldLow => thold_A0_CENeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CENeg, Violation => Tviol_A0_CENeg ); -- Setup/Hold Check between A and WENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => tsetup_A0_CENeg, SetupLow => tsetup_A0_CENeg, HoldHigh => thold_A0_CENeg, HoldLow => thold_A0_CENeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_WENeg, Violation => Tviol_A0_WENeg ); -- Setup/Hold Check between A and OENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => OENeg, RefSignalName => "OE#", SetupHigh => tsetup_A0_OENeg, SetupLow => tsetup_A0_OENeg, HoldHigh => thold_A0_OENeg, HoldLow => thold_A0_OENeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_OENeg, Violation => Tviol_A0_OENeg ); -- Setup/Hold Check between CIOFNeg and WENeg VitalSetupHoldCheck ( TestSignal => CIOFNeg, TestSignalName => "CIOFNeg", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => tsetup_A0_CENeg, SetupLow => tsetup_A0_CENeg, HoldHigh => thold_A0_CENeg,--used HoldLow => thold_A0_CENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CIOFNeg_WENeg, Violation => Tviol_CIOFNeg_WENeg ); -- Setup/Hold Check between DQ and CENeg VitalSetupHoldCheck ( TestSignal => DQ0, TestSignalName => "DQ", RefSignal => CENeg, RefSignalName => "CE#", SetupHigh => tsetup_DQ0_CENeg, SetupLow => tsetup_DQ0_CENeg, HoldHigh => thold_DQ0_CENeg, HoldLow => thold_DQ0_CENeg, CheckEnabled => (DIn(14 downto 0) /= DOut_zd(14 downto 0) AND CENeg = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_CENeg, Violation => Tviol_DQ0_CENeg ); -- Setup/Hold Check between DQ and WENeg VitalSetupHoldCheck ( TestSignal => DQ0, TestSignalName => "DQ", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => tsetup_DQ0_CENeg, SetupLow => tsetup_DQ0_CENeg, HoldHigh => thold_DQ0_CENeg, HoldLow => thold_DQ0_CENeg, CheckEnabled => (DIn(14 downto 0) /= DOut_zd(14 downto 0) AND CENeg = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_WENeg, Violation => Tviol_DQ0_WENeg ); -- Hold Check between CENeg and RESETNeg VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CE#", RefSignal => RESETNeg, RefSignalName => "RESET#", HoldHigh => thold_CENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_RESETNeg, Violation => Tviol_CENeg_RESETNeg ); -- Hold Check between OENeg and RESETNeg VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OE#", RefSignal => RESETNeg, RefSignalName => "RESET#", HoldHigh => thold_CENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_RESETNeg, Violation => Tviol_OENeg_RESETNeg ); -- Hold Check between OENeg and WENeg VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OE#", RefSignal => WENeg, RefSignalName => "WE#", HoldHigh => thold_OENeg_WENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_WENeg, Violation => Tviol_OENeg_WENeg ); -- Hold Check between WENeg and OENeg VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WE#", RefSignal => OENeg, RefSignalName => "OE#", HoldHigh => thold_WENeg_OENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_OENeg, Violation => Tviol_WENeg_OENeg ); -- Hold Check between CIOFNeg and CENeg VitalSetupHoldCheck ( TestSignal => CIOFNeg, TestSignalName => "CIOF#", RefSignal => CENeg, RefSignalName => "CE#", HoldHigh => thold_CIOFNeg_CENeg,--5ns HoldLow => thold_CIOFNeg_CENeg, --used CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CIOFNeg_CENeg, Violation => Tviol_CIOFNeg_CENeg ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESET#", PulseWidthLow => tpw_RESETNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg, Violation => Pviol_RESETNeg ); -- PulseWidth Check for OENeg VitalPeriodPulseCheck ( TestSignal => OENeg, TestSignalName => "OE#", PulseWidthHigh => tpw_OENeg_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_OENeg, Violation => Pviol_OENeg ); -- PulseWidth Check for WENeg, Flash VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WE#", PulseWidthHigh => tpw_WENeg_posedge, PulseWidthLow => tpw_WENeg_negedge, CheckEnabled => CENeg = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg, Violation => Pviol_WENeg ); -- PulseWidth Check for CENeg VitalPeriodPulseCheck ( TestSignal => CENeg, TestSignalName => "CE#", PulseWidthHigh => tpw_CENeg_posedge, PulseWidthLow => tpw_CENeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_CENeg, Violation => Pviol_CENeg ); -- PulseWidth Check for A VitalPeriodPulseCheck ( TestSignal => A(0), TestSignalName => "A", PulseWidthHigh => tpw_A0_negedge, PulseWidthLow => tpw_A0_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_A0, Violation => Pviol_A0 ); Violation := Tviol_A0_CENeg OR Tviol_A0_WENeg OR Tviol_A0_OENeg OR Tviol_CIOFNeg_WENeg OR Tviol_DQ0_WENeg OR Tviol_DQ0_CENeg OR Tviol_CENeg_RESETNeg OR Tviol_OENeg_RESETNeg OR Tviol_OENeg_WENeg OR Tviol_WENeg_OENeg OR Tviol_CIOFNeg_CENeg OR Pviol_RESETNeg OR Pviol_OENeg OR Pviol_CENeg OR Pviol_WENeg OR Pviol_A0 ; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS VITALTimingCheck; ---------------------------------------------------------------------------- -- sequential process for reset control and FSM state transition ---------------------------------------------------------------------------- StateTransition : PROCESS(next_state, RESETNeg, RST, READY, PDone, EDone, PoweredUp) VARIABLE R : std_logic := '0'; --prog or erase in progress VARIABLE E : std_logic := '0'; --reset timming error BEGIN IF PoweredUp = '1' THEN --Hardware reset timing control IF falling_edge(RESETNeg) THEN E := '0'; IF (PDONE = '0' OR EDONE = '0') THEN --if program or erase in progress READY_in <= '1'; R := '1'; ELSE READY_in <= '0'; R := '0'; --prog or erase not in progress END IF; ELSIF rising_edge(RESETNeg) AND RST = '1' THEN --RESET# pulse < tRP READY_in <= '0'; R := '0'; E := '1'; END IF; IF RESETNeg = '1' AND ( R = '0' OR (R = '1' AND READY = '1')) THEN current_state <= next_state; READY_in <= '0'; E := '0'; R := '0'; reseted <= '1'; ELSIF (R = '0' AND RESETNeg = '0' AND RST = '0') OR (R = '1' AND RESETNeg = '0' AND RST = '0' AND READY = '0') OR (R = '1' AND RESETNeg = '1' AND RST = '0' AND READY = '0') OR (R = '1' AND RESETNeg = '1' AND RST = '1' AND READY = '0') THEN --no state transition while RESET# low current_state <= RESET; --reset start reseted <= '0'; END IF; ELSE current_state <= RESET; -- reset reseted <= '0'; E := '0'; R := '0'; END IF; END PROCESS StateTransition; --------------------------------------------------------------------------- --Glitch Protection: Inertial Delay does not propagate pulses <5ns --------------------------------------------------------------------------- gWE_n <= WENeg AFTER 5 ns; gCE_n <= CENeg AFTER 5 ns; gOE_n <= OENeg AFTER 5 ns; --latch address on rising edge and data on falling edge of write write_dc: PROCESS (gWE_n, gCE_n, gOE_n, RESETNeg, reseted) BEGIN IF RESETNeg /= '0' AND reseted ='1' THEN IF (gWE_n = '0') AND (gCE_n = '0') AND (gOE_n = '1') THEN write <= '1'; ELSIF (gWE_n = '1' OR gCE_n = '1') AND gOE_n = '1' THEN write <= '0'; ELSE write <= 'X'; END IF; END IF; IF ((gWE_n = '1') AND (gCE_n = '0') AND (gOE_n = '0')) THEN read <= '1'; ELSE read <= '0'; END IF; END PROCESS write_dc; --------------------------------------------------------------------------- --Process that reports warning when changes on signals WE#, CE#, OE# are --discarded --------------------------------------------------------------------------- PulseWatch : PROCESS (WENeg, CENeg, OENeg, gWE_n, gCE_n, gOE_n) BEGIN IF (gWE_n'EVENT AND (gWE_n /= WENeg)) OR (gCE_n'EVENT AND (gCE_n /= CENeg)) OR (gOE_n'EVENT AND (gOE_n /= OENeg)) THEN ASSERT false REPORT "Glitch detected on write control signals" SEVERITY warning; END IF; END PROCESS PulseWatch; --------------------------------------------------------------------------- -- Latch address on falling edge of WE# or CE# what ever comes later -- Latches data on rising edge of WE# or CE# what ever comes first -- also Write cycle decode --------------------------------------------------------------------------- BusCycleDecode : PROCESS(A, Din, write, WENeg, CENeg, OENeg, CIOFNeg, reseted) VARIABLE A_tmp : NATURAL RANGE 0 TO 16#7FF#; VARIABLE A_tmp1 : NATURAL RANGE 0 TO SecSize; VARIABLE AddrTmp : NATURAL RANGE 0 TO ADDRRange; VARIABLE AddrLOW : NATURAL RANGE 0 TO ADDRRange; VARIABLE AddrHIGH : NATURAL RANGE 0 TO ADDRRange; VARIABLE AddressLatched : NATURAL RANGE 0 TO ADDRRange; VARIABLE sector : NATURAL; VARIABLE top_bottom : INTEGER; VARIABLE CE : std_logic; BEGIN IF reseted = '1' THEN IF TimingModel(12) = 'T' THEN top_bottom := 1; ELSE top_bottom := 0; END IF; IF ((falling_edge(WENeg) AND CENeg ='0' AND OENeg = '1') OR (falling_edge(CENeg) AND WENeg/= OENeg ) OR (falling_edge(OENeg) AND WENeg ='1' AND CENeg = '0') OR ((A'EVENT OR (Din(15)'EVENT AND CIOFNeg='0') OR CIOFNeg'EVENT) AND WENeg = '1' AND CENeg = '0' AND OENeg = '0')) THEN A_tmp := to_nat(A(10 downto 0)); AddressLatched := to_nat(A); BankID := ReturnBank(AddressLatched,top_bottom); sector := ReturnSectorID(AddressLatched,top_bottom); ADDRHILO(AddrLOW,AddrHIGH,sector,top_bottom); AddrTmp := AddressLatched - (AddrLOW/2); IF (CIOFNeg = '0') THEN A_tmp1 := to_nat(to_slv(AddrTmp,15) & Din(15)); ELSE A_tmp1 := to_nat(to_slv(AddrTmp,15) & '0'); END IF; ELSIF (rising_edge(WENeg) OR rising_edge(CENeg)) AND write = '1' THEN D_tmp0 <= to_nat(Din(7 downto 0)); IF CIOFNeg = '1' THEN D_tmp1 <= to_nat(Din(15 downto 8)); END IF; END IF; IF (rising_edge(write) OR falling_edge(OENeg) OR ((A'EVENT OR (Din(15)'EVENT AND CIOFNeg = '0') OR CIOFNeg'EVENT) AND WENeg = '1' AND CENeg = '0' AND OENeg = '0')) THEN BankID := ReturnBank(AddressLatched,top_bottom); SecAddr <= ReturnSectorID(AddressLatched,top_bottom); Address <= A_tmp1; CE := CENeg; Addr <= A_tmp; END IF; END IF; END PROCESS BusCycleDecode; --------------------------------------------------------------------------- -- Timing control for the Program --------------------------------------------------------------------------- ProgTime : PROCESS(PSTART, CIOFNeg, ESP_ACT, OTP_ACT, reseted) VARIABLE cnt : NATURAL RANGE 0 TO SecNum + 1 := 0; VARIABLE duration : time; VARIABLE pob : time; BEGIN IF LongTimming THEN pob := tdevice_POB; ELSE pob := tdevice_POB / 100; END IF; IF rising_edge(reseted) THEN PDONE <= '1'; -- reset done, programing terminated ELSIF reseted = '1' THEN IF rising_edge(PSTART) AND PDONE = '1' THEN IF NOT(Sec_Prot(SA) = '1' OR (Ers_queue(SA) = '1' AND ESP_ACT = '1') OR (FactoryProt = '1' AND OTP_ACT = '1')) THEN --Word/Byte program IF CIOFNeg = '1' THEN cnt := 2; ELSE cnt := 1; END IF; duration := cnt * pob; PDONE <= '0', '1' AFTER duration; ELSE PERR <= '1', '0' AFTER 1 us; END IF; END IF; END IF; END PROCESS ProgTime; --------------------------------------------------------------------------- -- Timing control for the Erase Operations --------------------------------------------------------------------------- ErsTime :PROCESS(ESTART, ESUSP, ERES, Ers_Queue, reseted) VARIABLE cnt : NATURAL RANGE 0 TO SecNum + 1 := 0; VARIABLE elapsed : time; VARIABLE duration : time; VARIABLE start : time; VARIABLE seo : time; BEGIN IF LongTimming THEN seo := tdevice_SEO; ELSE seo := tdevice_SEO / 1000; END IF; IF rising_edge(reseted) THEN EDONE <= '1'; -- reset done, ERASE terminated ELSIF reseted = '1' THEN IF rising_edge(ESTART) AND EDONE = '1' THEN cnt := 0; FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN cnt := cnt + 1; END IF; END LOOP; IF cnt > 0 THEN elapsed := 0 ns; duration := cnt * seo; EDONE <= '0', '1' AFTER duration; start := NOW; ELSE EERR <= '1', '0' AFTER 100 us; END IF; ELSIF rising_edge(ESUSP) AND EDONE = '0' THEN elapsed := NOW - start; duration := duration - elapsed; EDONE <= '0'; ELSIF rising_edge(ERES) AND EDONE = '0' THEN start := NOW; EDONE <= '0', '1' AFTER duration; END IF; END IF; END PROCESS; --------------------------------------------------------------------------- -- Main Behavior Process -- combinational process for next state generation --------------------------------------------------------------------------- StateGen :PROCESS(write, Addr, D_tmp0, ULBYPASS, PDONE, EDONE, HANG, CTMOUT, START_T1, reseted, READY, PERR, EERR) VARIABLE PATTERN_1 : boolean := FALSE; VARIABLE PATTERN_2 : boolean := FALSE; VARIABLE A_PAT_1 : boolean := FALSE; --DATA High Byte VARIABLE DataHi : NATURAL RANGE 0 TO MaxData := 0; --DATA Low Byte VARIABLE DataLo : NATURAL RANGE 0 TO MaxData := 0; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(write) THEN DataLo := D_tmp0; PATTERN_1 := (Addr=16#555#) AND (DataLo = 16#AA#) ; PATTERN_2 := (Addr=16#2AA#) AND (DataLo = 16#55#) ; A_PAT_1 := ((Addr=16#555#) AND (ULBYPASS = '0')) OR (ULBYPASS = '1'); END IF; IF reseted /= '1' THEN next_state <= current_state; ELSE CASE current_state IS WHEN RESET => IF falling_edge(write) THEN IF (PATTERN_1) THEN next_state <= Z001; ELSIF ((Addr=16#55#) AND (DataLo=16#98#)) THEN next_state <= CFI; ELSE next_state <= RESET; END IF; END IF; WHEN Z001 => IF falling_edge(write) THEN IF (PATTERN_2) THEN next_state <= PREL_SETBWB; ELSE next_state <= RESET; END IF; END IF; WHEN PREL_SETBWB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#20#)) THEN next_state <= PREL_ULBYPASS; ELSIF (A_PAT_1 AND (DataLo=16#90#)) THEN next_state <= AS; ELSIF (A_PAT_1 AND (DataLo=16#A0#)) THEN next_state <= A0SEEN; ELSIF (A_PAT_1 AND (DataLo=16#88#)) THEN next_state <= OTP; ELSIF (A_PAT_1 AND (DataLo=16#80#)) THEN next_state <= C8; ELSE next_state <= RESET; END IF; END IF; WHEN PREL_ULBYPASS => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#90#)) THEN next_state <= RES_ULBYPASS; ELSIF (A_PAT_1 AND (DataLo=16#A0#)) THEN next_state <= A0SEEN; ELSIF (A_PAT_1 AND (DataLo=16#88#)) THEN next_state <= OTP; ELSIF (A_PAT_1 AND (DataLo=16#80#)) THEN next_state <= C8_PREL; END IF; END IF; WHEN RES_ULBYPASS => IF falling_edge(WRITE) THEN IF (A_PAT_1 AND (DataLo = 16#00#)) THEN next_state <= RESET; ELSE next_state <= PREL_ULBYPASS; END IF; END IF; WHEN CFI => IF falling_edge(write) THEN IF (Addr=16#55#) AND (DataLo=16#98#) THEN next_state <= CFI; ELSIF (DataLo=16#F0#) THEN next_state <= RESET; ELSE next_state <= CFI; END IF; END IF; WHEN AS => IF falling_edge(write) THEN IF (DataLo=16#F0#) THEN next_state <= RESET; ELSE next_state <= AS; END IF; END IF; WHEN A0SEEN => IF falling_edge(write) THEN IF ( ULBYPASS = '1' AND BankID = BankUBPASS ) OR ULBYPASS = '0' THEN next_state <= PGMS; --set ESP END IF; ELSE next_state <= A0SEEN; END IF; WHEN OTP => IF falling_edge(write) THEN IF PATTERN_1 THEN next_state <= OTP_Z001; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= OTP_PREL; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_PREL => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#90#))THEN next_state <= OTP_AS; ELSIF (A_PAT_1 AND (DataLo = 16#A0#))THEN next_state <= OTP_A0SEEN; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_AS => IF falling_edge(write) THEN IF DataLo=16#F0# THEN IF ESP_ACT = '1' THEN next_state <= ESP; ELSE next_state <= RESET; END IF; ELSIF DataLo=16#00# THEN IF ESP_ACT = '1' THEN next_state <= ESP; ELSE next_state <= RESET; END IF; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_A0SEEN => IF falling_edge(write) THEN IF ( ULBYPASS = '1' AND BankID = BankUBPASS) OR ULBYPASS = '0' THEN next_state <= PGMS; --set ESP END IF; ELSE next_state <= OTP_A0SEEN; END IF; WHEN C8 => IF falling_edge(write) THEN IF PATTERN_1 THEN next_state <= C8_Z001; ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; END IF; WHEN C8_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= C8_PREL; ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; END IF; WHEN C8_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo=16#10# THEN next_state <= ERS; ELSIF DataLo = 16#30# AND NOT (ULBYPASS = '1' AND BankID /= BankUBPASS) THEN next_state <= SERS; ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; END IF; WHEN ERS => IF rising_edge(EDONE) OR falling_edge(EERR) THEN IF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; END IF; WHEN SERS => IF CTMOUT'EVENT AND CTMOUT = '1' THEN next_state <= SERS_EXEC; ELSIF falling_edge(write) THEN IF (DataLo = 16#B0# AND BusyBankE(BankERASE,BankID)) THEN next_state <= ESP; -- ESP according to datasheet ELSIF (DataLo=16#30#) THEN next_state <= SERS; ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; --C8_PREL; ELSE next_state <= RESET; END IF; END IF; WHEN ESPS => IF (START_T1 = '1') THEN next_state <= ESP; END IF; WHEN SERS_EXEC => IF rising_edge(EDONE) OR falling_edge(EERR) THEN IF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; ELSIF EERR /= '1' THEN IF falling_edge(write) THEN IF (DataLo=16#B0# AND BusyBankE(BankERASE,BankID)) THEN next_state <= ESPS; END IF; END IF; END IF; WHEN ESP => IF falling_edge(write) THEN IF DataLo = 16#30# AND BusyBankE(BankERASE,BankID) THEN next_state <= SERS_EXEC; ELSIF ULBYPASS = '1' THEN IF DataLo = 16#98# THEN next_state <= ESP_CFI; ELSIF A_PAT_1 AND DataLo = 16#A0# AND BankID = BankUBPASS THEN next_state <= ESP_A0SEEN; ELSIF A_PAT_1 AND DataLo = 16#88# THEN next_state <= OTP; --set ESP ELSIF A_PAT_1 AND DataLo = 16#90# THEN next_state <= ESP_AS; END IF; ELSE IF Addr = 16#55# AND DataLo = 16#98# THEN next_state <= ESP_CFI; ELSIF PATTERN_1 THEN next_state <= ESP_Z001; END IF; END IF; END IF; WHEN ESP_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= ESP_PREL; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#20# THEN next_state <= ESP; --set ULBYPASS ELSIF A_PAT_1 AND DataLo = 16#A0# THEN next_state <= ESP_A0SEEN; ELSIF A_PAT_1 AND DataLo = 16#88# THEN next_state <= OTP; --set ESP ELSIF A_PAT_1 AND DataLo = 16#90# THEN next_state <= ESP_AS; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_CFI => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN next_state <= ESP; ELSIF DataLo = 16#30# THEN next_state <= SERS_EXEC; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_A0SEEN => IF falling_edge(write) THEN next_state <= PGMS; --set ESP END IF; WHEN ESP_AS => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN -- reset ULBYPASS next_state <= ESP; END IF; END IF; WHEN PGMS => IF rising_edge(PDONE) OR falling_edge(PERR) THEN IF ESP_ACT = '1' THEN next_state <= ESP; ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSIF OTP_ACT = '1' THEN next_state <= OTP; ELSE next_state <= RESET; END IF; ELSIF OTP_ACT = '1' THEN null; END IF; END CASE; END IF; END PROCESS StateGen; WP_CTRL: PROCESS(WPNeg) VARIABLE Sec_Prot_reg0 : std_logic := '0'; VARIABLE Sec_Prot_reg1 : std_logic := '0'; BEGIN --Hardware Write Protection IF falling_edge(WPNeg) THEN Sec_Prot_reg0 := Sec_Prot(ProtSecNum); Sec_Prot_reg1 := Sec_Prot(ProtSecNum1); Sec_Prot(ProtSecNum) := '1'; Sec_Prot(ProtSecNum1) := '1'; ELSIF rising_edge(WPNeg) THEN Sec_Prot(ProtSecNum) := Sec_Prot_reg0; Sec_Prot(ProtSecNum1) := Sec_Prot_reg1; END IF; END PROCESS WP_CTRL; --------------------------------------------------------------------------- --FSM Output generation and general funcionality --------------------------------------------------------------------------- Functional : PROCESS(write, read, Addr, D_tmp0, D_tmp1, Address, SecAddr, PDONE, EDONE, HANG, START_T1, CTMOUT, RST, reseted, READY, gOE_n, current_state, A) --Flash Memory Array TYPE SecType IS ARRAY (0 TO SecSize) OF INTEGER RANGE -1 TO MaxData; TYPE MemArray IS ARRAY (0 TO SecNum) OF SecType; --Common Flash Interface Query codes TYPE CFItype IS ARRAY (16#10# TO 16#4F#) OF NATURAL RANGE 0 TO 16#FF#; --SecSi Sector TYPE SecSiType IS ARRAY ( 0 TO SecSiSize) OF INTEGER RANGE -1 TO MaxData; TYPE WDataType IS ARRAY ( 0 TO 1) OF INTEGER RANGE -1 TO MaxData; TYPE WAddrType IS ARRAY ( 0 TO 1) OF INTEGER RANGE -1 TO SecSize; VARIABLE WData : WDataType:= (OTHERS => 0); VARIABLE WAddr : WAddrType:= (OTHERS => -1); -- Mem(SecAddr)(Address).... VARIABLE Mem : MemArray := (OTHERS => (OTHERS => MaxData)); VARIABLE CFI_array : CFItype := (OTHERS => 0); VARIABLE SecSi : SecSiType := (OTHERS => 0); VARIABLE PATTERN_1 : boolean := FALSE; VARIABLE PATTERN_2 : boolean := FALSE; VARIABLE A_PAT_1 : boolean := FALSE; VARIABLE oe : boolean := FALSE; --Status reg. VARIABLE Status : std_logic_vector(7 downto 0) := (OTHERS => '0'); -- text file input variables FILE mem_file : text is mem_file_name; FILE prot_file : text is prot_file_name; FILE secsi_file : text is secsi_file_name; VARIABLE AddrLo : NATURAL; VARIABLE AddrHi : NATURAL; VARIABLE SECT : NATURAL; VARIABLE top_bottom : INTEGER; VARIABLE ind : NATURAL RANGE 0 TO AddrRANGE := 0; VARIABLE Addr_ind : NATURAL RANGE 0 TO SecSize := 0; VARIABLE buf : line; VARIABLE old_bit : std_logic_vector(7 downto 0); VARIABLE new_bit : std_logic_vector(7 downto 0); VARIABLE old_int : INTEGER RANGE -1 to MaxData; VARIABLE new_int : INTEGER RANGE -1 to MaxData; VARIABLE wr_cnt : NATURAL RANGE 0 TO 31; --DATA High Byte VARIABLE DataHi : NATURAL RANGE 0 TO MaxData := 0; --DATA Low Byte VARIABLE DataLo : NATURAL RANGE 0 TO MaxData := 0; VARIABLE temp : std_logic_vector(7 downto 0); VARIABLE SecSiAddr : NATURAL RANGE 0 TO SecSiSize := 0; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(write) THEN DataLo := D_tmp0; DataHi := D_tmp1; PATTERN_1 := (Addr=16#555#) AND (DataLo=16#AA#) ; PATTERN_2 := (Addr=16#2AA#) AND (DataLo=16#55#) ; A_PAT_1 := ((Addr=16#555#) AND (ULBYPASS='0')) OR (ULBYPASS='1'); END IF; oe := rising_edge(read) OR (read = '1' AND Address'EVENT); IF reseted = '1' THEN CASE current_state IS WHEN RESET => OTP_ACT <= '0'; ESP_ACT <= '0'; IF falling_edge(write) THEN IF ((Addr=16#55#) AND (DataLo=16#98#))THEN ULBYPASS <= '0'; END IF; ELSIF oe THEN DOut_zd(7 downto 0) <= READMEM(Mem(SecAddr)(Address)); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= READMEM(Mem(SecAddr)(Address + 1)); END IF; END IF; --ready signal active RY_zd <= '1'; WHEN Z001 => null; WHEN PREL_SETBWB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#20#)) THEN ULBYPASS <= '1'; BankUBPASS := BankID; ELSIF (A_PAT_1 AND (DataLo = 16#90#)) THEN ULBYPASS <= '0'; BankASEL := BankID; ELSIF (A_PAT_1 AND (DataLo = 16#88#)) THEN ULBYPASS <= '0'; OTP_ACT <= '1'; END IF; END IF; WHEN PREL_ULBYPASS => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#88#)) THEN ULBYPASS <= '0'; OTP_ACT <= '1'; END IF; ELSIF oe THEN IF BankID /= BankUBPASS THEN DOut_zd(7 downto 0) <= READMEM(Mem(SecAddr)(Address)); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= READMEM(Mem(SecAddr)(Address + 1)); END IF; ELSE DOut_zd(7 downto 0) <= (OTHERS => 'Z'); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= (OTHERS => 'Z'); END IF; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN RES_ULBYPASS => IF falling_edge(WRITE) THEN IF (A_PAT_1 AND (DataLo = 16#00#)) THEN ULBYPASS <= '0'; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN CFI => IF falling_edge(write) THEN IF (DataLo=16#F0#) THEN ULBYPASS <= '0'; END IF; ELSIF oe THEN DOut_zd(15 downto 0) <= (OTHERS => '0'); IF ((Addr>=16#10#) AND (Addr <= 16#4F#)) THEN DOut_zd(7 downto 0) <= to_slv(CFI_array(Addr) ,8); ELSE ASSERT FALSE REPORT "Invalid CFI query address" SEVERITY warning; END IF; END IF; WHEN AS => IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN ULBYPASS <= '0'; END IF; ELSIF oe THEN IF BankID = BankASEL THEN IF CIOFNeg = '1' THEN IF Address = 0 THEN DOut_zd(15 downto 8) <= to_slv(0,8); ELSIF Addr = 1 THEN DOut_zd(15 downto 8) <= to_slv(16#22#,8); ELSIF Addr = 2 THEN DOut_zd(15 downto 8) <= to_slv(0,8); ELSIF Addr = 3 THEN DOut_zd(15 downto 8) <= to_slv(0,8); END IF; ELSE DOut_zd(15 downto 8) <= "ZZZZZZZZ"; END IF; IF Addr = 0 THEN DOut_zd(7 downto 0) <= to_slv(1,8); ELSIF Addr = 1 THEN DOut_zd(7 downto 0) <= READAS(top_bottom); ELSIF Addr = 2 THEN DOut_zd(7 downto 1) <= to_slv(0,7); DOut_zd(0) <= Sec_Prot(SecAddr); ELSIF Addr = 3 THEN DOut_zd(7 downto 0) <= to_slv(2,8); DOut_zd(7) <= FactoryProt; END IF; ELSE DOut_zd(7 downto 0) <= READMEM(Mem(SecAddr)(Address)); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= READMEM(Mem(SecAddr)(Address + 1)); END IF; END IF; END IF; WHEN A0SEEN => IF falling_edge(write) AND NOT (ULBYPASS = '1' AND BankID /= BankUBPASS) THEN BankPROGRAM := BankID; PSTART <= '1', '0' AFTER 1 ns; WData(0) := -1; WData(1) := -1; IF Viol = '0' THEN WData(0) := DataLo; WData(1) := DataHi; END IF; WAddr(0) := Address; SA <= SecAddr; temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); IF CIOFNeg = '1' THEN WAddr(1) := WAddr(0) +1; ELSE WAddr(1) := -1; END IF; END IF; WHEN OTP => OTP_ACT <= '1'; IF oe THEN --read SecSi Sector Region SecSiAddr := Address MOD (SecSiSize + 1); DOut_zd(7 downto 0) <= (OTHERS => 'X'); IF SecSi(SecSiAddr) /= -1 THEN DOut_zd(7 downto 0) <= to_slv(SecSi(SecSiAddr),8); END IF; IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= (OTHERS => 'X'); IF SecSi(SecSiAddr + 1) /= -1 THEN DOut_zd(15 downto 8) <= to_slv(SecSi(SecSiAddr + 1),8); END IF; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN OTP_Z001 => null; WHEN OTP_PREL => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#90#))THEN ULBYPASS <= '0'; BankASEL := BankID; END IF; END IF; WHEN OTP_AS => IF falling_edge(write) THEN IF DataLo=16#F0# OR DataLo=16#00# THEN OTP_ACT <='0'; IF ESP_ACT = '1' THEN ULBYPASS <= '0'; END IF; END IF; ELSIF oe THEN IF BankID = BankASEL THEN IF CIOFNeg = '1' THEN IF Address = 0 THEN DOut_zd(15 downto 8) <= to_slv(0,8); ELSIF Addr = 1 THEN DOut_zd(15 downto 8) <= to_slv(16#22#,8); ELSIF Addr = 2 THEN DOut_zd(15 downto 8) <= to_slv(0,8); ELSIF Addr = 3 THEN DOut_zd(15 downto 8) <= to_slv(0,8); END IF; ELSE DOut_zd(15 downto 8) <= "ZZZZZZZZ"; END IF; IF Addr = 0 THEN DOut_zd(7 downto 0) <= to_slv(1,8); ELSIF Addr = 1 THEN DOut_zd(7 downto 0) <= READAS(top_bottom); ELSIF Addr = 2 THEN DOut_zd(7 downto 1) <= to_slv(0,7); DOut_zd(0) <= Sec_Prot(SecAddr); ELSIF Addr = 3 THEN DOut_zd(7 downto 0) <= to_slv(2,8); DOut_zd(7) <= FactoryProt; END IF; ELSE DOut_zd(7 downto 0) <= READMEM(Mem(SecAddr)(Address)); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= READMEM(Mem(SecAddr)(Address + 1)); END IF; END IF; END IF; WHEN OTP_A0SEEN => IF falling_edge(write) THEN -- proveri uslov kao kod A0SEEN OTP_ACT <= '1'; ----------------------------------------------------------- --SecSi programming: TBD ----------------------------------------------------------- BankPROGRAM := ABank; PSTART <= '1', '0' AFTER 1 ns; WData(0) := -1; WData(1) := -1; IF Viol = '0' THEN WData(0) := DataLo; WData(1) := DataHi; END IF; WAddr(0) := Address; SA <= 70 * top_bottom; ASSERT (SecAddr = 0 AND top_bottom = 0) OR (SecAddr = 70 AND top_bottom = 1) REPORT "Invalid sector Address in SecSi" SEVERITY warning; temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); IF CIOFNeg = '1' THEN WAddr(1) := WAddr(0) + 1; ELSE WAddr(1) := -1; END IF; END IF; WHEN C8 => null; WHEN C8_Z001 => null; WHEN C8_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#10# THEN --Start Chip Erase ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; Ers_Queue <= (OTHERS => '1'); Status := "00001000"; ELSIF DataLo=16#30# AND NOT (ULBYPASS = '1' AND BankID /= BankUBPASS) THEN BankE(BankERASE, BankID, TRUE); --put selected sector to sec. ers. queue --start timeout Ers_Queue <= (OTHERS => '0'); Ers_Queue(SecAddr) <= '1'; CTMOUT_in <= '0', '1' AFTER 2 ns; END IF; END IF; WHEN ERS => IF oe THEN ----------------------------------------------------------- -- read status / embeded erase algorithm - Chip Erase ----------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; END IF; IF EERR /= '1' THEN FOR i IN 0 TO SecNum LOOP IF Sec_Prot(i) /= '1' THEN Mem(i) := (OTHERS => -1); END IF; END LOOP; IF EDONE = '1' THEN FOR i IN 0 TO SecNum LOOP IF Sec_Prot(i) /= '1' THEN Mem(i) := (OTHERS => MaxData); END IF; END LOOP; END IF; END IF; -- busy signal active RY_zd <= '0'; WHEN SERS => IF CTMOUT = '1' THEN CTMOUT_in <= '0'; START_T1_in <= '0'; ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; IF oe THEN --read status END IF; ELSIF falling_edge(write) THEN IF (DataLo = 16#B0# AND BusyBankE(BankERASE,BankID)) THEN --need to start erase process prior to suspend ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; --suspend timeout (should be 0 according to datasheet) ESUSP <= '1' AFTER 2 ns, '0' AFTER 3 ns; ELSIF (DataLo=16#30# ) THEN BankE(BankERASE, BankID, TRUE); CTMOUT_in <= '0', '1' AFTER 1 ns; Ers_Queue(SecAddr) <= '1'; END IF; ELSIF oe THEN IF BusyBankE(BankERASE,BankID) THEN ----------------------------------------------------------- --read status - sector erase timeout ----------------------------------------------------------- Status(3) := '0'; DOut_zd(7 downto 0) <= Status; ELSE DOut_zd(7 downto 0) <= READMEM(Mem(SecAddr)(Address)); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= READMEM(Mem(SecAddr)(Address + 1)); END IF; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN ESPS => ESUSP <= '1';--, '0' AFTER 1 ns; IF (START_T1 = '1') THEN ESP_ACT <= '1'; START_T1_in <= '0'; ELSIF oe THEN IF BusyBankE(BankERASE,BankID) THEN ----------------------------------------------------------- --read status / erase suspend timeout - stil erasing ----------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; IF Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); --toggle END IF; DOut_zd(7 downto 0) <= Status; ELSE DOut_zd(7 downto 0) <= READMEM(Mem(SecAddr)(Address)); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= READMEM(Mem(SecAddr)(Address + 1)); END IF; END IF; END IF; --busy signal active RY_zd <= '0'; WHEN SERS_EXEC => IF oe THEN IF BusyBankE(BankERASE,BankID) THEN ----------------------------------------------------------- --read status Erase Busy ----------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; IF Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); --toggle END IF; DOut_zd(7 downto 0) <= Status; ELSE DOut_zd(7 downto 0) <= READMEM(Mem(SecAddr)(Address)); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= READMEM(Mem(SecAddr)(Address + 1)); END IF; END IF; END IF; IF rising_edge(EDONE) THEN BankE(BankERASE, BankID, false); END IF; IF EERR /= '1' THEN FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN Mem(i) := (OTHERS => -1); END IF; END LOOP; IF EDONE = '1' THEN FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN Mem(i) := (OTHERS => MaxData); END IF; END LOOP; ELSIF falling_edge(write) THEN IF DataLo=16#B0# THEN START_T1_in <= '1'; END IF; END IF; END IF; --busy signal active RY_zd <= '0'; WHEN ESP => IF falling_edge(write) THEN IF DataLo = 16#30# AND BusyBankE(BankERASE,BankID) THEN --resume erase ERES <= '1', '0' AFTER 1 ns; ELSIF ULBYPASS = '1' THEN IF A_PAT_1 AND DataLo = 16#88# THEN ESP_ACT <= '1'; END IF; END IF; ELSIF oe THEN ----------------------------------------------------------- --read ----------------------------------------------------------- IF Ers_Queue(SecAddr) /= '1' THEN DOut_zd(7 downto 0) <= READMEM(Mem(SecAddr)(Address)); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= READMEM(Mem(SecAddr)(Address + 1)); END IF; ELSE ------------------------------------------------------- --read status ------------------------------------------------------- Status(7) := '1'; -- Status(6) No toggle Status(5) := '0'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN ESP_Z001 => null; WHEN ESP_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#20# THEN ULBYPASS <= '1'; ELSIF A_PAT_1 AND DataLo = 16#88# THEN ESP_ACT <= '1'; END IF; END IF; WHEN ESP_CFI => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN ESP_ACT <= '1'; ELSIF DataLo = 16#30# AND BusyBankE(BankERASE,BankID) THEN --resume erase ERES <= '1', '0' AFTER 1 ns; ELSE ESP_ACT <= '1'; END IF; ELSIF oe THEN DOut_zd(15 downto 0) <= (OTHERS => '0'); IF ((Addr >= 16#10#) AND (Addr<=16#4F#)) THEN DOut_zd(7 downto 0) <= to_slv(CFI_array(Addr) ,8); ELSE ASSERT FALSE REPORT "Invalid CFI query address" SEVERITY warning; END IF; END IF; WHEN ESP_A0SEEN => IF falling_edge(write) THEN BankPROGRAM := BankID; ESP_ACT <= '1'; PSTART <= '1', '0' AFTER 1 ns; WData(0) := -1; WData(1) := -1; IF Viol = '0' THEN WData(0) := DataLo; WData(1) := DataHi; END IF; WAddr(0) := Address; SA <= SecAddr; temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); IF CIOFNeg = '1' THEN WAddr(1) := WAddr(0) + 1; ELSE WAddr(1) := -1; END IF; END IF; WHEN ESP_AS => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN -- resret ULBYPASS ULBYPASS <= '0'; END IF; ELSIF oe THEN IF BankID = BankASEL THEN IF CIOFNeg = '1' THEN IF Address = 0 THEN DOut_zd(15 downto 8) <= to_slv(0,8); ELSIF Addr = 1 THEN DOut_zd(15 downto 8) <= to_slv(16#22#,8); ELSIF Addr = 2 THEN DOut_zd(15 downto 8) <= to_slv(0,8); ELSIF Addr = 3 THEN DOut_zd(15 downto 8) <= to_slv(0,8); END IF; ELSE DOut_zd(15 downto 8) <= "ZZZZZZZZ"; END IF; IF Addr = 0 THEN DOut_zd(7 downto 0) <= to_slv(1,8); ELSIF Addr = 1 THEN DOut_zd(7 downto 0) <= READAS(top_bottom); ELSIF Addr = 2 THEN DOut_zd(7 downto 1) <= to_slv(0,7); DOut_zd(0) <= Sec_Prot(SecAddr); ELSIF Addr = 3 THEN DOut_zd(7 downto 0) <= to_slv(2,8); DOut_zd(7) <= FactoryProt; END IF; ELSE DOut_zd(7 downto 0) <= READMEM(Mem(SecAddr)(Address)); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= READMEM(Mem(SecAddr)(Address + 1)); END IF; END IF; END IF; WHEN PGMS => IF oe THEN ----------------------------------------------------------- --read status ----------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle Status(1) := '0'; IF BankID = BankPROGRAM THEN DOut_zd(7 downto 0) <= Status; ELSIF BankID /= BankPROGRAM AND ESP_ACT = '1' AND BusyBankE(BankERASE,BankID) AND Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); DOut_zd(7 downto 0) <= Status; ELSE DOut_zd(7 downto 0) <= READMEM(Mem(SecAddr)(Address)); IF CIOFNeg = '1' THEN DOut_zd(15 downto 8) <= READMEM(Mem(SecAddr)(Address + 1)); END IF; END IF; END IF; IF PERR /= '1' THEN wr_cnt := 0; IF CIOFNeg = '1' THEN wr_cnt := 1; END IF; FOR i IN wr_cnt downto 0 LOOP new_int := WData(i); IF WAddr(i) < 0 THEN old_int := -1; ELSIF OTP_ACT /= '1' THEN --mem write old_int := Mem(SA)(WAddr(i)); ELSE old_int := SecSi(WAddr(i)); END IF; IF new_int > -1 THEN new_bit := to_slv(new_int,8); IF old_int > -1 THEN old_bit := to_slv(old_int,8); FOR j IN 0 TO 7 LOOP IF old_bit(j) = '0' THEN new_bit(j) := '0'; END IF; END LOOP; new_int := to_nat(new_bit); END IF; WData(i) := new_int; ELSE WData(i) := -1; END IF; END LOOP; FOR i IN wr_cnt downto 0 LOOP IF WAddr(i) > -1 THEN IF OTP_ACT /= '1' THEN --mem write Mem(SA)(WAddr(i)) := -1; ELSE --SecSi write SecSi(WAddr(i)) := -1; END IF; END IF; END LOOP; IF HANG /= '1' AND PDONE = '1' AND (NOT PERR'EVENT) THEN FOR i IN wr_cnt downto 0 LOOP IF WAddr(i) > -1 THEN IF OTP_ACT /= '1' THEN --mem write Mem(SA)(WAddr(i)) := WData(i); ELSE --SecSi write SecSi(WAddr(i)) := WData(i); END IF; END IF; WData(i) := -1; END LOOP; END IF; END IF; --busy signal active RY_zd <= '0'; END CASE; END IF; --Output Disable Control IF ((gOE_n = '1') OR (RESETNeg = '0'AND RST = '0')) THEN DOut_zd <= (OTHERS => 'Z'); ELSE IF CIOFNeg = '0' THEN DOut_zd(15 downto 8) <= (OTHERS =>'Z'); END IF; END IF; ------------------------------------------------------------------------------- -- File Read Section ------------------------------------------------------------------------------- IF NOW = 0 ns THEN BankE(BankERASE, BankID, false); IF TimingModel(12) = 'T' THEN top_bottom := 1; ELSE top_bottom := 0; END IF; ----------------------------------------------------------------------- --CFI array data ----------------------------------------------------------------------- --CFI query identification string CFI_array(16#10#) := 16#51#; CFI_array(16#11#) := 16#52#; CFI_array(16#12#) := 16#59#; CFI_array(16#13#) := 16#02#; CFI_array(16#14#) := 16#00#; CFI_array(16#15#) := 16#40#; CFI_array(16#16#) := 16#00#; CFI_array(16#17#) := 16#00#; CFI_array(16#18#) := 16#00#; CFI_array(16#19#) := 16#00#; CFI_array(16#1A#) := 16#00#; --system interface string CFI_array(16#1B#) := 16#27#; CFI_array(16#1C#) := 16#36#; CFI_array(16#1D#) := 16#00#; CFI_array(16#1E#) := 16#00#; CFI_array(16#1F#) := 16#04#; CFI_array(16#20#) := 16#00#; CFI_array(16#21#) := 16#0A#; CFI_array(16#22#) := 16#00#; CFI_array(16#23#) := 16#05#; CFI_array(16#24#) := 16#00#; CFI_array(16#25#) := 16#04#; CFI_array(16#26#) := 16#00#; --device geometry definition CFI_array(16#27#) := 16#16#; CFI_array(16#28#) := 16#02#; CFI_array(16#29#) := 16#00#; CFI_array(16#2A#) := 16#00#; CFI_array(16#2B#) := 16#00#; CFI_array(16#2C#) := 16#02#; CFI_array(16#2D#) := 16#07#; CFI_array(16#2E#) := 16#00#; CFI_array(16#2F#) := 16#20#; CFI_array(16#30#) := 16#00#; CFI_array(16#31#) := 16#3E#; CFI_array(16#32#) := 16#00#; CFI_array(16#33#) := 16#00#; CFI_array(16#34#) := 16#01#; CFI_array(16#35#) := 16#00#; CFI_array(16#36#) := 16#00#; CFI_array(16#37#) := 16#00#; CFI_array(16#38#) := 16#00#; CFI_array(16#39#) := 16#00#; CFI_array(16#3A#) := 16#00#; CFI_array(16#3B#) := 16#00#; CFI_array(16#3C#) := 16#00#; --primary vendor-specific extended query CFI_array(16#40#) := 16#50#; CFI_array(16#41#) := 16#52#; CFI_array(16#42#) := 16#49#; CFI_array(16#43#) := 16#31#; CFI_array(16#44#) := 16#33#; CFI_array(16#45#) := 16#04#; CFI_array(16#46#) := 16#02#; CFI_array(16#47#) := 16#01#; CFI_array(16#48#) := 16#01#; CFI_array(16#49#) := 16#04#; CFI_array(16#4A#) := 16#20#; CFI_array(16#4B#) := 16#00#; CFI_array(16#4C#) := 16#00#; CFI_array(16#4D#) := 16#85#; CFI_array(16#4E#) := 16#95#; IF TimingModel(12) = 'T' THEN CFI_array(16#4F#) := 16#03#;--top boot ELSE CFI_array(16#4F#) := 16#02#; END IF; ------------------------------------------------------------------------------- -----am41dl3244g sector protection preload file format------- ------------------ ------------------------------------------------------------------------------- -- / - comment -- @aaa - stands for sector address -- b - is 1 for protected sector , 0 for unprotect. -- If > SecNum SecSi is protected/unprotected -- only first 1-4 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- IF (prot_file_name /= "none" AND UserPreload ) THEN ind := 0; FactoryProt <= '0'; Sec_Prot := (OTHERS => '0'); WHILE (not ENDFILE (prot_file)) LOOP READLINE (prot_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 4)); --address ELSE IF ind > SecNum THEN --SecSi Factory protect preload IF buf(1) = '1' THEN FactoryProt <= '1'; END IF; ELSE -- Standard Sector prload IF buf(1) = '1' THEN Sec_Prot(ind) := '1'; END IF; ind := ind + 1; END IF; END IF; END LOOP; END IF; ------------------------------------------------------------------------------- -----am41dl3244g SecSi preload file format------------------------------------- ------------------------------------------------------------------------------- -- / - comment -- @aa - stands for address within sector -- dd -
is byte to be written at SecSi(aa++) -- (aa is incremented at every load) -- only first 1-3 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- IF (SecSi_file_name /= "none" AND UserPreload ) THEN SecSi := (OTHERS => MaxData); ind := 0; WHILE (not ENDFILE (SecSi_file)) LOOP READLINE (SecSi_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 3)); --address ELSE IF ind <= SecSiSize THEN SecSi(ind) := h(buf(1 TO 2)); ind := ind + 1; END IF; END IF; END LOOP; END IF; ------------------------------------------------------------------------------- -----am41dl3244g memory preload file format ----------------------------------- ------------------------------------------------------------------------------- -- / - comment -- @aaaaaa - stands for address within sector -- dd -
is byte to be written at Mem(*)(aaaaaa++) -- (aaaaaa is incremented at every load) -- only first 1-7 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- IF (mem_file_name /= "none" AND UserPreload ) THEN ind := 0; Mem := (OTHERS => (OTHERS => MaxData)); WHILE (not ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 7)); --address ELSE SECT := ReturnSectorID1(ind,top_bottom); ADDRHILO(AddrLO,AddrHi,SECT,top_bottom); Addr_ind := ind - AddrLO; IF Addr_ind <= SecSize THEN Mem(SECT)(Addr_ind) := h(buf(1 to 2)); ind := ind + 1; END IF; END IF; END LOOP; END IF; END IF; END PROCESS Functional; DOutPassThrough : PROCESS(DOut_zd) VARIABLE ValidData : std_logic_vector(15 downto 0); VARIABLE CEDQ_t : TIME; VARIABLE OEDQ_t : TIME; VARIABLE ADDRDQ_t : TIME; BEGIN IF DOut_zd(0) /= 'Z' THEN OPENLATCH := TRUE; CEDQ_t := -CENeg'LAST_EVENT + tpd_CENeg_DQ0(trz0); OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_DQ0(trz0); ADDRDQ_t := -A'LAST_EVENT + tpd_A0_DQ0(tr01);-- IF ( CIOFNeg = '0' ) AND (DIn(15)'LAST_EVENT < A'LAST_EVENT) THEN ADDRDQ_t := -DIn(15)'LAST_EVENT + tpd_A0_DQ0(tr01);-- END IF; FROMOE := (OEDQ_t >= CEDQ_t) AND (OEDQ_t > 0 ns); FROMCE := (CEDQ_t > OEDQ_t) AND (CEDQ_t > 0 ns); IF CIOFNeg = '0' THEN ValidData := "ZZZZZZZZXXXXXXXX"; ELSE ValidData := "XXXXXXXXXXXXXXXX"; END IF; IF ((ADDRDQ_t > 0 ns) AND (((ADDRDQ_t > CEDQ_t) AND FROMCE) OR ((ADDRDQ_t > OEDQ_t) AND FROMOE))) THEN DOut_Pass <= ValidData, DOut_zd AFTER ADDRDQ_t; ELSE DOut_Pass <= DOut_zd; END IF; ELSE OPENLATCH := FALSE; DOut_Pass <= DOut_zd; END IF; END PROCESS DOutPassThrough; ----------------------------------------------------------------------- -- Path Delay Section ----------------------------------------------------------------------- RY_OUT: PROCESS(RY_zd) VARIABLE RY_GlitchData : VitalGlitchDataType; VARIABLE RY_DATA : std_logic; BEGIN IF RY_zd = '1' THEN RY_DATA := 'Z'; ELSE RY_DATA := '0'; END IF; VitalPathDelay01Z( OutSignal => RY, OutSignalName => "RY/BY#", OutTemp => RY_DATA, Mode => VitalTransport, GlitchData => RY_GlitchData, Paths => ( 0 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_WENeg_RY, PathCondition => TRUE), 1 => (InputChangeTime => WENeg'LAST_EVENT, PathDelay => tpd_WENeg_RY, PathCondition => TRUE), 2 => (InputChangeTime => READY'LAST_EVENT, PathDelay => VitalZeroDelay01Z, PathCondition => EDONE = '1'), 3 => (InputChangeTime => EDONE'LAST_EVENT, PathDelay => VitalZeroDelay01Z, PathCondition => EDONE = '1'), 4 => (InputChangeTime => PDONE'LAST_EVENT, PathDelay => VitalZeroDelay01Z, PathCondition => PDONE = '1') ) ); END PROCESS RY_Out; --------------------------------------------------------------------------- -- Path Delay Section for DOut signal --------------------------------------------------------------------------- D_Out_PathDelay_Gen : FOR i IN 0 TO 7 GENERATE --Dout_zd'RANGE GENERATE PROCESS(DOut_Pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_Pass(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_DQ0, PathCondition => (NOT OPENLATCH OR (OPENLATCH AND FROMCE))), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ0, PathCondition => (NOT OPENLATCH OR (OPENLATCH AND FROMOE))), 2 => (InputChangeTime => A'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => true), 3 => (InputChangeTime => Din(15)'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => CIOFNeg='0'), 4 => (InputChangeTime => CIOFNeg'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CIOFNeg_DQ15), PathCondition => CIOFNeg = '1'), 5 => (InputChangeTime => RESETNeg'LAST_EVENT, PathDelay => tpd_RESETNeg_DQ0, PathCondition => RESETNeg='0') ) ); END PROCESS; END GENERATE D_Out_PathDelay_Gen; --------------------------------------------------------------------------- -- Path Delay Section for DOut signal --------------------------------------------------------------------------- D_Out_15_7_PathDelay_Gen : FOR i IN 8 TO 15 GENERATE PROCESS(DOut_Pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_Pass(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_DQ0, PathCondition => (NOT OPENLATCH OR (OPENLATCH AND FROMCE))), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ0, PathCondition => (NOT OPENLATCH OR (OPENLATCH AND FROMOE))), 2 => (InputChangeTime => A'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => true), 3 => (InputChangeTime => Din(15)'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => CIOFNeg='0'), 4 => (InputChangeTime => CIOFNeg'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CIOFNeg_DQ15), PathCondition => CIOFNeg = '1'), 5 => (InputChangeTime => RESETNeg'LAST_EVENT, PathDelay => tpd_RESETNeg_DQ0, PathCondition => RESETNeg='0'), 6 => (InputChangeTime => CIOFNeg'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CIOFNeg_DQ15), PathCondition => CIOFNeg = '0') ) ); END PROCESS; END GENERATE D_Out_15_7_PathDelay_Gen; END BLOCK behavior; END vhdl_behavioral; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY SRAM4M IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; --address tipd_A10 : VitalDelayType01 := VitalZeroDelay01; --lines tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_CIOSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SA : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_UBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE2 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A0_DQ1 : VitalDelayType01 := UnitDelay01;--SRAM tpd_CE1Neg_DQ0 : VitalDelayType01Z := UnitDelay01Z;--SRAM tpd_OENeg_DQ1 : VitalDelayType01Z := UnitDelay01Z;--SRAM tpd_LBNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --tsetup values tsetup_A0_WENeg : VitalDelayType := UnitDelay; --tAS edge \ sram tsetup_DQ0_WENeg : VitalDelayType := UnitDelay; --tDH edge / --thold values thold_A0_WENeg : VitalDelayType := UnitDelay; thold_DQ0_WENeg : VitalDelayType := UnitDelay; --tDH edge / --tpw values: pulse width tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP tpw_CE1Neg_negedge : VitalDelayType := UnitDelay; --tCW tpw_LBNeg_negedge : VitalDelayType := UnitDelay; --tBW tpw_A0_negedge : VitalDelayType := UnitDelay; --tWC tRC -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded sram_file_name : STRING := "none";--"am41dl3244g_sram.mem"; UserPreload : BOOLEAN := FALSE; --TRUE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A17 : IN std_ulogic := 'U'; -- A16 : IN std_ulogic := 'U'; -- A15 : IN std_ulogic := 'U'; -- A14 : IN std_ulogic := 'U'; -- A13 : IN std_ulogic := 'U'; --address A12 : IN std_ulogic := 'U'; --lines A11 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A8 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- A6 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A1 : IN std_ulogic := 'U'; -- A0 : IN std_ulogic := 'U'; -- DQ15 : INOUT std_ulogic := 'U'; -- DQ14 : INOUT std_ulogic := 'U'; -- DQ13 : INOUT std_ulogic := 'U'; -- DQ12 : INOUT std_ulogic := 'U'; -- DQ11 : INOUT std_ulogic := 'U'; -- DQ10 : INOUT std_ulogic := 'U'; -- DQ9 : INOUT std_ulogic := 'U'; -- data DQ8 : INOUT std_ulogic := 'U'; -- lines DQ7 : INOUT std_ulogic := 'U'; -- DQ6 : INOUT std_ulogic := 'U'; -- DQ5 : INOUT std_ulogic := 'U'; -- DQ4 : INOUT std_ulogic := 'U'; -- DQ3 : INOUT std_ulogic := 'U'; -- DQ2 : INOUT std_ulogic := 'U'; -- DQ1 : INOUT std_ulogic := 'U'; -- DQ0 : INOUT std_ulogic := 'U'; -- CIOSNeg : IN std_ulogic := 'U'; SA : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; LBNeg : IN std_ulogic := 'U'; UBNeg : IN std_ulogic := 'U'; CE1Neg : IN std_ulogic := 'U'; CE2 : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of SRAM4M : ENTITY IS TRUE; END SRAM4M; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of SRAM4M IS ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT HiAddrBit : NATURAL := 17; CONSTANT MaxData : NATURAL := 524287; CONSTANT PartID : STRING := "SRAM4M"; -- interconnect path delay signals SIGNAL A17_ipd : std_ulogic := 'U'; SIGNAL A16_ipd : std_ulogic := 'U'; SIGNAL A15_ipd : std_ulogic := 'U'; SIGNAL A14_ipd : std_ulogic := 'U'; SIGNAL A13_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL SA_ipd : std_ulogic := 'U'; SIGNAL CIOSNeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL UBNeg_ipd : std_ulogic := 'U'; SIGNAL LBNeg_ipd : std_ulogic := 'U'; SIGNAL CE1Neg_ipd : std_ulogic := 'U'; SIGNAL CE2_ipd : std_ulogic := 'U'; BEGIN --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_0 : VitalWireDelay (A17_ipd, A17, tipd_A17); w_1 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_2 : VitalWireDelay (A15_ipd, A15, tipd_A15); w_3 : VitalWireDelay (A14_ipd, A14, tipd_A14); w_4 : VitalWireDelay (A13_ipd, A13, tipd_A13); w_5 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_6 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_7 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_8 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_9 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_10 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_11 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_12 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_13 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_14 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_15 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_16 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_17 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_18 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15); w_19 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14); w_20 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13); w_21 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12); w_22 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11); w_23 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10); w_24 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9); w_25 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8); w_26 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7); w_27 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6); w_28 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5); w_29 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4); w_30 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_31 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_32 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_33 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_34 : VitalWireDelay (SA_ipd, SA, tipd_SA); w_35 : VitalWireDelay (CIOSNeg_ipd, CIOSNeg, tipd_CIOSNeg); w_36 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_37 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_38 : VitalWireDelay (UBNeg_ipd, UBNeg, tipd_UBNeg); w_39 : VitalWireDelay (LBNeg_ipd, LBNeg, tipd_LBNeg); w_40 : VitalWireDelay (CE1Neg_ipd, CE1Neg, tipd_CE1Neg); w_41 : VitalWireDelay (CE2_ipd, CE2, tipd_CE2); END BLOCK; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior: BLOCK PORT ( A : IN std_logic_vector(HiAddrBit downto 0) := (OTHERS => 'U'); DIn : IN std_logic_vector(15 downto 0) := (OTHERS => 'U'); DOut : OUT std_ulogic_vector(15 downto 0) := (OTHERS => 'Z'); SA : IN std_ulogic := 'U'; CIOSNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; LBNeg : IN std_ulogic := 'U'; UBNeg : IN std_ulogic := 'U'; CE1Neg : IN std_ulogic := 'U'; CE2 : IN std_ulogic := 'U' ); PORT MAP ( A(17) => A17_ipd, A(16) => A16_ipd, A(15) => A15_ipd, A(14) => A14_ipd, A(13) => A13_ipd, A(12) => A12_ipd, A(11) => A11_ipd, A(10) => A10_ipd, A(9) => A9_ipd, A(8) => A8_ipd, A(7) => A7_ipd, A(6) => A6_ipd, A(5) => A5_ipd, A(4) => A4_ipd, A(3) => A3_ipd, A(2) => A2_ipd, A(1) => A1_ipd, A(0) => A0_ipd, DIn(15) => DQ15_ipd, DIn(14) => DQ14_ipd, DIn(13) => DQ13_ipd, DIn(12) => DQ12_ipd, DIn(11) => DQ11_ipd, DIn(10) => DQ10_ipd, DIn(9) => DQ9_ipd, DIn(8) => DQ8_ipd, DIn(7) => DQ7_ipd, DIn(6) => DQ6_ipd, DIn(5) => DQ5_ipd, DIn(4) => DQ4_ipd, DIn(3) => DQ3_ipd, DIn(2) => DQ2_ipd, DIn(1) => DQ1_ipd, DIn(0) => DQ0_ipd, DOut(15) => DQ15, DOut(14) => DQ14, DOut(13) => DQ13, DOut(12) => DQ12, DOut(11) => DQ11, DOut(10) => DQ10, DOut(9) => DQ9, DOut(8) => DQ8, DOut(7) => DQ7, DOut(6) => DQ6, DOut(5) => DQ5, DOut(4) => DQ4, DOut(3) => DQ3, DOut(2) => DQ2, DOut(1) => DQ1, DOut(0) => DQ0, SA => SA_ipd, CIOSNeg => CIOSNeg_ipd, OENeg => OENeg_ipd, WENeg => WENeg_ipd, LBNeg => LBNeg_ipd, UBNeg => UBNeg_ipd, CE1Neg => CE1Neg_ipd, CE2 => CE2_ipd ); -- SRAM Memory array declaration TYPE MemStore IS ARRAY (0 to MaxData) OF INTEGER RANGE -2 TO 511; SHARED VARIABLE MemDataA : MemStore :=(OTHERS=> 255); SHARED VARIABLE MemDataB : MemStore :=(OTHERS=> 255); --zero delay signals SIGNAL DOut_zd : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL DOut_Pass : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL writeSRAM : std_logic := '0'; SIGNAL readSRAM : std_logic := '0'; SIGNAL Pmode : std_logic := '0'; SIGNAL UB : std_logic := '0'; SIGNAL LB : std_logic := '0'; -- Access time variables SHARED VARIABLE OPENLATCH : BOOLEAN; SHARED VARIABLE FROMOE : BOOLEAN; SHARED VARIABLE FROMCE1 : BOOLEAN; SHARED VARIABLE FROMLB : BOOLEAN; SHARED VARIABLE FROMUB : BOOLEAN; -- timing check violation SIGNAL Viol : X01 := '0'; BEGIN --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS(A, Din, OENeg, WENeg, CE1Neg, CE2, UBNeg, LBNeg) -- Timing Check Variables VARIABLE Tviol_A0_WENegsram : X01 := '0'; VARIABLE TD_A0_WENegsram : VitalTimingDataType; VARIABLE Tviol_A0_WENegsrm : X01 := '0'; VARIABLE TD_A0_WENegsrm : VitalTimingDataType; VARIABLE Tviol_A0_CE1Neg : X01 := '0'; VARIABLE TD_A0_CE1Neg : VitalTimingDataType; VARIABLE Tviol_A0_LBNeg : X01 := '0'; VARIABLE TD_A0_LBNeg : VitalTimingDataType; VARIABLE Tviol_A0_UBNeg : X01 := '0'; VARIABLE TD_A0_UBNeg : VitalTimingDataType; VARIABLE Tviol_DQ0_WENegsram : X01 := '0'; VARIABLE TD_DQ0_WENegsram : VitalTimingDataType; VARIABLE Tviol_DQ0_CE1Neg : X01 := '0'; VARIABLE TD_DQ0_CE1Neg : VitalTimingDataType; VARIABLE Tviol_DQ0_UBNeg : X01 := '0'; VARIABLE TD_DQ0_UBNeg : VitalTimingDataType; VARIABLE Tviol_DQ0_LBNeg : X01 := '0'; VARIABLE TD_DQ0_LBNeg : VitalTimingDataType; VARIABLE Pviol_CE1Neg : X01 := '0'; VARIABLE PD_CE1Neg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_UBNeg : X01 := '0'; VARIABLE PD_UBNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_LBNeg : X01 := '0'; VARIABLE PD_LBNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENegsram : X01 := '0'; VARIABLE PD_WENegsram : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A0 : X01 := '0'; VARIABLE PD_A0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN --------------------------------------------------------------------------- -- Timing Check Section --------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Setup Check between A and WENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => tsetup_A0_WENeg, SetupLow => tsetup_A0_WENeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_WENegsram, Violation => Tviol_A0_WENegsram ); -- Hold Check between A and WENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => thold_A0_WENeg, SetupLow => thold_A0_WENeg, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_WENegsrm, Violation => Tviol_A0_WENegsrm ); -- Setup Check between A and CE1Neg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => CE1Neg, RefSignalName => "CE1#", SetupHigh => tsetup_A0_WENeg, SetupLow => tsetup_A0_WENeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CE1Neg, Violation => Tviol_A0_CE1Neg ); -- Setup Check between A and LBNeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => LBNeg, RefSignalName => "LB#", SetupHigh => tsetup_A0_WENeg, SetupLow => tsetup_A0_WENeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_LBNeg, Violation => Tviol_A0_LBNeg ); -- Setup Check between A and UBNeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => UBNeg, RefSignalName => "LB#", SetupHigh => tsetup_A0_WENeg, SetupLow => tsetup_A0_WENeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_UBNeg, Violation => Tviol_A0_UBNeg ); -- Setup/Hold Check between DQ and WENeg, SRAM VitalSetupHoldCheck ( TestSignal => DQ0, TestSignalName => "DQ", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => tsetup_DQ0_WENeg, SetupLow => tsetup_DQ0_WENeg, HoldHigh => thold_DQ0_WENeg, HoldLow => thold_DQ0_WENeg, CheckEnabled => (DIn(14 downto 0) /= DOut_zd(14 downto 0)), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_WENegsram, Violation => Tviol_DQ0_WENegsram ); -- Setup/Hold Check between DQ and CE1Neg VitalSetupHoldCheck ( TestSignal => DQ0, TestSignalName => "DQ", RefSignal => CE1Neg, RefSignalName => "CE1#", SetupHigh => tsetup_DQ0_WENeg, SetupLow => tsetup_DQ0_WENeg, HoldHigh => thold_DQ0_WENeg, HoldLow => thold_DQ0_WENeg, CheckEnabled => (DIn(14 downto 0) /= DOut_zd(14 downto 0)), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_CE1Neg, Violation => Tviol_DQ0_CE1Neg ); -- Setup/Hold Check between DQ and UBNeg VitalSetupHoldCheck ( TestSignal => DQ0, TestSignalName => "DQ", RefSignal => UBNeg, RefSignalName => "UB#", SetupHigh => tsetup_DQ0_WENeg, SetupLow => tsetup_DQ0_WENeg, HoldHigh => thold_DQ0_WENeg, HoldLow => thold_DQ0_WENeg, CheckEnabled => (DIn(14 downto 0) /= DOut_zd(14 downto 0)), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_UBNeg, Violation => Tviol_DQ0_UBNeg ); -- Setup/Hold Check between DQ and LBNeg VitalSetupHoldCheck ( TestSignal => DQ0, TestSignalName => "DQ", RefSignal => LBNeg, RefSignalName => "LB#", SetupHigh => tsetup_DQ0_WENeg, SetupLow => tsetup_DQ0_WENeg, HoldHigh => thold_DQ0_WENeg, HoldLow => thold_DQ0_WENeg, CheckEnabled => (DIn(14 downto 0) /= DOut_zd(14 downto 0)), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_LBNeg, Violation => Tviol_DQ0_LBNeg ); -- PulseWidth Check for WENeg, SRAM VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WE#", PulseWidthLow => tpw_WENeg_negedge, CheckEnabled => CE2 = '1' AND CE1Neg = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_WENegsram, Violation => Pviol_WENegsram ); -- PulseWidth Check for CE1Neg VitalPeriodPulseCheck ( TestSignal => CE1Neg, TestSignalName => "CE1#", PulseWidthLow => tpw_CE1Neg_negedge, CheckEnabled => true, HeaderMsg => InstancePath & PartID, PeriodData => PD_CE1Neg, Violation => Pviol_CE1Neg ); -- PulseWidth Check for LBNeg VitalPeriodPulseCheck ( TestSignal => LBNeg, TestSignalName => "LB#", PulseWidthLow => tpw_LBNeg_negedge, CheckEnabled => true, HeaderMsg => InstancePath & PartID, PeriodData => PD_LBNeg, Violation => Pviol_LBNeg ); -- PulseWidth Check for UBNeg VitalPeriodPulseCheck ( TestSignal => UBNeg, TestSignalName => "UB#", PulseWidthLow => tpw_LBNeg_negedge, CheckEnabled => true, HeaderMsg => InstancePath & PartID, PeriodData => PD_UBNeg, Violation => Pviol_UBNeg ); -- PulseWidth Check for A VitalPeriodPulseCheck ( TestSignal => A(0), TestSignalName => "A", PulseWidthHigh => tpw_A0_negedge, PulseWidthLow => tpw_A0_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_A0, Violation => Pviol_A0 ); Violation := Tviol_A0_WENegsram OR Tviol_A0_WENegsrm OR Tviol_A0_CE1Neg OR Tviol_A0_LBNeg OR Tviol_A0_UBNeg OR Tviol_DQ0_WENegsram OR Tviol_DQ0_CE1Neg OR Tviol_DQ0_UBNeg OR Tviol_DQ0_LBNeg OR Pviol_CE1Neg OR Pviol_UBNeg OR Pviol_LBNeg OR Pviol_WENegsram OR Pviol_A0 ; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS VITALTimingCheck; BusCycleDecode : PROCESS(A, Din, WENeg, OENeg, CE1Neg, CE2, LBNeg, UBNeg) BEGIN IF CE2 = '1' THEN IF WENeg = '1' AND --readsram_en = true CE1Neg = '0' AND OENeg = '0' THEN readSRAM <= '1'; ELSE readSRAM <= '0'; END IF; IF (WENeg = '0' AND CE1Neg = '0' AND rising_edge(UBNeg) AND CIOSNeg = '1') OR (WENeg = '0' AND CE1Neg = '0' AND rising_edge(LBNeg) AND CIOSNeg = '1') OR (CE1Neg = '0' AND rising_edge(WENeg)) OR (WENeg = '0' AND rising_edge(CE1Neg)) THEN writeSRAM <= '0'; IF rising_edge(UBNeg) OR UBNeg = '0' THEN UB <= '0'; ELSE UB <= '1'; END IF; IF rising_edge(LBNeg) OR LBNeg = '0' THEN LB <= '0'; ELSE LB <= '1'; END IF; ELSIF WENeg = '0' AND CE1Neg = '0' THEN writeSRAM <= '1'; END IF; END IF; END PROCESS BusCycleDecode; ------------------------------------------------------------------------------- -- Behavior Process ------------------------------------------------------------------------------- Behavior : PROCESS( A, readSRAM, writeSRAM, LBNeg, UBNeg, CIOSNeg, SA) VARIABLE MemAddr : NATURAL RANGE 0 TO MaxData; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- --read SRAM IF rising_edge(readSRAM) OR (readSRAM = '1' AND A'EVENT) OR (readSRAM = '1' AND SA'EVENT AND CIOSNeg = '0') OR (readSRAM = '1' AND CIOSNeg'EVENT) OR (readSRAM = '1' AND falling_edge(LBNeg) AND CIOSNeg = '1') OR (readSRAM = '1' AND falling_edge(UBNeg) AND CIOSNeg = '1') THEN IF CIOSNeg = '1' THEN MemAddr := to_nat(A); ELSE MemAddr := to_nat(SA & A); END IF; IF (LBNeg = '0' AND CIOSNeg = '1') OR CIOSNeg = '0' THEN DOut_zd(7 downto 0) <= (others => 'X'); IF MemDataA(MemAddr) /= -1 THEN DOut_zd(7 downto 0) <= to_slv(MemDataA(MemAddr),8); END IF; END IF; IF (UBNeg = '0' AND CIOSNeg = '1') THEN DOut_zd(15 downto 8) <= (others => 'X'); IF MemDataB(MemAddr) /= -1 THEN DOut_zd(15 downto 8) <= to_slv(MemDataB(MemAddr),8); END IF; END IF; END IF; --write SRAM IF falling_edge(writeSRAM) THEN IF CIOSNeg = '1' THEN MemAddr := to_nat(A); ELSE MemAddr := to_nat(SA & A); END IF; IF (LB = '0' AND CIOSNeg = '1') OR CIOSNeg = '0' THEN MemDataA(MemAddr) := -1; IF Viol /= 'X' THEN MemDataA(MemAddr) := to_nat(DIn(7 downto 0)); END IF; END IF; IF (UB = '0'AND CIOSNeg = '1') THEN MemDataB(MemAddr) := -1; IF Viol /= 'X' THEN MemDataB(MemAddr) := to_nat(DIn(15 downto 8)); END IF; END IF; END IF; --Output Disable Control IF OENeg = '1' THEN DOut_zd <= (OTHERS => 'Z'); ELSE IF UBNeg = '1' AND CIOSNeg = '1' THEN DOut_zd(15 downto 8) <= (OTHERS =>'Z'); END IF; IF LBNeg = '1' AND CIOSNeg = '1' THEN DOut_zd(7 downto 0) <= (OTHERS =>'Z'); END IF; IF CIOSNeg = '0' THEN DOut_zd(15 downto 8) <= (OTHERS =>'Z'); END IF; END IF; END PROCESS Behavior; ------------------------------------------------------------------------------- -- File Read Section ------------------------------------------------------------------------------- Preloadfile: PROCESS FILE sram_file : text is sram_file_name; VARIABLE ind : NATURAL := 0; VARIABLE buf : line; BEGIN ------------------------------------------------------------------------------- -----am41dl3244g sram memory preload file format ------------------------------ ------------------------------------------------------------------------------- -- / - comment -- @aaaa - stands for address -- db - is byte to be written at MemDataA(*)(aaaa++) -- is byte to be written at MemDataB(*)(aaaa++) -- (aaaa is incremented at every load) -- only first 1-5 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- IF (sram_file_name /= "none" AND UserPreload ) THEN ind := 0; WHILE (not ENDFILE (sram_file)) LOOP READLINE (sram_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 5)); --address ELSE MemDataA(ind) := h(buf(1 to 2)); MemDataB(ind) := h(buf(3 to 4)); ind := ind + 1; END IF; END LOOP; END IF; WAIT; END PROCESS Preloadfile; DOutPassThrough : PROCESS(DOut_zd) VARIABLE ValidData : std_logic_vector(15 downto 0); VARIABLE CE1DQ_t : TIME; VARIABLE OEDQ_t : TIME; VARIABLE ADDRDQ_t : TIME; VARIABLE LBDQ_t : TIME; VARIABLE UBDQ_t : TIME; BEGIN IF (DOut_zd(8) /= 'Z' OR DOut_zd(0) /= 'Z') THEN OPENLATCH := TRUE; CE1DQ_t := -CE1Neg'LAST_EVENT + tpd_CE1Neg_DQ0(trz0); OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_DQ1(trz0); LBDQ_t := -LBNeg'LAST_EVENT + tpd_LBNeg_DQ0(trz0); UBDQ_t := -UBNeg'LAST_EVENT + tpd_LBNeg_DQ0(trz0); ADDRDQ_t := -A'LAST_EVENT + tpd_A0_DQ1(tr01);-- IF ( CIOSNeg = '0' ) AND (SA'LAST_EVENT < A'LAST_EVENT) THEN ADDRDQ_t := -SA'LAST_EVENT + tpd_A0_DQ1(tr01);-- END IF; FROMOE := (OEDQ_t >= CE1DQ_t AND OEDQ_t >= LBDQ_t AND OEDQ_t >= UBDQ_t) AND (OEDQ_t > 0 ns); FROMCE1 := (CE1DQ_t > OEDQ_t AND CE1DQ_t > LBDQ_t AND CE1DQ_t > UBDQ_t)AND (CE1DQ_t > 0 ns); FROMLB := (LBDQ_t > OEDQ_t AND LBDQ_t >= CE1DQ_t) AND (LBDQ_t > 0 ns) AND CIOSNeg = '1'; FROMUB := (UBDQ_t > OEDQ_t AND UBDQ_t >= CE1DQ_t) AND (UBDQ_t > 0 ns) AND CIOSNeg = '1'; IF CIOSNeg = '1' THEN IF LBNeg = '0' THEN ValidData(7 downto 0) := "XXXXXXXX"; END IF; IF UBNeg = '0' THEN ValidData(15 downto 8) := "XXXXXXXX"; END IF; ELSE ValidData := "ZZZZZZZZXXXXXXXX"; END IF; IF ((ADDRDQ_t > 0 ns) AND (((ADDRDQ_t > CE1DQ_t) AND FROMCE1) OR ((ADDRDQ_t > OEDQ_t) AND FROMOE) OR ((ADDRDQ_t > LBDQ_t) AND FROMLB) OR ((ADDRDQ_t > UBDQ_t) AND FROMUB))) THEN DOut_Pass <= ValidData, DOut_zd AFTER ADDRDQ_t; ELSE DOut_Pass <= DOut_zd; END IF; ELSE OPENLATCH := FALSE; DOut_Pass <= DOut_zd; END IF; END PROCESS DOutPassThrough; ----------------------------------------------------------------------- -- Path Delay Section ----------------------------------------------------------------------- D_Out_PathDelay_Gen : FOR i IN 0 TO 7 GENERATE --Dout_zd'RANGE GENERATE PROCESS(DOut_Pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_Pass(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => CE1Neg'LAST_EVENT, PathDelay => tpd_CE1Neg_DQ0, PathCondition => (NOT OPENLATCH OR (OPENLATCH AND FROMCE1))), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ1, PathCondition => (NOT OPENLATCH OR (OPENLATCH AND FROMOE))), 2 => (InputChangeTime => LBNeg'LAST_EVENT, PathDelay => tpd_LBNeg_DQ0, PathCondition => (NOT OPENLATCH OR (OPENLATCH AND FROMLB))), 3 => (InputChangeTime => SA'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ1), PathCondition => CIOSNeg='0'), 4 => (InputChangeTime => A'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ1), PathCondition => true) ) ); END PROCESS; END GENERATE D_Out_PathDelay_Gen; --------------------------------------------------------------------------- -- Path Delay Section for DOut signal --------------------------------------------------------------------------- D_Out_15_7_PathDelay_Gen : FOR i IN 8 TO 15 GENERATE PROCESS(DOut_Pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_Pass(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => CE1Neg'LAST_EVENT, PathDelay => tpd_CE1Neg_DQ0, PathCondition => (NOT OPENLATCH OR (OPENLATCH AND FROMCE1))), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ1, PathCondition => (NOT OPENLATCH OR (OPENLATCH AND FROMOE))), 2 => (InputChangeTime => UBNeg'LAST_EVENT, PathDelay => tpd_LBNeg_DQ0, PathCondition => (NOT OPENLATCH OR (OPENLATCH AND FROMUB))), 3 => (InputChangeTime => A'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ1), PathCondition => true) ) ); END PROCESS; END GENERATE D_Out_15_7_PathDelay_Gen; END BLOCK behavior; END vhdl_behavioral; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of AM41DL3244G IS ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE; COMPONENT Flash32M GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A18 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A19 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A20 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CIOFNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_RESETNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; tpd_A0_DQ0 : VitalDelayType01 := UnitDelay01;--tACC tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tCE,tCE,tDF,-,tDF,-) tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tOE,tOE,tDF,-,tDF,-) tpd_CIOFNeg_DQ15 : VitalDelayType01Z := UnitDelay01Z; tpd_WENeg_RY : VitalDelayType01Z := UnitDelay01Z; --tBUSY --tsetup values tsetup_A0_CENeg : VitalDelayType := UnitDelay; --tAS edge \ tsetup_A0_OENeg : VitalDelayType := UnitDelay; --tASO edge \ tsetup_DQ0_CENeg : VitalDelayType := UnitDelay; --tDS edge / --thold values thold_CENeg_RESETNeg: VitalDelayType := UnitDelay; --tRH edge / thold_OENeg_WENeg : VitalDelayType := UnitDelay; --tOEH edge / thold_A0_CENeg : VitalDelayType := UnitDelay; --tAH edge \ thold_A0_OENeg : VitalDelayType := UnitDelay; --tAHT edge \ thold_DQ0_CENeg : VitalDelayType := UnitDelay; --tDH edge / thold_WENeg_OENeg : VitalDelayType := UnitDelay; --tGHWL edge / thold_CIOFNeg_CENeg : VitalDelayType := UnitDelay; --tELFL edge \ --tpw values: pulse width tpw_RESETNeg_negedge : VitalDelayType := UnitDelay; --tRP tpw_OENeg_posedge : VitalDelayType := UnitDelay; --tOEPH tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP tpw_WENeg_posedge : VitalDelayType := UnitDelay; --tWPH tpw_CENeg_negedge : VitalDelayType := UnitDelay; --tCP tpw_CENeg_posedge : VitalDelayType := UnitDelay; --tCEPH tpw_A0_negedge : VitalDelayType := UnitDelay; --tWC tRC -- tdevice values: values for internal delays --Program Operation tdevice_POB : VitalDelayType := 5 us; --Sector Erase Operation tWHWH2 tdevice_SEO : VitalDelayType := 400 ms; --Timing Limit Exceeded tdevice_HANG : VitalDelayType := 400 ms; --? --program/erase suspend timeout tdevice_START : VitalDelayType := 5 us; --sector erase command sequence timeout tdevice_TCTMOUT : VitalDelayType := 50 us; --device ready after Hardware reset(during embeded algorithm) tdevice_TREADY : VitalDelayType := 20 us; --tReady -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING := "none";--"am41dl3244g.mem"; prot_file_name : STRING := "none";--"am41dl3244g_prot.mem"; secsi_file_name : STRING := "none";--"am41dl3244g_secsi.mem"; UserPreload : BOOLEAN := FALSE; --TRUE; LongTimming : BOOLEAN := TRUE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A20 : IN std_ulogic := 'U'; -- A19 : IN std_ulogic := 'U'; -- A18 : IN std_ulogic := 'U'; -- A17 : IN std_ulogic := 'U'; -- A16 : IN std_ulogic := 'U'; -- A15 : IN std_ulogic := 'U'; -- A14 : IN std_ulogic := 'U'; -- A13 : IN std_ulogic := 'U'; --address A12 : IN std_ulogic := 'U'; --lines A11 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A8 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- A6 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A1 : IN std_ulogic := 'U'; -- A0 : IN std_ulogic := 'U'; -- DQ15 : INOUT std_ulogic := 'U'; -- DQ15/A-1 DQ14 : INOUT std_ulogic := 'U'; -- DQ13 : INOUT std_ulogic := 'U'; -- DQ12 : INOUT std_ulogic := 'U'; -- DQ11 : INOUT std_ulogic := 'U'; -- DQ10 : INOUT std_ulogic := 'U'; -- DQ9 : INOUT std_ulogic := 'U'; -- data DQ8 : INOUT std_ulogic := 'U'; -- lines DQ7 : INOUT std_ulogic := 'U'; -- DQ6 : INOUT std_ulogic := 'U'; -- DQ5 : INOUT std_ulogic := 'U'; -- DQ4 : INOUT std_ulogic := 'U'; -- DQ3 : INOUT std_ulogic := 'U'; -- DQ2 : INOUT std_ulogic := 'U'; -- DQ1 : INOUT std_ulogic := 'U'; -- DQ0 : INOUT std_ulogic := 'U'; -- CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; --WP#/ACC CIOFNeg : IN std_ulogic := 'U'; RY : OUT std_ulogic := 'U' --RY/BY# ); END COMPONENT; COMPONENT SRAM4M GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_SA : VitalDelayType01 := VitalZeroDelay01; tipd_CIOSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_UBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE2 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A0_DQ1 : VitalDelayType01 := UnitDelay01;--SRAM tpd_CE1Neg_DQ0 : VitalDelayType01Z := UnitDelay01Z;--SRAM tpd_OENeg_DQ1 : VitalDelayType01Z := UnitDelay01Z;--SRAM tpd_LBNeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --tsetup values tsetup_A0_WENeg : VitalDelayType := UnitDelay; --tAS edge \ sram tsetup_DQ0_WENeg : VitalDelayType := UnitDelay; --tDH edge / --thold values thold_A0_WENeg : VitalDelayType := UnitDelay; thold_DQ0_WENeg : VitalDelayType := UnitDelay; --tDH edge / --tpw values: pulse width tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP tpw_CE1Neg_negedge : VitalDelayType := UnitDelay; --tCW tpw_LBNeg_negedge : VitalDelayType := UnitDelay; --tBW tpw_A0_negedge : VitalDelayType := UnitDelay; --tWC tRC -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded sram_file_name : STRING := "none";--"am41dl3244g_sram.mem"; UserPreload : BOOLEAN := FALSE; --TRUE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A17 : IN std_ulogic := 'U'; -- A16 : IN std_ulogic := 'U'; -- A15 : IN std_ulogic := 'U'; -- A14 : IN std_ulogic := 'U'; -- A13 : IN std_ulogic := 'U'; --address A12 : IN std_ulogic := 'U'; --lines A11 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A8 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- A6 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A1 : IN std_ulogic := 'U'; -- A0 : IN std_ulogic := 'U'; -- DQ15 : INOUT std_ulogic := 'U'; -- DQ14 : INOUT std_ulogic := 'U'; -- DQ13 : INOUT std_ulogic := 'U'; -- DQ12 : INOUT std_ulogic := 'U'; -- DQ11 : INOUT std_ulogic := 'U'; -- DQ10 : INOUT std_ulogic := 'U'; -- DQ9 : INOUT std_ulogic := 'U'; -- data DQ8 : INOUT std_ulogic := 'U'; -- lines DQ7 : INOUT std_ulogic := 'U'; -- DQ6 : INOUT std_ulogic := 'U'; -- DQ5 : INOUT std_ulogic := 'U'; -- DQ4 : INOUT std_ulogic := 'U'; -- DQ3 : INOUT std_ulogic := 'U'; -- DQ2 : INOUT std_ulogic := 'U'; -- DQ1 : INOUT std_ulogic := 'U'; -- DQ0 : INOUT std_ulogic := 'U'; -- SA : IN std_ulogic := 'U'; CIOSNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; LBNeg : IN std_ulogic := 'U'; UBNeg : IN std_ulogic := 'U'; CE1Neg : IN std_ulogic := 'U'; CE2 : IN std_ulogic := 'U' ); END COMPONENT; FOR U1: Flash32M USE ENTITY WORK.Flash32M(VHDL_BEHAVIORAL); FOR U2: SRAM4M USE ENTITY WORK.SRAM4M(VHDL_BEHAVIORAL); BEGIN U1: Flash32M GENERIC MAP ( tipd_A0 => tipd_A0, tipd_A1 => tipd_A1, tipd_A2 => tipd_A2, tipd_A3 => tipd_A3, tipd_A4 => tipd_A4, tipd_A5 => tipd_A5, tipd_A6 => tipd_A6, tipd_A7 => tipd_A7, tipd_A8 => tipd_A8, tipd_A9 => tipd_A9, tipd_A10 => tipd_A10, tipd_A11 => tipd_A11, tipd_A12 => tipd_A12, tipd_A13 => tipd_A13, tipd_A14 => tipd_A14, tipd_A15 => tipd_A15, tipd_A16 => tipd_A16, tipd_A17 => tipd_A17, tipd_A18 => tipd_A18, tipd_A19 => tipd_A19, tipd_A20 => tipd_A20, tipd_DQ0 => tipd_DQ0, tipd_DQ1 => tipd_DQ1, tipd_DQ2 => tipd_DQ2, tipd_DQ3 => tipd_DQ3, tipd_DQ4 => tipd_DQ4, tipd_DQ5 => tipd_DQ5, tipd_DQ6 => tipd_DQ6, tipd_DQ7 => tipd_DQ7, tipd_DQ8 => tipd_DQ8, tipd_DQ9 => tipd_DQ9, tipd_DQ10 => tipd_DQ10, tipd_DQ11 => tipd_DQ11, tipd_DQ12 => tipd_DQ12, tipd_DQ13 => tipd_DQ13, tipd_DQ14 => tipd_DQ14, tipd_DQ15 => tipd_DQ15, tipd_CENeg => tipd_CENeg, tipd_OENeg => tipd_OENeg, tipd_WENeg => tipd_WENeg, tipd_RESETNeg => tipd_RESETNeg, tipd_WPNeg => tipd_WPNeg, tipd_CIOFNeg => tipd_CIOFNeg, -- generic control parameters InstancePath => InstancePath, TimingChecksOn => TRUE,--DefaultTimingChecks, MsgOn => MsgOn, XOn => XOn, -- memory file to be loaded mem_file_name => mem_file_name, prot_file_name => prot_file_name , secsi_file_name => secsi_file_name, UserPreload => UserPreload, LongTimming => LongTimming, -- For FMF SDF technology file usage TimingModel => TimingModel -- TimingModel ) PORT MAP( A20 => A20, -- A19 => A19, -- A18 => A18, -- A17 => A17, -- A16 => A16, -- A15 => A15, -- A14 => A14, -- A13 => A13, --address A12 => A12, --lines A11 => A11, -- A10 => A10, -- A9 => A9, -- A8 => A8, -- A7 => A7, -- A6 => A6, -- A5 => A5,-- A4 => A4,-- A3 => A3, -- A2 => A2, -- A1 => A1, -- A0 => A0, -- DQ15 => DQ15, -- DQ15/A-1 DQ14 => DQ14, -- DQ13 => DQ13, -- DQ12 => DQ12, -- DQ11 => DQ11, -- DQ10 => DQ10, -- DQ9 => DQ9, -- data DQ8 => DQ8, -- lines DQ7 => DQ7, -- DQ6 => DQ6, -- DQ5 => DQ5, -- DQ4 => DQ4, -- DQ3 => DQ3, -- DQ2 => DQ2, -- DQ1 => DQ1, -- DQ0 => DQ0, -- CENeg => CENeg, OENeg => OENeg, WENeg => WENeg, RESETNeg => RESETNeg, WPNeg => WPNeg, --WP#/ACC CIOFNeg => CIOFNeg, RY => RY --RY/BY# ); U2: SRAM4M GENERIC MAP ( tipd_A0 => tipd_A0, tipd_A1 => tipd_A1, tipd_A2 => tipd_A2, tipd_A3 => tipd_A3, tipd_A4 => tipd_A4, tipd_A5 => tipd_A5, tipd_A6 => tipd_A6, tipd_A7 => tipd_A7, tipd_A8 => tipd_A8, tipd_A9 => tipd_A9, tipd_A10 => tipd_A10, tipd_A11 => tipd_A11, tipd_A12 => tipd_A12, tipd_A13 => tipd_A13, tipd_A14 => tipd_A14, tipd_A15 => tipd_A15, tipd_A16 => tipd_A16, tipd_A17 => tipd_A17, tipd_DQ0 => tipd_DQ0, tipd_DQ1 => tipd_DQ1, tipd_DQ2 => tipd_DQ2, tipd_DQ3 => tipd_DQ3, tipd_DQ4 => tipd_DQ4, tipd_DQ5 => tipd_DQ5, tipd_DQ6 => tipd_DQ6, tipd_DQ7 => tipd_DQ7, tipd_DQ8 => tipd_DQ8, tipd_DQ9 => tipd_DQ9, tipd_DQ10 => tipd_DQ10, tipd_DQ11 => tipd_DQ11, tipd_DQ12 => tipd_DQ12, tipd_DQ13 => tipd_DQ13, tipd_DQ14 => tipd_DQ14, tipd_DQ15 => tipd_DQ15, tipd_SA => tipd_SA, tipd_CIOSNeg => tipd_CIOSNeg, tipd_WENeg => tipd_WENeg, tipd_OENeg => tipd_OENeg, tipd_LBNeg => tipd_LBNeg, tipd_UBNeg => tipd_UBNeg, tipd_CE1Neg => tipd_CE1Neg, tipd_CE2 => tipd_CE2, -- generic control parameters InstancePath => InstancePath, TimingChecksOn => TRUE,--DefaultTimingChecks, MsgOn => MsgOn, XOn => XOn, -- memory file to be loaded sram_file_name => sram_file_name, UserPreload => UserPreload, -- For FMF SDF technology file usage TimingModel => TimingModel -- TimingModel ) PORT MAP( A17 => A17, -- A16 => A16, -- A15 => A15, -- A14 => A14, -- A13 => A13, --address A12 => A12, --lines A11 => A11, -- A10 => A10, -- A9 => A9, -- A8 => A8, -- A7 => A7, -- A6 => A6, -- A5 => A5,-- A4 => A4,-- A3 => A3, -- A2 => A2, -- A1 => A1, -- A0 => A0, -- DQ15 => DQ15, -- DQ15/A-1 DQ14 => DQ14, -- DQ13 => DQ13, -- DQ12 => DQ12, -- DQ11 => DQ11, -- DQ10 => DQ10, -- DQ9 => DQ9, -- data DQ8 => DQ8, -- lines DQ7 => DQ7, -- DQ6 => DQ6, -- DQ5 => DQ5, -- DQ4 => DQ4, -- DQ3 => DQ3, -- DQ2 => DQ2, -- DQ1 => DQ1, -- DQ0 => DQ0, -- SA => SA, CIOSNeg => CIOSNeg, OENeg => OENeg, WENeg => WENeg, LBNeg => LBNeg, UBNeg => UBNeg, CE1Neg => CE1Neg, CE2 => CE2 ); END vhdl_behavioral;