------------------------------------------------------------------------------- -- File name : am29dl323d.vhd ------------------------------------------------------------------------------- -- Copyright (C) 2004 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V1.0 J.Bogosavljevic 04 Apr 28 - Initial release ------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: AMD -- Technology: Flash Memory -- Part: am29dl323d -- -- Description: 32Mbit (4M x 8-Bit/2M x 16-Bit) Simultaneous Operation Flash -- Memory. Boot sector determined by TimingModel generic -- ------------------------------------------------------------------------------- -- Known Bugs: -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.all; USE FMF.conversions.all; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY am29dl323d IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; --address tipd_A10 : VitalDelayType01 := VitalZeroDelay01; --lines tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A18 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A19 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A20 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- DQ15/A-1 tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; --WP#/ACC tipd_BYTENeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A0_DQ0 : VitalDelayType01 := UnitDelay01;--tACC --tpd_dq15_dq0 tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(-,-,tDF,tCE,tDF,tce) tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z; --(tOE,tOE,tDF,-,tDF,-) tpd_WENeg_RY : VitalDelayType01 := UnitDelay01; --tBUSY --tpd_CENeg_RY : VitalDelayType01 := UnitDelay01; --tBUSY tpd_BYTENeg_DQ15 : VitalDelayType01Z := UnitDelay01Z; --(tfhqa:-:-, tfhqa,-:-, -:-:tflqz, tfhqa:-:-:, -:-:tflqz, tfhqa:-:-:) --(tfhqv, tfhqv, tflqz, tfhqa, tflqz, tfhqa)PROVERI --tsetup values tsetup_A0_OENeg : VitalDelayType := UnitDelay; --tASO edge \ tsetup_DQ0_CENeg : VitalDelayType := UnitDelay; --tDS edge / --thold values thold_A0_CENeg : VitalDelayType := UnitDelay; --tAH edge \ thold_BYTENeg_CENeg : VitalDelayType := UnitDelay; --telfh, tehfl thold_OENeg_WENeg : VitalDelayType := UnitDelay; --tOEH edge / thold_CENeg_RESETNeg: VitalDelayType := UnitDelay; --tRH edge / --tpw values: pulse width tpw_A0_negedge : VitalDelayType := UnitDelay; --tWC tRC tpw_RESETNeg_negedge: VitalDelayType := UnitDelay; --tRP tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP tpw_WENeg_posedge : VitalDelayType := UnitDelay; --tWPH tpw_CENeg_negedge : VitalDelayType := UnitDelay; --tCP ok tpw_CENeg_posedge : VitalDelayType := UnitDelay; --tCPH ok tpw_OENeg_posedge : VitalDelayType := UnitDelay; --toeph -- tdevice values: values for internal delays --byte write tdevice_POB : VitalDelayType := 5 us; --word write tdevice_POW : VitalDelayType := 7 us; --unlock bypass byte/word write tdevice_POU : VitalDelayType := 4 us; --Sector Erase Operation tWHWH2 tdevice_SEO : VitalDelayType := 700 ms; --erase suspend timeout - only max time specified tdevice_START_T1 : VitalDelayType := 20 us;--max 20 us --sector erase command sequence timeout tdevice_CTMOUT : VitalDelayType := 50 us; --device ready after Hardware reset(during embeded algorithm) tdevice_READY : VitalDelayType := 20 us; --tReady -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING := "none";--"am29dl323d.mem"; prot_file_name : STRING := "none";--"am29dl323d_prot.mem"; secsi_file_name : STRING := "none";--"am29dl323d_secsi.mem"; UserPreload : BOOLEAN := FALSE;--TRUE; LongTimming : BOOLEAN := TRUE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A20 : IN std_ulogic := 'U'; -- A19 : IN std_ulogic := 'U'; -- A18 : IN std_ulogic := 'U'; -- A17 : IN std_ulogic := 'U'; -- A16 : IN std_ulogic := 'U'; -- A15 : IN std_ulogic := 'U'; -- A14 : IN std_ulogic := 'U'; -- A13 : IN std_ulogic := 'U'; --address A12 : IN std_ulogic := 'U'; --lines A11 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A8 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- A6 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A1 : IN std_ulogic := 'U'; -- A0 : IN std_ulogic := 'U'; -- DQ15 : INOUT std_ulogic := 'U'; -- DQ15/A-1 DQ14 : INOUT std_ulogic := 'U'; -- DQ13 : INOUT std_ulogic := 'U'; -- DQ12 : INOUT std_ulogic := 'U'; -- DQ11 : INOUT std_ulogic := 'U'; -- DQ10 : INOUT std_ulogic := 'U'; -- DQ9 : INOUT std_ulogic := 'U'; -- data DQ8 : INOUT std_ulogic := 'U'; -- lines DQ7 : INOUT std_ulogic := 'U'; -- DQ6 : INOUT std_ulogic := 'U'; -- DQ5 : INOUT std_ulogic := 'U'; -- DQ4 : INOUT std_ulogic := 'U'; -- DQ3 : INOUT std_ulogic := 'U'; -- DQ2 : INOUT std_ulogic := 'U'; -- DQ1 : INOUT std_ulogic := 'U'; -- DQ0 : INOUT std_ulogic := 'U'; -- CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; --WP#/ACC BYTENeg : IN std_ulogic := 'U'; RY : OUT std_ulogic := 'U' --RY/BY# ); ATTRIBUTE VITAL_LEVEL0 of am29dl323d : ENTITY IS TRUE; END am29dl323d; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of am29dl323d IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT PartID : STRING := "am29dl323d"; CONSTANT MaxData : NATURAL := 16#FF#; CONSTANT MemSize : NATURAL := 16#3FFFFF#; CONSTANT BankNum : NATURAL := 1; --0,1 CONSTANT SecSize_l : NATURAL := 16#FFFF#; CONSTANT SecSize_s : NATURAL := 16#1FFF#; CONSTANT SecSiSize : NATURAL := 16#FFFF#; CONSTANT SecNum : NATURAL := 70; CONSTANT BootSecNum : NATURAL := 7; CONSTANT HiAddrBit : NATURAL := 20; CONSTANT MinCfiAddr : NATURAL := 16#10#; CONSTANT MaxCfiAddr : NATURAL := 16#4F#; -- interconnect path delay signals SIGNAL A20_ipd : std_ulogic := 'U'; SIGNAL A19_ipd : std_ulogic := 'U'; SIGNAL A18_ipd : std_ulogic := 'U'; SIGNAL A17_ipd : std_ulogic := 'U'; SIGNAL A16_ipd : std_ulogic := 'U'; SIGNAL A15_ipd : std_ulogic := 'U'; SIGNAL A14_ipd : std_ulogic := 'U'; SIGNAL A13_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL CENeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; SIGNAL WPNeg_ipd : std_ulogic := 'U'; SIGNAL BYTENeg_ipd : std_ulogic := 'U'; --- internal delays SIGNAL POB_in : std_ulogic := '0'; SIGNAL POB_out : std_ulogic := '0'; SIGNAL POW_in : std_ulogic := '0'; SIGNAL POW_out : std_ulogic := '0'; SIGNAL POU_in : std_ulogic := '0'; SIGNAL POU_out : std_ulogic := '0'; SIGNAL SEO_in : std_ulogic := '0'; SIGNAL SEO_out : std_ulogic := '0'; SIGNAL START_T1_out : std_ulogic := '0'; --Erase Start TimeOut SIGNAL START_T1_in : std_ulogic := '0'; SIGNAL CTMOUT_out : std_ulogic := '0'; --Sector Erase TimeOut SIGNAL CTMOUT_in : std_ulogic := '0'; SIGNAL READY_in : std_ulogic := '0'; SIGNAL READY_out : std_ulogic := '0'; -- Device ready after reset BEGIN --------------------------------------------------------------------------- -- Internal Delays --------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays POB :VitalBuf(POB_out, POB_in, (tdevice_POB ,UnitDelay)); POW :VitalBuf(POW_out, POW_in, (tdevice_POW ,UnitDelay)); POU :VitalBuf(POU_out, POU_in, (tdevice_POU ,UnitDelay)); SEO :VitalBuf(SEO_out, SEO_in, (tdevice_SEO ,UnitDelay)); START_T1 :VitalBuf(START_T1_out,START_T1_in, (tdevice_START_T1,UnitDelay)); CTMOUT :VitalBuf(CTMOUT_out, CTMOUT_in, (tdevice_CTMOUT-5 ns, UnitDelay)); READY :VitalBuf(READY_out, READY_in, (tdevice_READY ,UnitDelay)); --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_0 : VitalWireDelay (A20_ipd, A20, tipd_A20); w_1 : VitalWireDelay (A19_ipd, A19, tipd_A19); w_2 : VitalWireDelay (A18_ipd, A18, tipd_A18); w_3 : VitalWireDelay (A17_ipd, A17, tipd_A17); w_4 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_5 : VitalWireDelay (A15_ipd, A15, tipd_A15); w_6 : VitalWireDelay (A14_ipd, A14, tipd_A14); w_7 : VitalWireDelay (A13_ipd, A13, tipd_A13); w_8 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_9 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_10 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_11 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_12 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_13 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_14 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_15 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_16 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_17 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_18 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_19 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_20 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_21 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15); w_22 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14); w_23 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13); w_24 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12); w_25 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11); w_26 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10); w_27 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9); w_28 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8); w_29 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7); w_30 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6); w_31 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5); w_32 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4); w_33 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_34 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_35 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_36 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_37 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_38 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_39 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg); w_40 : VitalWireDelay (WPNeg_ipd, WPNeg, tipd_WPNeg); w_41 : VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg); w_42 : VitalWireDelay (BYTENeg_ipd, BYTENeg, tipd_BYTENeg); END BLOCK; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior: BLOCK PORT ( A : IN std_logic_vector(HiAddrBit downto 0) := (OTHERS => 'U'); DIn : IN std_logic_vector(15 downto 0) := (OTHERS => 'U'); DOut : OUT std_ulogic_vector(15 downto 0) := (OTHERS => 'Z'); CENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; WPNeg : IN std_ulogic := 'U'; BYTENeg : IN std_ulogic := 'U'; RY : OUT std_ulogic := 'U' ); PORT MAP ( A(20) => A20_ipd, A(19) => A19_ipd, A(18) => A18_ipd, A(17) => A17_ipd, A(16) => A16_ipd, A(15) => A15_ipd, A(14) => A14_ipd, A(13) => A13_ipd, A(12) => A12_ipd, A(11) => A11_ipd, A(10) => A10_ipd, A(9) => A9_ipd, A(8) => A8_ipd, A(7) => A7_ipd, A(6) => A6_ipd, A(5) => A5_ipd, A(4) => A4_ipd, A(3) => A3_ipd, A(2) => A2_ipd, A(1) => A1_ipd, A(0) => A0_ipd, DIn(15) => DQ15_ipd, DIn(14) => DQ14_ipd, DIn(13) => DQ13_ipd, DIn(12) => DQ12_ipd, DIn(11) => DQ11_ipd, DIn(10) => DQ10_ipd, DIn(9) => DQ9_ipd, DIn(8) => DQ8_ipd, DIn(7) => DQ7_ipd, DIn(6) => DQ6_ipd, DIn(5) => DQ5_ipd, DIn(4) => DQ4_ipd, DIn(3) => DQ3_ipd, DIn(2) => DQ2_ipd, DIn(1) => DQ1_ipd, DIn(0) => DQ0_ipd, DOut(15) => DQ15, DOut(14) => DQ14, DOut(13) => DQ13, DOut(12) => DQ12, DOut(11) => DQ11, DOut(10) => DQ10, DOut(9) => DQ9, DOut(8) => DQ8, DOut(7) => DQ7, DOut(6) => DQ6, DOut(5) => DQ5, DOut(4) => DQ4, DOut(3) => DQ3, DOut(2) => DQ2, DOut(1) => DQ1, DOut(0) => DQ0, CENeg => CENeg_ipd, OENeg => OENeg_ipd, WENeg => WENeg_ipd, RESETNeg => RESETNeg_ipd, WPNeg => WPNeg_ipd, BYTENeg => BYTENeg_ipd, RY => RY ); -- State Machine : State_Type TYPE state_type IS ( RESET, Z001, PREL_SETBWB, PREL_ULBYPASS, CFI, AS, AS_CFI, A0SEEN, OTP, OTP_Z001, OTP_PREL, OTP_AS, OTP_A0SEEN, C8, C8_Z001, C8_PREL, ERS, SERS, ESPS, SERS_EXEC, ESP, ESP_Z001, ESP_PREL, ESP_CFI, ESP_A0SEEN, ESP_AS, PGMS ); --Flash Memory Array TYPE MemArray IS ARRAY (0 TO MemSize) OF INTEGER RANGE -1 TO MaxData; --Common Flash Interface Query codes TYPE CFItype IS ARRAY (MinCfiAddr TO MaxCfiAddr) OF NATURAL RANGE 0 TO 16#FF#; TYPE BankArray IS ARRAY (0 TO BankNum) OF INTEGER RANGE 0 TO BankNum+1; --SecSi Sector TYPE SecSiType IS ARRAY ( 0 TO SecSiSize) OF INTEGER RANGE -1 TO MaxData; -- states SIGNAL current_state : state_type; -- SIGNAL next_state : state_type; -- -- powerup SIGNAL PoweredUp : std_logic := '0'; --zero delay signals SIGNAL DOut_zd : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL RY_zd : std_logic := 'Z'; --FSM control signals SIGNAL ULBYPASS : std_logic := '0'; --Unlock Bypass Active SIGNAL OTP_ACT : std_logic := '0'; --SecSi access SIGNAL ESP_ACT : std_logic := '0'; --Erase Suspend SIGNAL PDONE : std_logic := '1'; --Prog. Done SIGNAL PSTART : std_logic := '0'; --Start Programming --Program location is in protected sector SIGNAL PERR : std_logic := '0'; SIGNAL EDONE : std_logic := '1'; --Ers. Done SIGNAL ESTART : std_logic := '0'; --Start Erase SIGNAL ESUSP : std_logic := '0'; --Suspend Erase SIGNAL ERES : std_logic := '0'; --Resume Erase --All sectors selected for erasure are protected SIGNAL EERR : std_logic := '0'; --Sectors selected for erasure SIGNAL ERS_QUEUE : std_logic_vector(SecNum downto 0) := (OTHERS => '0'); --Command Register SIGNAL write : std_logic := '0'; SIGNAL read : std_logic := '0'; --Sector Address SIGNAL SecAddr : NATURAL RANGE 0 TO SecNum := 0; SIGNAL SA : NATURAL RANGE 0 TO SecNum := 0; --Address within sector SIGNAL Address : NATURAL RANGE 0 TO SecSize_l := 0; SIGNAL D_tmp0 : NATURAL RANGE 0 TO MaxData; SIGNAL D_tmp1 : NATURAL RANGE 0 TO MaxData; --A20:A11 Don't Care SIGNAL Addr : NATURAL RANGE 0 TO 16#7FF# := 0; --glitch protection SIGNAL gWE_n : std_logic := 'U'; SIGNAL gCE_n : std_logic := 'U'; SIGNAL gOE_n : std_logic := 'U'; SIGNAL RST : std_logic := '1'; SIGNAL reseted : std_logic := '0'; SIGNAL LB_Ei : BankArray; SIGNAL BA_sel2 : NATURAL RANGE 0 TO BankNum +1 := 0; SIGNAL BA : NATURAL RANGE 0 TO BankNum +1 := 0; -- Mem(SecAddr)(Address).... SHARED VARIABLE Mem : MemArray := (OTHERS=> MaxData); SHARED VARIABLE CFI_array : CFItype := (OTHERS => 0); --protected sectors SHARED VARIABLE Sec_Prot : std_logic_vector(SecNum downto 0) := (OTHERS => '0'); SHARED VARIABLE SecSi : SecSiType := (OTHERS => 0); --SecSi ProtectionStatus SIGNAL FactoryProt : std_logic := '1'; -- timing check violation SIGNAL Viol : X01 := '0'; --top/bottom identifiers SIGNAL vs : INTEGER;--0 if bottom else 1 SIGNAL first_prot : INTEGER; SIGNAL DOut_z : std_logic_vector(15 downto 0) :=(OTHERS=>'Z'); ---------- --output delay control SHARED VARIABLE tpd_from_OE : BOOLEAN := FALSE; SHARED VARIABLE tpd_from_CE : BOOLEAN := FALSE; SHARED VARIABLE Open3state : BOOLEAN := FALSE; ---------------------------------------------------------- --FUNCTIONS AND PROCEDURES -------------------------------- ------------------ --Sector functions ------------------ -- Size of sector FUNCTION SectSize(i : NATURAL) RETURN NATURAL IS VARIABLE result : NATURAL; BEGIN result := 0; IF ((TimingModel(11) = 't' AND i >= 63) OR (TimingMOdel(11) = 'b' AND i<= 7)) THEN result :=SecSize_S; ELSE result :=SecSize_L; END IF; RETURN result; END SectSize; --sector's starting address FUNCTION sssa(i : NATURAL) RETURN NATURAL IS VARIABLE result : NATURAL; BEGIN result := 0; IF (TimingModel(11) = 't' AND i <= 62) OR (TimingModel(11) = 'b' AND i <= 7) THEN result := (SectSize(i) + 1) * i; ELSIF (TimingModel(11) = 't' AND i > 62) THEN result := (SecNum - BootSecNum)*(SecSize_l+1) +--3F0000 (SectSize(i) + 1) * (i-63); ELSIF(TimingModel(11) = 'b' AND i > 7) THEN result := (BootSecNum + 1)*(SecSize_s+1) +--10000 (SectSize(i) + 1) * (i-8); END IF; RETURN result; END sssa; --sector's ending address FUNCTION ssea(i : NATURAL) RETURN NATURAL IS VARIABLE result : NATURAL; BEGIN result := 0; IF ((TimingModel(11) = 't' AND i <= 62) OR (TimingModel(11) = 'b' AND i <= 7 )) THEN result := (SectSize(i) + 1) * (i+1) - 1; ELSIF (TimingModel(11) = 't' AND i > 62) THEN result := (SecNum - BootSecNum)*(SecSize_l+1) +--1F0000 (SectSize(i) + 1) * (i-63+1)-1; ELSIF(TimingModel(11) = 'b' AND i > 7) THEN result := (BootSecNum + 1)*(SecSize_s+1) +--10000 (SectSize(i) + 1) * (i-8+1) - 1; END IF; RETURN result; END ssea; PROCEDURE RestoreSectAddr ( SIGNAL A : IN std_logic_vector(HiAddrBit downto 0); VARIABLE SecAddr : INOUT NATURAL RANGE 0 TO SecNum; VARIABLE Addr : INOUT NATURAL RANGE 0 TO SecSize_L; SIGNAL D15 : IN std_logic; SIGNAL BYTENeg : IN std_logic ) IS VARIABLE SA_tmp : NATURAL RANGE 0 TO SecNum; VARIABLE A_tmp : std_logic_vector(15 downto 0); BEGIN SA_tmp := to_nat (A(HiAddrBit downto 15)); IF (TimingModel(11) = 'b' AND SA_tmp = 0) OR (TimingModel(11) = 't' AND SA_tmp = 63) THEN SecAddr := SA_tmp + to_nat(A(14 downto 12)); A_tmp := "0000" & A(11 downto 0); ELSIF TimingModel(11) = 'b' THEN SecAddr := SA_tmp + BootSecNum; A_tmp := '0' & A(14 downto 0); ELSE SecAddr := SA_tmp ; A_tmp := '0' & A(14 downto 0); END IF; IF (BYTENeg = '0') THEN Addr := to_nat(A_tmp & D15); ELSE Addr := to_nat(A_tmp & '0'); END IF; END RestoreSectAddr; ------------------------ --BANK ACCESS FUNCTIONS ----------------------- --returns what bank sector belongs to FUNCTION ResolveBank(Sect: NATURAL) RETURN NATURAL IS VARIABLE result : NATURAL :=0; BEGIN IF ( (TimingModel(9) = '2' AND TimingModel(11) = 't' AND Sect < 56) OR (TimingModel(9) = '2' AND TimingModel(11) = 'b' AND Sect > 14) OR (TimingModel(9) = '3' AND TimingModel(11) = 't' AND Sect < 48) OR (TimingModel(9) = '3' AND TimingModel(11) = 'b' AND Sect > 22) OR (TimingModel(9) = '4' AND TimingModel(11) = 't' AND Sect < 32) OR (TimingModel(9) = '4' AND TimingModel(11) = 'b' AND Sect > 38) ) THEN result := 2; ELSIF ( (TimingModel(9) = '2' AND TimingModel(11) = 't' AND Sect >= 56) OR (TimingModel(9) = '2' AND TimingModel(11) = 'b' AND Sect <= 14) OR (TimingModel(9) = '3' AND TimingModel(11) = 't' AND Sect >= 48) OR (TimingModel(9) = '3' AND TimingModel(11) = 'b' AND Sect <= 22) OR (TimingModel(9) = '4' AND TimingModel(11) = 't' AND Sect >= 32) OR (TimingModel(9) = '4' AND TimingModel(11) = 'b' AND Sect <= 38) ) THEN result := 1; END IF; RETURN result; END ResolveBank; FUNCTION BankLockedForErs (LB_Ei : BankArray; BA :NATURAL RANGE 0 TO BankNum + 1) RETURN BOOLEAN IS VARIABLE result : BOOLEAN; BEGIN result := FALSE; IF BA > 0 THEN FOR i IN 0 TO BankNum LOOP IF LB_Ei(i) = BA THEN result := TRUE; END IF; END LOOP; END IF; RETURN result; END BankLockedForErs; FUNCTION BankLocked( BA_sel2 :NATURAL RANGE 0 TO BankNum + 1; BA :NATURAL RANGE 0 TO BankNum + 1 ) RETURN BOOLEAN IS VARIABLE result : BOOLEAN; BEGIN result := FALSE; IF BA_sel2 = BA OR BA_sel2 = 0 THEN result := TRUE; END IF; RETURN result; END BankLocked; PROCEDURE AddBankForErs( SIGNAL BA : IN NATURAL RANGE 0 TO BankNum+1; SIGNAL LB_Ei : INOUT BankArray ) IS VARIABLE i : NATURAL; VARIABLE found : BOOLEAN; BEGIN found := FALSE; i := 0; -- add bank for erasure if !found WHILE (i <= BankNum AND found = FALSE) LOOP IF LB_Ei(i) = 0 THEN found := TRUE; LB_Ei(i) <= BA; END IF; i := i+1; END LOOP; END PROCEDURE AddBankForErs; PROCEDURE ResetBankForErs( SIGNAL LB_Ei : INOUT BankArray ) IS BEGIN FOR i IN 0 TO BankNum LOOP LB_Ei(i) <= 0; END LOOP; END PROCEDURE ResetBankForErs; FUNCTION GroupProtect(conv : NATURAL ) RETURN NATURAL IS VARIABLE result : NATURAL; BEGIN result := 0; IF (conv = 0 ) THEN result := conv; END IF; IF ( conv >= 1 ) AND ( conv <= 3 ) THEN result := 1; END IF; IF ( conv >= 4) AND ( conv <= 59 ) THEN result := 4 * ( ( conv ) / 4 ); END IF; IF ( conv >= 60 ) AND ( conv <= 62 ) THEN result := 60; END IF; IF ( conv > 62 ) THEN result := conv; END IF; RETURN result; END GroupProtect; FUNCTION OtpAddr(vs : INTEGER; SecAddr : NATURAL RANGE 0 TO SecNum) RETURN BOOLEAN IS VARIABLE result : BOOLEAN; BEGIN result := FALSE; IF ((vs = 1 AND SecAddr >= 63) OR (vs = 0 AND SecAddr <= 7)) THEN result := TRUE; END IF; RETURN result; END OtpAddr; PROCEDURE MemRead ( SIGNAL SecAddr : IN NATURAL RANGE 0 TO SecNum; SIGNAL Address : IN NATURAL RANGE 0 TO SecSize_L; SIGNAL BYTENeg : IN std_ulogic; SIGNAL DOut_zd : INOUT std_logic_vector(15 downto 0) ) IS VARIABLE A_tmp : INTEGER RANGE -1 TO MemSize; BEGIN A_tmp := sssa(SecAddr) + Address; IF Mem(A_tmp) = -1 THEN DOut_zd(7 downto 0) <= (OTHERS => 'X'); ELSE DOut_zd(7 downto 0) <= to_slv(Mem(A_tmp),8); END IF; IF BYTENeg = '1' THEN IF Mem(A_tmp+1) = -1 THEN DOut_zd(15 downto 8) <= (OTHERS => 'X'); ELSE DOut_zd(15 downto 8) <= to_slv(Mem(A_tmp+1),8); END IF; END IF; END MemRead; PROCEDURE SecSiRead ( SIGNAL SecAddr : IN NATURAL RANGE 0 TO SecNum; SIGNAL Address : IN NATURAL RANGE 0 TO SecSize_l; SIGNAL BYTENeg : IN std_ulogic; SIGNAL DOut_zd : INOUT std_logic_vector(15 downto 0) ) IS VARIABLE SecSiAddr : NATURAL RANGE 0 TO SecSiSize; BEGIN IF (TimingModel(11) = 't' AND SecAddr >= 63) OR (TimingModel(11) = 'b' AND SecAddr <= 7) THEN SecSiAddr := Address; IF SecSi(SecSiAddr) = -1 THEN DOut_zd(7 downto 0) <= (OTHERS => 'X'); ELSE DOut_zd(7 downto 0) <= to_slv(SecSi(SecSiAddr),8); END IF; IF BYTENeg = '1' THEN IF SecSi(SecSiAddr + 1) = -1 THEN DOut_zd(15 downto 8) <= (OTHERS => 'X'); ELSE DOut_zd(15 downto 8) <= to_slv(SecSi(SecSiAddr + 1),8); END IF; END IF; ELSE DOut_zd(15 downto 0) <= (OTHERS=>'Z'); ASSERT FALSE REPORT "Wrong SecSI Address read" SEVERITY NOTE; END IF; END SecSiRead; --AsRead(Address, BYTENeg, vs, SecAddr, Dout_zd); PROCEDURE AsRead ( SIGNAL Address : IN NATURAL RANGE 0 TO SecSize_L; SIGNAL BYTENeg : IN std_ulogic; SIGNAL vs : IN INTEGER; SIGNAL SecAddr : IN NATURAL RANGE 0 TO SecNum; SIGNAL DOut_zd : INOUT std_logic_vector(15 downto 0) ) IS BEGIN IF BYTENeg = '1' THEN IF Address = 2 THEN DOut_zd(15 downto 8) <= to_slv(16#22#,8); ELSE DOut_zd(15 downto 8) <= to_slv(0,8); END IF; ELSE DOut_zd(15 downto 8) <= "ZZZZZZZZ"; END IF; IF Address = 0 THEN DOut_zd(7 downto 0) <= to_slv(1,8); ELSIF Address = 2 THEN IF vs = 1 THEN DOut_zd(7 downto 0) <= to_slv(16#50#,8); ELSE DOut_zd(7 downto 0) <= to_slv(16#53#,8); END IF; ELSIF Address = 4 THEN DOut_zd(7 downto 1) <= to_slv(0,7); DOut_zd(0) <= Sec_Prot(SecAddr); ELSIF Address = 6 THEN DOut_zd(7 downto 0) <= to_slv(1,8); IF FactoryProt = '1' THEN DOut_zd(7) <= '1'; END IF; ELSE DOut_zd(15 downto 0) <= (OTHERS=>'Z'); ASSERT FALSE REPORT "Invalid AS address" SEVERITY NOTE; END IF; END AsRead; PROCEDURE CfiRead ( SIGNAL Address : IN NATURAL RANGE 0 TO 16#7FF#; SIGNAL DOut_zd : INOUT std_logic_vector(15 downto 0) ) IS VARIABLE Addr : INTEGER RANGE -1 TO MemSize; BEGIN Addr := Address; DOut_zd(15 downto 0) <= (OTHERS=>'0'); IF ((Addr >= MinCfiAddr) AND (Addr <= MaxCfiAddr)) THEN DOut_zd(7 downto 0) <= to_slv(CFI_array(Addr) ,8); ELSE DOut_zd(15 downto 0) <= (OTHERS=>'Z'); ASSERT FALSE REPORT "Invalid CFI query address" SEVERITY NOTE; END IF; END CfiRead; BEGIN --------------------------------------------------------------------------- --VarSect --------------------------------------------------------------------------- vs <= 1 WHEN TimingModel(11) ='t' ELSE 0; first_prot <= SecNum - 1 WHEN TimingModel(11) = 't' ELSE 0; --------------------------------------------------------------------------- --Power Up time 100 ns; --------------------------------------------------------------------------- PoweredUp <= '1' AFTER 100 ns; RST <= RESETNeg AFTER 500 ns; --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS(A, Din, CENeg, OENeg, WENeg, RESETNeg, WPNeg) -- Timing Check Variables VARIABLE Tviol_A0_CENeg : X01 := '0'; VARIABLE TD_A0_CENeg : VitalTimingDataType; VARIABLE Tviol_A0_WENeg : X01 := '0'; VARIABLE TD_A0_WENeg : VitalTimingDataType; VARIABLE Tviol_BYTENeg_WENeg : X01 := '0'; VARIABLE TD_BYTENeg_WENeg : VitalTimingDataType; VARIABLE Tviol_DQ0_CENeg : X01 := '0'; VARIABLE TD_DQ0_CENeg : VitalTimingDataType; VARIABLE Tviol_DQ0_WENeg : X01 := '0'; VARIABLE TD_DQ0_WENeg : VitalTimingDataType; VARIABLE Tviol_A0_OENeg : X01 := '0';---??? VARIABLE TD_A0_OENeg : VitalTimingDataType; VARIABLE Tviol_CENeg_RESETNeg : X01 := '0'; VARIABLE TD_CENeg_RESETNeg : VitalTimingDataType; VARIABLE Tviol_OENeg_RESETNeg : X01 := '0'; VARIABLE TD_OENeg_RESETNeg : VitalTimingDataType; VARIABLE Tviol_WENeg_RESETNeg : X01 := '0'; VARIABLE TD_WENeg_RESETNeg : VitalTimingDataType; VARIABLE Tviol_OENeg_WENeg_R : X01 := '0'; VARIABLE TD_OENeg_WENeg_R : VitalTimingDataType; VARIABLE Tviol_BYTENeg_CENeg : X01 := '0'; VARIABLE TD_BYTENeg_CENeg : VitalTimingDataType; VARIABLE Pviol_RESETNeg : X01 := '0'; VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CENeg : X01 := '0'; VARIABLE PD_CENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg : X01 := '0'; VARIABLE PD_WENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A0 : X01 := '0'; VARIABLE PD_A0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_OENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_OENeg : X01 := '0'; VARIABLE Violation : X01 := '0'; BEGIN --------------------------------------------------------------------------- -- Timing Check Section --------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Setup/Hold Check between A and CENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => CENeg, RefSignalName => "CE#", HoldHigh => thold_A0_CENeg, HoldLow => thold_A0_CENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CENeg, Violation => Tviol_A0_CENeg ); -- Setup/Hold Check between A and WENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => WENeg, RefSignalName => "WE#", HoldHigh => thold_A0_CENeg, HoldLow => thold_A0_CENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_WENeg, Violation => Tviol_A0_WENeg ); -- Setup/Hold Check between BYTENeg and WENeg VitalSetupHoldCheck ( TestSignal => BYTENeg, TestSignalName => "BYTENeg", RefSignal => WENeg, RefSignalName => "WE#", HoldHigh => thold_A0_CENeg, HoldLow => thold_A0_CENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_BYTENeg_WENeg, Violation => Tviol_BYTENeg_WENeg ); -- Setup/Hold Check between A and OENeg VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => OENeg, RefSignalName => "OE#", SetupHigh => tsetup_A0_OENeg, SetupLow => tsetup_A0_OENeg, CheckEnabled => PDONE = '0' OR EDONE = '0',--during emb algorith. RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_OENeg, Violation => Tviol_A0_OENeg ); -- Setup/Hold Check between DQ and CENeg VitalSetupHoldCheck ( TestSignal => Din, TestSignalName => "DQ", RefSignal => CENeg, RefSignalName => "CE#", SetupHigh => tsetup_DQ0_CENeg, SetupLow => tsetup_DQ0_CENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_CENeg, Violation => Tviol_DQ0_CENeg ); -- Setup/Hold Check between DQ and WENeg VitalSetupHoldCheck ( TestSignal => Din, TestSignalName => "DQ", RefSignal => WENeg, RefSignalName => "WE#", SetupHigh => tsetup_DQ0_CENeg, SetupLow => tsetup_DQ0_CENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_WENeg, Violation => Tviol_DQ0_WENeg ); -- Hold Check between CENeg and RESETNeg VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CE#", RefSignal => RESETNeg, RefSignalName => "RESET#", HoldHigh => thold_CENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_RESETNeg, Violation => Tviol_CENeg_RESETNeg ); -- Hold Check between OENeg and RESETNeg VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OE#", RefSignal => RESETNeg, RefSignalName => "RESET#", HoldHigh => thold_CENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_RESETNeg, Violation => Tviol_OENeg_RESETNeg ); -- Hold Check between WENeg and RESETNeg VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WE#", RefSignal => RESETNeg, RefSignalName => "RESET#", HoldHigh => thold_CENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_RESETNeg, Violation => Tviol_WENeg_RESETNeg ); -- Hold Check between OENeg and WENeg VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OE#", RefSignal => WENeg, RefSignalName => "WE#", HoldHigh => thold_OENeg_WENeg, CheckEnabled => PDONE = '0' OR EDONE = '0',--toggle, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_WENeg_R, Violation => Tviol_OENeg_WENeg_R ); -- Setup/Hold Check between BYTENeg and WENeg VitalSetupHoldCheck ( TestSignal => BYTENeg, TestSignalName => "BYTE#", RefSignal => CENeg, RefSignalName => "CE#", HoldHigh => thold_BYTENeg_CENeg,--5ns HoldLow => thold_BYTENeg_CENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_BYTENeg_CENeg, Violation => Tviol_BYTENeg_CENeg ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESET#", PulseWidthLow => tpw_RESETNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg, Violation => Pviol_RESETNeg ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WE#", PulseWidthHigh => tpw_WENeg_posedge, PulseWidthLow => tpw_WENeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg, Violation => Pviol_WENeg ); -- PulseWidth Check for CENeg VitalPeriodPulseCheck ( TestSignal => CENeg, TestSignalName => "CE#", PulseWidthHigh => tpw_CENeg_posedge, PulseWidthLow => tpw_CENeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_CENeg, Violation => Pviol_CENeg ); -- PulseWidth Check for A VitalPeriodPulseCheck ( TestSignal => A(0), TestSignalName => "A", PulseWidthHigh => tpw_A0_negedge, PulseWidthLow => tpw_A0_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_A0, Violation => Pviol_A0 ); -- PulseWidth Check for OENeg VitalPeriodPulseCheck ( TestSignal => OENeg, TestSignalName => "OE#", PulseWidthHigh => tpw_OENeg_posedge, CheckEnabled => PDONE = '0' OR EDONE = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_OENeg, Violation => Pviol_OENeg ); Violation := Tviol_A0_CENeg OR Tviol_A0_WENeg OR Tviol_BYTENeg_WENeg OR Tviol_DQ0_CENeg OR Tviol_DQ0_WENeg OR Tviol_CENeg_RESETNeg OR Tviol_OENeg_RESETNeg OR Tviol_WENeg_RESETNeg OR Tviol_BYTENeg_CENeg OR Tviol_OENeg_WENeg_R OR Pviol_RESETNeg OR Pviol_WENeg OR Pviol_CENeg OR Pviol_A0 OR Pviol_OENeg ; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS VITALTimingCheck; ---------------------------------------------------------------------------- -- sequential process for reset control and FSM state transition ---------------------------------------------------------------------------- StateTransition : PROCESS(next_state, RESETNeg, RST, READY_out, PDone, EDone, PoweredUp) VARIABLE R : std_logic := '0'; --prog or erase in progress VARIABLE E : std_logic := '0'; --reset timming error BEGIN IF PoweredUp = '1' THEN --Hardware reset timing control IF falling_edge(RESETNeg) THEN E := '0'; IF (PDONE = '0' OR EDONE = '0') THEN --if program or erase in progress READY_in <= '1'; R := '1'; ELSE READY_in <= '0'; R := '0'; --prog or erase not in progress END IF; ELSIF rising_edge(RESETNeg) AND RST = '1' THEN --RESET# pulse < tRP READY_in <= '0'; R := '0'; E := '1'; END IF; IF RESETNeg = '1' AND ( R = '0' OR (R = '1' AND READY_out = '1')) THEN current_state <= next_state; READY_in <= '0'; E := '0'; R := '0'; reseted <= '1'; ELSIF (R = '0' AND RESETNeg = '0' AND RST = '0') OR (R = '1' AND RESETNeg = '0' AND RST = '0' AND READY_out = '0') OR (R = '1' AND RESETNeg = '1' AND RST = '0' AND READY_out = '0') OR (R = '1' AND RESETNeg = '1' AND RST = '1' AND READY_out = '0') THEN --no state transition while RESET# low current_state <= RESET; --reset start reseted <= '0'; END IF; ELSE current_state <= RESET; -- reset reseted <= '0'; E := '0'; R := '0'; END IF; END PROCESS StateTransition; --------------------------------------------------------------------------- --Glitch Protection: Inertial Delay does not propagate pulses <5ns --------------------------------------------------------------------------- gWE_n <= WENeg AFTER 5 ns; gCE_n <= CENeg AFTER 5 ns; gOE_n <= OENeg AFTER 5 ns; --------------------------------------------------------------------------- --Process that reports warning when changes on signals WE#, CE#, OE# are --discarded --------------------------------------------------------------------------- PulseWatch : PROCESS (WENeg, CENeg, OENeg, gWE_n, gCE_n, gOE_n) BEGIN IF (WENeg'EVENT AND WENeg = gWE_n) OR (CENeg'EVENT AND CENeg = gCE_n) OR (OENeg'EVENT AND OENeg = gOE_n) THEN ASSERT false REPORT "Glitch detected on write control signals" SEVERITY warning; END IF; END PROCESS PulseWatch; --latch address on rising edge and data on falling edge of write write_dc: PROCESS (gWE_n, gCE_n, gOE_n, RESETNeg, reseted) BEGIN IF RESETNeg /= '0' AND reseted ='1' THEN IF (gWE_n = '0') AND (gCE_n = '0') AND (gOE_n = '1') THEN write <= '1'; ELSIF (gWE_n = '1' OR gCE_n = '1') AND gOE_n = '1' THEN write <= '0'; ELSE write <= 'X'; END IF; END IF; IF ((gWE_n = '1') AND (gCE_n = '0') AND (gOE_n = '0')) THEN read <= '1'; ELSE read <= '0'; END IF; END PROCESS write_dc; --------------------------------------------------------------------------- -- Latch address on falling edge of WE# or CE# what ever comes later -- Latches data on rising edge of WE# or CE# what ever comes first -- also Write cycle decode --------------------------------------------------------------------------- BusCycleDecode : PROCESS(A, Din, write, WENeg, CENeg, OENeg, BYTENeg, reseted) VARIABLE A_tmp : NATURAL RANGE 0 TO 16#7FF#; VARIABLE SA_tmp : NATURAL RANGE 0 TO SecNum; VARIABLE A_tmp1 : NATURAL RANGE 0 TO SecSize_l; VARIABLE CE : std_logic; VARIABLE i : NATURAL; BEGIN IF reseted = '1' THEN IF (falling_edge(WENeg) AND CENeg ='0' AND OENeg = '1') OR (falling_edge(CENeg) AND WENeg/= OENeg ) OR (falling_edge(OENeg) AND WENeg ='1' AND CENeg = '0') OR ((A'EVENT OR (Din(15)'EVENT AND BYTENeg='0' AND Din(15) /= Dout_zd(15)) OR BYTENeg'EVENT ) AND WENeg = '1' AND CENeg = '0' AND OENeg = '0') THEN RestoreSectAddr(A, SA_tmp, A_tmp1, Din(15), BYTENeg); A_tmp := to_nat(A(10 downto 0)); ELSIF (rising_edge(WENeg) OR rising_edge(CENeg)) AND write = '1' THEN D_tmp0 <= to_nat(Din(7 downto 0)); IF BYTENeg = '1' THEN D_tmp1 <= to_nat(Din(15 downto 8)); END IF; END IF; IF rising_edge(write) OR falling_edge(OENeg) OR ((A'EVENT OR (Din(15)'EVENT AND BYTENeg = '0') OR BYTENeg'EVENT ) AND WENeg = '1' AND CENeg = '0' AND OENeg = '0') THEN SecAddr <= SA_tmp; Address <= A_tmp1; BA <= ResolveBank(SA_tmp); Addr <= A_tmp; END IF; END IF; END PROCESS BusCycleDecode; --------------------------------------------------------------------------- -- Timing control for the Program/ Write Buffer Program Operations -- start/ suspend/ resume --------------------------------------------------------------------------- ProgTime : PROCESS(PSTART, BYTENeg, ESP_ACT, OTP_ACT, reseted) VARIABLE cnt : NATURAL RANGE 0 TO SecNum + 1 := 0; VARIABLE elapsed : time; VARIABLE duration : time; VARIABLE start : time; VARIABLE pob : time; VARIABLE pow : time; BEGIN IF LongTimming THEN IF ULBYPASS = '1' THEN pob := tdevice_POU; pow := tdevice_POU; ELSE pob := tdevice_POB; pow := tdevice_POW; END IF; ELSE pob := tdevice_POB / 1; pow := tdevice_POW / 1; END IF; IF rising_edge(reseted) THEN PDONE <= '1'; -- reset done, programing terminated ELSIF reseted = '1' THEN IF rising_edge(PSTART) AND PDONE = '1' THEN IF (Sec_Prot(SA) = '0' AND (Ers_queue(SA) = '0' OR ESP_ACT = '0') AND (FactoryProt = '0' OR OTP_ACT = '0')) THEN IF BYTENeg = '1' THEN duration := pow;--tdevice_POW; ELSE duration := pob;--tdevice_POB; END IF; PDONE <= '0', '1' AFTER duration; ELSE PERR <= '1', '0' AFTER 1 us; END IF; END IF; END IF; END PROCESS ProgTime; --------------------------------------------------------------------------- -- Timing control for the Erase Operations --------------------------------------------------------------------------- ErsTime :PROCESS(ESTART, ESUSP, ERES, Ers_Queue, reseted) VARIABLE cnt : NATURAL RANGE 0 TO SecNum := 0; VARIABLE elapsed : time; VARIABLE duration : time; VARIABLE start : time; VARIABLE seo : time; VARIABLE bank1 : BOOLEAN; VARIABLE bank2 : BOOLEAN; BEGIN bank1 := FALSE; bank2 := FALSE; IF LongTimming THEN seo := tdevice_SEO; ELSE seo := tdevice_SEO / 1000; END IF; IF rising_edge(reseted) THEN EDONE <= '1'; -- reset done, ERASE terminated ELSIF reseted = '1' THEN IF rising_edge(ESTART) AND EDONE = '1' THEN cnt := 0; IF OTP_ACT = '1' THEN IF (FactoryProt = '0') THEN cnt := cnt+1; END IF; ELSE FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN cnt := cnt +1; bank1 := bank1 OR ResolveBAnk(i) = 1; bank2 := bank2 OR ResolveBAnk(i) = 2; END IF; END LOOP; END IF; IF cnt > 0 THEN elapsed := 0 ns; duration := cnt * seo; EDONE <= '0', '1' AFTER duration; start := NOW; ELSE EERR <= '1', '0' AFTER 100 us; END IF; ELSIF rising_edge(ESUSP) AND EDONE = '0' THEN elapsed := NOW - start; duration := duration - elapsed; EDONE <= '0'; ELSIF rising_edge(ERES) AND EDONE = '0' THEN start := NOW; EDONE <= '0', '1' AFTER duration; END IF; END IF; END PROCESS ErsTime; --------------------------------------------------------------------------- -- Main Behavior Process -- combinational process for next state generation --------------------------------------------------------------------------- StateGen :PROCESS(write, Addr, D_tmp0, ULBYPASS, PDONE, EDONE, CTMOUT_out, START_T1_out, reseted, READY_out, PERR, EERR) VARIABLE PATTERN_1 : boolean := FALSE; VARIABLE PATTERN_2 : boolean := FALSE; VARIABLE A_PAT_1 : boolean := FALSE; --DATA Low Byte VARIABLE DataLo : NATURAL RANGE 0 TO MaxData := 0; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(write) THEN DataLo := D_tmp0; PATTERN_1 := (Addr=16#555#) AND (DataLo = 16#AA#) ; PATTERN_2 := (Addr=16#2AA#) AND (DataLo = 16#55#) ; A_PAT_1 := ((Addr=16#555#) AND (ULBYPASS = '0')) OR (ULBYPASS = '1'); END IF; IF reseted /= '1' THEN next_state <= current_state; ELSE CASE current_state IS WHEN RESET => IF falling_edge(write) THEN IF (PATTERN_1) THEN next_state <= Z001; ELSIF ((Addr=16#55#) AND (DataLo=16#98#)) THEN next_state <= CFI; ELSE next_state <= RESET; END IF; END IF; WHEN Z001 => IF falling_edge(write) THEN IF (PATTERN_2) THEN next_state <= PREL_SETBWB; ELSE next_state <= RESET; END IF; END IF; WHEN PREL_SETBWB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo=16#20#)) THEN next_state <= PREL_ULBYPASS; ELSIF (A_PAT_1 AND (DataLo=16#90#)) THEN --lock bank BA_sel2 next_state <= AS; ELSIF (A_PAT_1 AND (DataLo=16#A0#)) THEN next_state <= A0SEEN; ELSIF (A_PAT_1 AND (DataLo=16#88#)) THEN next_state <= OTP; ELSIF (A_PAT_1 AND (DataLo=16#80#)) THEN next_state <= C8; ELSE next_state <= RESET; END IF; END IF; WHEN PREL_ULBYPASS => --only unlock bypass program and unlock bypass reset commands -- are allowed IF falling_edge(write) THEN --IF (A_PAT_1 AND (DataLo=16#90#)) THEN IF (DataLo=16#90#) THEN next_state <= AS; --ELSIF (A_PAT_1 AND (DataLo=16#A0#)) THEN ELSIF (DataLo=16#A0#) THEN next_state <= A0SEEN; ELSE next_state <= PREL_ULBYPASS; END IF; END IF; WHEN CFI => IF falling_edge(write) THEN IF (DataLo=16#F0#) THEN next_state <= RESET; ELSE next_state <= CFI; END IF; END IF; WHEN AS => IF falling_edge(write) THEN IF (DataLo=16#F0#) THEN next_state <= RESET;--unlock bank ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSIF (Addr=16#55#) AND (DataLo=16#98#) THEN next_state <= AS_CFI; ELSE next_state <= AS; END IF; END IF; WHEN A0SEEN => IF falling_edge(write) THEN IF (BankLocked(BA_sel2, BA) = TRUE) THEN next_state <= PGMS;--lock bank2 ELSE next_state <= PREL_ULBYPASS; END IF; ELSE next_state <= A0SEEN; END IF; WHEN OTP => IF falling_edge(write) THEN IF PATTERN_1 THEN next_state <= OTP_Z001; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= OTP_PREL; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_PREL => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#90#))THEN --lock ba_sel2 next_state <= OTP_AS; ELSIF (A_PAT_1 AND (DataLo = 16#A0#))THEN next_state <= OTP_A0SEEN; ELSIF (A_PAT_1 AND (DataLo=16#80#)) THEN next_state <= C8; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_AS => IF falling_edge(write) THEN IF (DataLo=16#F0#) THEN--unlock bank IF ESP_ACT = '1' THEN next_state <= ESP; ELSE next_state <= RESET; END IF; --comment if AS and CFI read from OTP are --not available ELSIF (Addr=16#55#) AND (DataLo=16#98#) THEN next_state <= AS_CFI; ELSE next_state <= OTP; END IF; END IF; WHEN OTP_A0SEEN => -- if wrong addres is asserted for SECSI write -- FSM goes to OTP IF falling_edge(write) THEN IF (OtpAddr(vs, SecAddr) = TRUE) THEN next_state <= PGMS; --set OTP, lock bank2 ELSE next_state <= OTP; END IF; ELSE next_state <= OTP_A0SEEN; END IF; WHEN C8 => IF falling_edge(write) THEN IF PATTERN_1 THEN next_state <= C8_Z001; ELSIF OTP_ACT = '1' THEN next_state <= OTP; ELSE next_state <= RESET; END IF; END IF; WHEN C8_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= C8_PREL; ELSIF OTP_ACT = '1' THEN next_state <= OTP; ELSE next_state <= RESET; END IF; END IF; WHEN C8_PREL => IF falling_edge(write) THEN IF OTP_ACT = '1' THEN IF DataLo=16#30# AND OtpAddr(vs, SecAddr) = TRUE THEN next_state <= SERS; ELSE next_state <= OTP; END IF; ELSE IF A_PAT_1 AND DataLo=16#10# THEN next_state <= ERS; ELSIF DataLo=16#30# THEN next_state <= SERS;--lock bank ELSE next_state <= RESET; END IF; END IF; END IF; WHEN ERS => IF rising_edge(EDONE) OR falling_edge(EERR) THEN next_state <= RESET; END IF; WHEN SERS => IF CTMOUT_out = '1' THEN next_state <= SERS_EXEC; ELSIF falling_edge(write) THEN IF OTP_ACT = '1' THEN IF ((DataLo = 16#B0#) AND (OtpAddr(vs, SecAddr) = TRUE)) THEN next_state <= ESPS; -- ESP according to datasheet ELSIF ((DataLo=16#30#) AND (OtpAddr(vs, SecAddr) = TRUE)) THEN next_state <= SERS; ELSE next_state <= OTP; END IF; ELSE IF ((DataLo = 16#B0#) AND (BankLockedForErs(LB_Ei, BA) = TRUE)) THEN next_state <= ESPS; -- ESP according to datasheet ELSIF ((DataLo=16#30#) AND BankLockedForErs(LB_Ei, BA)) THEN next_state <= SERS; ELSE next_state <= RESET;--resetBankForErs END IF; END IF; END IF; WHEN ESPS => IF (START_T1_out = '1') THEN next_state <= ESP; END IF; WHEN SERS_EXEC => IF rising_edge(EDONE) OR falling_edge(EERR) THEN IF OTP_ACT = '1' THEN next_state <= OTP; ELSE --ResetBankForErs next_state <= RESET; END IF; ELSIF EERR /= '1' THEN IF falling_edge(write) THEN IF OTP_ACT = '1' THEN IF (DataLo=16#B0# AND (OtpAddr(vs, SecAddr) = TRUE)) THEN next_state <= ESPS; END IF; ELSE IF ((DataLo=16#B0#) AND (BankLockedForErs(LB_Ei, BA) = TRUE)) THEN next_state <= ESPS; END IF; END IF; END IF; END IF; WHEN ESP => IF falling_edge(write) THEN IF OTP_ACT = '1' THEN IF (DataLo = 16#30# AND (OtpAddr(vs, SecAddr) = TRUE)) THEN next_state <= SERS_EXEC; ELSE next_state <= ESP; END IF; ELSE -- can not resume erase if unlcok = '1' IF ULBYPASS = '1' THEN IF DataLo = 16#20# THEN null; ELSIF A_PAT_1 AND DataLo = 16#A0# THEN next_state <= ESP_A0SEEN; ELSIF A_PAT_1 AND DataLo = 16#90# THEN next_state <= ESP_AS; END IF; ELSIF ((DataLo = 16#30#) AND (BankLockedForErs(LB_Ei, BA) = TRUE)) THEN next_state <= SERS_EXEC; ELSE IF Addr = 16#55# AND DataLo = 16#98# THEN next_state <= ESP_CFI; ELSIF PATTERN_1 THEN next_state <= ESP_Z001; END IF; END IF; END IF; END IF; WHEN ESP_Z001 => IF falling_edge(write) THEN IF PATTERN_2 THEN next_state <= ESP_PREL; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#20# THEN next_state <= ESP; --set ULBYPASS ELSIF A_PAT_1 AND DataLo = 16#A0# THEN next_state <= ESP_A0SEEN; ELSIF A_PAT_1 AND DataLo = 16#88# THEN next_state <= OTP; --set ESP ELSIF A_PAT_1 AND DataLo = 16#90# THEN next_state <= ESP_AS;--lock bank1 ELSE next_state <= ESP; END IF; END IF; WHEN ESP_CFI => IF falling_edge(write) THEN IF Addr = 16#55# AND DataLo = 16#98# THEN null; ELSIF DataLo = 16#F0# THEN next_state <= ESP; ELSIF ((DataLo = 16#30#) AND (BankLockedForErs(LB_Ei, BA))) THEN next_state <= SERS_EXEC; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_A0SEEN => IF falling_edge(write) THEN IF (BankLockedForErs(LB_Ei, BA)) THEN next_state <= PGMS;--lock bank2 ELSE next_state <= ESP; END IF; END IF; WHEN ESP_AS => IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN -- resret ULBYPASS --unlock bankk next_state <= ESP; ELSIF ULBYPASS = '1' THEN next_state <= ESP; ELSIF (Addr=16#55#) AND (DataLo=16#98#) THEN next_state <= AS_CFI; END IF; END IF; WHEN AS_CFI => IF falling_edge(write) THEN IF DataLo = 16#F0# THEN IF OTP_ACT = '1' THEN next_state <= OTP_AS; ELSIF ESP_ACT = '1' THEN next_state <= ESP_AS; ELSE next_state <= AS; END IF; END IF; END IF; WHEN PGMS => IF rising_edge(PDONE) OR falling_edge(PERR) THEN --UNLOCK BANK IF ESP_ACT = '1' THEN next_state <= ESP; ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSIF OTP_ACT = '1' THEN next_state <= OTP; ELSE next_state <= RESET; END IF; END IF; END CASE; END IF; END PROCESS StateGen; WP_CTRL: PROCESS(WPNeg) VARIABLE Sec_Prot_reg0 : std_logic := '0'; VARIABLE Sec_Prot_reg1 : std_logic := '0'; BEGIN --Hardware Write Protection IF falling_edge(WPNeg) THEN Sec_Prot_reg0 := Sec_Prot(first_prot); Sec_Prot_reg1 := Sec_Prot(first_prot+1); Sec_Prot(first_prot) := '1'; Sec_Prot(first_prot+1) := '1'; ELSIF rising_edge(WPNeg) THEN Sec_Prot(first_prot) := Sec_Prot_reg0; Sec_Prot(first_prot+1) := Sec_Prot_reg1; END IF; END PROCESS WP_CTRL; --------------------------------------------------------------------------- --FSM Output generation and general funcionality --------------------------------------------------------------------------- Functional : PROCESS(write, read, Addr, D_tmp0, D_tmp1, Address, SecAddr, PDONE, PERR, EDONE, EERR, START_T1_out, CTMOUT_out, RST, reseted, READY_out, gOE_n, gCE_n, current_state, BYTENeg) TYPE WBDataType IS ARRAY ( 0 TO 1) OF INTEGER RANGE -1 TO MaxData; TYPE WBAddrType IS ARRAY ( 0 TO 1) OF INTEGER RANGE -1 TO SecSize_l; VARIABLE WBData : WBDataType:= (OTHERS => 0); VARIABLE WBAddr : WBAddrType:= (OTHERS => -1); VARIABLE wr_cnt : NATURAL RANGE 0 TO 1; VARIABLE PATTERN_1 : boolean := FALSE; VARIABLE PATTERN_2 : boolean := FALSE; VARIABLE A_PAT_1 : boolean := FALSE; VARIABLE oe : boolean := FALSE; --Status reg. VARIABLE Status : std_logic_vector(7 downto 0) := (OTHERS => '0'); VARIABLE old_bit : std_logic_vector(7 downto 0); VARIABLE new_bit : std_logic_vector(7 downto 0); VARIABLE old_int : INTEGER RANGE -1 to MaxData; VARIABLE new_int : INTEGER RANGE -1 to MaxData; VARIABLE DataHi : NATURAL RANGE 0 TO MaxData := 0; VARIABLE DataLo : NATURAL RANGE 0 TO MaxData := 0; VARIABLE d_tmp : std_logic_vector(15 downto 0); VARIABLE temp : std_logic_vector(7 downto 0); VARIABLE SecSiAddr : NATURAL RANGE 0 TO SecSiSize := 0; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(write) THEN DataLo := D_tmp0; DataHi := D_tmp1; PATTERN_1 := (Addr=16#555#) AND (DataLo=16#AA#) ; PATTERN_2 := (Addr=16#2AA#) AND (DataLo=16#55#) ; A_PAT_1 := ((Addr=16#555#) AND (ULBYPASS='0')) OR (ULBYPASS='1'); END IF; oe := rising_edge(read) OR (read = '1' AND (Address'EVENT OR SecAddr'EVENT OR BYTENEg'EVENT)); IF rising_edge(reseted) THEN --ba_sel <= 0; ba_sel2 <= 0; ResetBankForErs(LB_Ei); ELSIF reseted = '1' THEN CASE current_state IS WHEN RESET => OTP_ACT <= '0'; ESP_ACT <= '0'; IF falling_edge(write) THEN null; ELSIF oe THEN MemRead(SecAddr, Address, BYTENeg, DOut_zd); END IF; --ready signal active RY_zd <= '1'; WHEN Z001 => null; WHEN PREL_SETBWB => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#20#)) THEN ULBYPASS <= '1'; ELSIF (A_PAT_1 AND (DataLo = 16#90#)) THEN ULBYPASS <= '0'; BA_sel2 <= BA; ELSIF (A_PAT_1 AND (DataLo = 16#88#)) THEN ULBYPASS <= '0'; OTP_ACT <= '1'; END IF; END IF; WHEN PREL_ULBYPASS => IF falling_edge(write) THEN IF (DataLo=16#20#) THEN ULBYPASS <= '1'; ELSIF ((DataLo=16#90#)) THEN null; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN CFI => IF falling_edge(write) THEN IF (DataLo=16#F0#) THEN --ULBYPASS <= '0'; null; END IF; ELSIF oe THEN --bank is not important CfiRead(Addr, DOut_zd); END IF; WHEN AS => IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN BA_sel2 <= 0;--unlock bank ULBYPASS <= '0'; ELSIF ULBYPASS = '1' THEN null; ELSIF (Addr=16#55#) AND (DataLo=16#98#) THEN NULL; END IF; ELSIF oe THEN IF ULBYPASS = '0' THEN IF BA_sel2 = BA THEN AsRead(Address, BYTENeg, vs, SecAddr, Dout_zd); ELSE MemRead(SecAddr, Address, BYTENeg, DOut_zd); END IF; END IF; END IF; WHEN A0SEEN => IF falling_edge(write) THEN IF (BankLocked(BA_sel2, BA) = TRUE) THEN BA_sel2 <= BA; PSTART <= '1', '0' AFTER 1 ns; WBData(0) := DataLo; WBData(1) := DataHi; WBAddr(0) := Address; SA <= SecAddr; temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); IF BYTENeg = '1' THEN WBAddr(1) := WBAddr(0) +1; ELSE WBAddr(1) := -1; END IF; END IF; END IF; WHEN OTP => OTP_ACT <= '1'; IF oe THEN --read SecSi Sector Region SecSiRead(SecAddr, Address, BYTENeg, Dout_zd); END IF; --ready signal active RY_zd <= '1'; WHEN OTP_Z001 => null; WHEN OTP_PREL => IF falling_edge(write) THEN IF (A_PAT_1 AND (DataLo = 16#90#))THEN BA_sel2 <= BA; ULBYPASS <= '0'; ELSIF (A_PAT_1 AND (DataLo=16#80#)) THEN null; END IF; END IF; WHEN OTP_AS => IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN OTP_ACT <='0'; BA_sel2 <= 0;--unlock bank when moving to ESP or reset IF (ESP_ACT = '1') THEN ULBYPASS <= '0'; --can not be accessed from ULBYPASS moda END IF; --comment if AS and CFI read from OTP are --not available ELSIF (Addr=16#55#) AND (DataLo=16#98#) THEN null; ELSE BA_sel2 <= 0; END IF; ELSIF oe THEN --comment if AS in SECSI not allowed IF BA_sel2 = BA THEN--as codes are read AsRead(Address, BYTENeg, vs, SecAddr, Dout_zd); ELSE SecSiRead(SecAddr, Address, BYTENeg, Dout_zd); END IF; END IF; WHEN OTP_A0SEEN => IF falling_edge(write) THEN IF (OtpAddr(vs, SecAddr)) THEN BA_sel2 <= BA; OTP_ACT <= '1'; PSTART <= '1', '0' AFTER 1 ns; WBData(0) := DataLo; WBData(1) := DataHi; WBAddr(0) := Address; SA <= SecAddr; temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); IF BYTENeg = '1' THEN WBAddr(1) := WBAddr(0) + 1; ELSE WBAddr(1) := -1; END IF; ELSE ASSERT FALSE REPORT "Invalid sector Address in SecSi" SEVERITY NOTE; BA_sel2 <= 0; END IF; END IF; WHEN C8 => IF falling_edge(write) THEN null; END IF; WHEN C8_Z001 => IF falling_edge(write) THEN null; END IF; WHEN C8_PREL => IF falling_edge(write) THEN IF OTP_ACT = '1' THEN IF (DataLo=16#30# AND OtpAddr(vs, SecAddr) = TRUE) THEN CTMOUT_in <= '0', '1' AFTER 1 ns; END IF; ELSE IF A_PAT_1 AND DataLo = 16#10# THEN --Start Chip Erase FOR i IN 0 TO BankNum LOOP LB_Ei(i) <= i+1; END LOOP; ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; Ers_Queue <= (OTHERS => '1'); Status := "00001000"; ELSIF DataLo=16#30# THEN --put selected sector to sec. ers. queue --start timeout AddBankForErs(BA, LB_Ei); Ers_Queue <= (OTHERS => '0'); Ers_Queue(SecAddr) <= '1'; CTMOUT_in <= '0', '1' AFTER 1 ns; END IF; END IF; END IF; WHEN ERS => IF oe THEN ----------------------------------------------------------- -- read status / embeded erase algorithm - Chip Erase ----------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; END IF; IF rising_edge(EDONE) OR falling_edge(EERR) THEN ResetBankForErs(LB_Ei); END IF; IF EERR /= '1' THEN FOR i IN 0 TO SecNum LOOP IF Sec_Prot(i) /= '1' THEN Mem((sssa(i)) TO (ssea(i))) := (OTHERS => -1); END IF; END LOOP; IF EDONE = '1' THEN FOR i IN 0 TO SecNum LOOP IF Sec_Prot(i) /= '1' THEN Mem(sssa(i) TO ssea(i)) := (OTHERS => MaxData); END IF; END LOOP; END IF; END IF; -- busy signal active RY_zd <= '0'; WHEN SERS => IF CTMOUT_out = '1' THEN CTMOUT_in <= '0'; START_T1_in <= '0'; ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; ELSIF falling_edge(write) THEN IF OTP_ACT = '1' THEN IF ((DataLo = 16#B0#) AND (OtpAddr(vs, SecAddr) = TRUE)) THEN --need to start erase process prior to suspend ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; --suspend timeout (should be 0 acc. to datasheet) START_T1_in <= '1'; ELSIF (DataLo=16#30# AND OtpAddr(vs, SecAddr) = TRUE) THEN CTMOUT_in <= '0', '1' AFTER 1 ns; END IF; ELSE IF ((DataLo = 16#B0#) AND (BankLockedForErs(LB_Ei, BA) = TRUE)) THEN --need to start erase process prior to suspend ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; --suspend timeout (should be 0 acc. to datasheet) START_T1_in <= '1'; ELSIF ((DataLo=16#30# AND BankLockedForErs(LB_Ei, BA))) THEN --AdD BANK SELECTED FOR ERASURE --AddBankForErs(BA, LB_Ei); Ers_Queue(SecAddr) <= '1'; CTMOUT_in <= '0', '1' AFTER 1 ns; ELSE --RESET ResetBankForErs(LB_Ei); --RESET ALL BANKS END IF; END IF; ELSIF oe THEN IF OTP_ACT = '1' THEN IF (OtpAddr(vs, SecAddr) = TRUE) THEN ------------------------------------------------------- --read status - sector erase timeout ------------------------------------------------------- Status(3) := '0'; DOut_zd(7 downto 0) <= Status; ELSE SecSiRead(SecAddr, Address, BYTENeg, Dout_zd); -- HIZ is read, wrong secsi address END IF; ELSE IF BankLockedForErs(LB_Ei, BA) THEN --BANK SELECTED FOR ERASURE ------------------------------------------------------- --read status - sector erase timeout ------------------------------------------------------- Status(3) := '0'; DOut_zd(7 downto 0) <= Status; ELSE MemRead(SecAddr, Address, BYTENeg, DOut_zd); END IF; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN ESPS => ESUSP <= '1';--, '0' AFTER 1 ns; CTMOUT_in <= '0'; IF (START_T1_out = '1') THEN ESP_ACT <= '1'; START_T1_in <= '0'; ELSIF oe THEN IF OTP_ACT = '1' THEN IF (OtpAddr(vs, SecAddr) = TRUE) THEN ------------------------------------------------------- --read status / erase suspend timeout - stil erasing ------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; ELSE SecSiRead(SecAddr, Address, BYTENeg, Dout_zd); -- HIZ is read, wrong secsi address END IF; ELSE IF BankLockedForErs(LB_Ei, BA) THEN --BANK SELECTED FOR ERASURE ------------------------------------------------------- --read status / erase suspend timeout - stil erasing ------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; IF Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); --toggle END IF; DOut_zd(7 downto 0) <= Status; ELSE MemRead(SecAddr, Address, BYTENeg, DOut_zd); END IF; END IF; END IF; --busy signal active RY_zd <= '0'; WHEN SERS_EXEC => IF oe THEN IF OTP_ACT = '1' THEN IF (OtpAddr(vs, SecAddr) = TRUE) THEN ------------------------------------------------------- --read status Erase Busy ------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; ELSE SecSiRead(SecAddr, Address, BYTENeg, Dout_zd); -- HIZ is read, wrong secsi address END IF; ELSE IF BankLockedForErs(LB_Ei, BA) THEN --BANK SELECTED FOR ERASURE ------------------------------------------------------- --read status Erase Busy ------------------------------------------------------- Status(7) := '0'; Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; IF Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); --toggle END IF; DOut_zd(7 downto 0) <= Status; ELSE MemRead(SecAddr, Address, BYTENeg, DOut_zd); END IF; END IF; END IF; --LB_Ei is 0,0 if OTP_ACT = '1' IF rising_edge(EDONE) OR falling_edge(EERR) THEN ResetBankForErs(LB_Ei); ESP_ACT <= '0'; END IF; IF EERR /= '1' AND (NOT EERR'EVENT) THEN IF OTP_ACT = '1' THEN SecSi := (OTHERS => -1); ELSE FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN Mem(sssa(i) TO ssea(i)) := (OTHERS => -1); END IF; END LOOP; END IF; IF EDONE = '1' THEN IF OTP_ACT = '1' THEN SecSi := (OTHERS => MaxData); ELSE FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '1' THEN Mem(sssa(i) TO ssea(i)) := (OTHERS => MaxData); END IF; END LOOP; END IF; ELSIF falling_edge(write) THEN IF OTP_ACT = '1' THEN IF (DataLo=16#B0# AND OtpAddr(vs, SecAddr) = TRUE) THEN START_T1_in <= '1'; END IF; ELSE IF (DataLo=16#B0#) AND (BankLockedForErs(LB_Ei, BA) = TRUE) THEN START_T1_in <= '1'; END IF; END IF; END IF; END IF; --busy signal active RY_zd <= '0'; WHEN ESP => ESUSP <= '0'; IF falling_edge(write) THEN IF OTP_ACT = '1' THEN IF (DataLo = 16#30# AND (OtpAddr(vs, SecAddr) = TRUE)) THEN ERES <= '1', '0' AFTER 1 ns; END IF; ELSE IF ULBYPASS = '1' THEN IF DataLo = 16#20# THEN null; END IF; ELSIF (DataLo = 16#30# AND (BankLockedForErs(LB_Ei, BA) = TRUE)) THEN --BANK SELECTED FOR ERASURE --resume erase ERES <= '1', '0' AFTER 1 ns; END IF; END IF; ELSIF oe THEN IF OTP_ACT = '1' THEN IF OtpAddr(vs, SecAddr) = TRUE THEN ------------------------------------------------------- --read status ------------------------------------------------------- Status(7) := '1'; -- Status(6) No toggle Status(5) := '0'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; ELSE SecSiRead(SecAddr, Address, BYTENeg, Dout_zd); -- HIZ is read, wrong secsi address END IF; ELSE ------------------------------------------------------- --read ------------------------------------------------------- IF (Ers_Queue(SecAddr) /= '1') THEN MemRead(SecAddr, Address, BYTENeg, DOut_zd); ELSE --------------------------------------------------- --read status --------------------------------------------------- Status(7) := '1'; -- Status(6) No toggle Status(5) := '0'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; END IF; END IF; END IF; --ready signal active RY_zd <= '1'; WHEN ESP_Z001 => null; WHEN ESP_PREL => IF falling_edge(write) THEN IF A_PAT_1 AND DataLo = 16#20# THEN ULBYPASS <= '1'; ELSIF A_PAT_1 AND DataLo = 16#88# THEN ESP_ACT <= '1'; ELSIF A_PAT_1 AND DataLo = 16#90# THEN BA_sel2 <= BA; END IF; END IF; WHEN ESP_CFI => --reset ULBYPASS IF falling_edge(write) THEN IF Addr = 16#55# AND DataLo = 16#98# THEN null; ELSIF DataLo = 16#F0# THEN ESP_ACT <= '1'; ELSIF ((DataLo = 16#30#) AND (BankLockedForErs(LB_Ei, BA))) THEN --BANK SELECTED FOR ERASURE --resume erase ERES <= '1', '0' AFTER 1 ns; ELSE ESP_ACT <= '1'; END IF; ELSIF oe THEN CfiRead(Addr, DOut_zd); END IF; WHEN ESP_A0SEEN => IF falling_edge(write) THEN IF (BankLockedForErs(LB_Ei, BA) = TRUE) THEN BA_sel2 <= BA; ESP_ACT <= '1'; PSTART <= '1', '0' AFTER 1 ns; WBData(0) := DataLo; WBData(1) := DataHi; WBAddr(0) := Address; SA <= SecAddr; temp := to_slv(DataLo, 8); Status(7) := NOT temp(7); IF BYTENeg = '1' THEN WBAddr(1) := WBAddr(0) + 1; ELSE WBAddr(1) := -1; END IF; END IF; END IF; WHEN ESP_AS => IF falling_edge(write) THEN IF (DataLo = 16#F0#) THEN -- resret ULBYPASS ULBYPASS <= '0'; BA_sel2 <= 0; --unlock bank END IF; ELSIF oe THEN IF ULBYPASS = '0' THEN IF (BA_sel2 = BA) THEN AsRead(Address, BYTENeg, vs, SecAddr, Dout_zd); ELSIF (Ers_Queue(SecAddr) /= '1') THEN MemRead(SecAddr, Address, BYTENeg, DOut_zd); ELSE --------------------------------------------------- -- if addressed sector is selected for erasure --read status --------------------------------------------------- Status(7) := '1'; -- Status(6) No toggle Status(5) := '0'; Status(2) := NOT Status(2); --toggle DOut_zd(7 downto 0) <= Status; END IF; END IF; END IF; WHEN AS_CFI => --this is CFI state, only CFI codes are visable IF falling_edge(write) THEN IF DataLo = 16#F0# THEN null; END IF; ELSIF oe THEN CfiRead(Addr, DOut_zd); END IF; WHEN PGMS => IF oe THEN IF BA_sel2 = BA THEN ------------------------------------------------------- --read status ------------------------------------------------------- Status(6) := NOT Status(6); --toggle Status(5) := '0'; --Status(2) no toggle --Status(1) := '0'; DOut_zd(7 downto 0) <= Status; ELSIF OTP_ACT = '1' THEN SecSiRead(SecAddr, Address, BYTENeg, Dout_zd); ELSE MemRead(SecAddr, Address, BYTENeg, DOut_zd); END IF; END IF; ----------------------- IF rising_edge(PDONE) OR falling_edge(PERR) THEN IF (ULBYPASS /= '1') THEN BA_sel2 <= 0; END IF; END IF; IF PERR /= '1' AND NOT(PERR'EVENT) THEN IF WBAddr(1) < 0 THEN wr_cnt := 0; ELSE wr_cnt := 1; END IF; FOR i IN wr_cnt downto 0 LOOP new_int := WBData(i); IF OTP_ACT /= '1' THEN --mem write old_int := Mem(sssa(SA) + WBAddr(i)); ELSE old_int := SecSi(WBAddr(i)); END IF; new_bit := to_slv(new_int,8); IF old_int > -1 THEN old_bit := to_slv(old_int,8); FOR j IN 0 TO 7 LOOP IF old_bit(j) = '0' THEN new_bit(j) := '0'; END IF; END LOOP; new_int := to_nat(new_bit); END IF; WBData(i) := new_int; END LOOP; FOR i IN wr_cnt downto 0 LOOP IF OTP_ACT /= '1' THEN --mem write Mem(sssa(SA) + WBAddr(i)) := -1; ELSE SecSi(WBAddr(i)) := -1; END IF; END LOOP; IF PDONE = '1' AND (NOT PERR'EVENT) THEN FOR i IN wr_cnt downto 0 LOOP IF OTP_ACT /= '1' THEN --mem write Mem(sssa(SA) + WBAddr(i)) := WBData(i); ELSE --SecSi write SecSi(WBAddr(i)) := WBData(i); END IF; WBData(i) := -1; END LOOP; END IF; --------------------------------- END IF; --busy signal active RY_zd <= '0'; END CASE; END IF; --Output Disable Control IF (gOE_n = '1') OR (gCE_n = '1') OR (RESETNeg = '0' AND RST = '0') THEN DOut_zd <= (OTHERS => 'Z'); ELSE IF (BYTENeg = '0') THEN DOut_zd(15 downto 8) <= (OTHERS =>'Z'); END IF; END IF; --Preload Control ----------------------------------------------------------------------- -- File Read Section ----------------------------------------------------------------------- IF NOW = 0 ns THEN ----------------------------------------------------------------------- --CFI array data ----------------------------------------------------------------------- --CFI query identification string CFI_array(16#10#) := 16#51#; CFI_array(16#11#) := 16#52#; CFI_array(16#12#) := 16#59#; CFI_array(16#13#) := 16#02#; CFI_array(16#14#) := 16#00#; CFI_array(16#15#) := 16#40#; CFI_array(16#16#) := 16#00#; CFI_array(16#17#) := 16#00#; CFI_array(16#18#) := 16#00#; CFI_array(16#19#) := 16#00#; CFI_array(16#1A#) := 16#00#; --system interface string CFI_array(16#1B#) := 16#27#; CFI_array(16#1C#) := 16#36#; CFI_array(16#1D#) := 16#00#; CFI_array(16#1E#) := 16#00#; CFI_array(16#1F#) := 16#04#; CFI_array(16#20#) := 16#00#; CFI_array(16#21#) := 16#0A#; CFI_array(16#22#) := 16#00#; CFI_array(16#23#) := 16#05#; CFI_array(16#24#) := 16#00#; CFI_array(16#25#) := 16#04#; CFI_array(16#26#) := 16#00#; --device geometry definition CFI_array(16#27#) := 16#16#; CFI_array(16#28#) := 16#02#; CFI_array(16#29#) := 16#00#; CFI_array(16#2A#) := 16#00#; CFI_array(16#2B#) := 16#00#; CFI_array(16#2C#) := 16#02#; CFI_array(16#2D#) := 16#07#; CFI_array(16#2E#) := 16#00#; CFI_array(16#2F#) := 16#20#; CFI_array(16#30#) := 16#00#; CFI_array(16#31#) := 16#3E#; CFI_array(16#32#) := 16#00#; CFI_array(16#33#) := 16#00#; CFI_array(16#34#) := 16#01#; CFI_array(16#35#) := 16#00#; CFI_array(16#36#) := 16#00#; CFI_array(16#37#) := 16#00#; CFI_array(16#38#) := 16#00#; CFI_array(16#39#) := 16#00#; CFI_array(16#3A#) := 16#00#; CFI_array(16#3B#) := 16#00#; CFI_array(16#3C#) := 16#00#; --primary vendor-specific extended query CFI_array(16#40#) := 16#50#; CFI_array(16#41#) := 16#52#; CFI_array(16#42#) := 16#49#; CFI_array(16#43#) := 16#31#; CFI_array(16#44#) := 16#31#; CFI_array(16#45#) := 16#00#; CFI_array(16#46#) := 16#02#; CFI_array(16#47#) := 16#01#; CFI_array(16#48#) := 16#01#; CFI_array(16#49#) := 16#04#; CFI_array(16#4A#) := 16#30#; CFI_array(16#4B#) := 16#00#; CFI_array(16#4C#) := 16#00#; CFI_array(16#4D#) := 16#85#; CFI_array(16#4E#) := 16#95#; IF TimingModel(11) = 't' THEN CFI_array(16#4F#) := 16#03#; ELSE CFI_array(16#4F#) := 16#02#; END IF; END IF; END PROCESS Functional; --------------------------------------------------------------------------- ---- File Read Section - Preload Control --------------------------------------------------------------------------- MemPreload : PROCESS -- text file input variables FILE mem_file : text is mem_file_name; FILE prot_file : text is prot_file_name; FILE secsi_file : text is secsi_file_name; VARIABLE ind : INTEGER RANGE -1 TO MemSize:= 0; VARIABLE Sec_Prot_tmp : std_logic_vector(SecNum downto 0) := (OTHERS => '0'); VARIABLE buf : line; BEGIN WAIT ON vs; ------------------------------------------------------------------------------- -----am29dl323d memory preload file format ----------------------------------- ------------------------------------------------------------------------------- -- / - comment -- @aaaaaa - stands for address within Memory -- dd -
is word to be written at Mem(aaaaaa++) -- (aaaaaa is incremented at every load) -- only first 1-7 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- IF (mem_file_name /= "none" AND UserPreload ) THEN ind := 0; Mem := (OTHERS => MaxData); WHILE (not ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '/' THEN --comment NEXT; ELSIF buf(1) = '@' THEN --address ind := h(buf(2 to 7)); ELSE IF ind <= MemSize THEN Mem(ind) := h(buf(1 to 2)); END IF; IF ind < MemSize THEN ind := ind + 1; END IF; END IF; END LOOP; END IF; ------------------------------------------------------------------------------- -----am29dl323d sector protect preload file format ----------------------------- ------------------------------------------------------------------------------- -- / - comment -- @sec - stands for sector -- d - is bit to be written at SecProt(sec++) -- (sec is incremented at every load) -- only first 1-3 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! -- @71 - if d = 1 SecSi is factory protected -- - if d = 0 Secsi is customer lockable -- sectors are numerated for top architecture, if bottom architecture is to -- be used then ai protected sector stands for a(secNum - i) protected sector -- top/bottom -- a0 ->a70 -- a1 ->a69 -- a2 ->a68 ------------------------------------------------------------------------------- IF (prot_file_name /= "none" AND UserPreload ) THEN ind := 0; FactoryProt <= '0'; Sec_Prot := (OTHERS => '0'); WHILE (not ENDFILE (prot_file)) LOOP READLINE (prot_file, buf); IF buf(1) = '/' THEN --comment NEXT; ELSIF buf(1) = '@' THEN --sector ind := h(buf(2 to 3)); ELSE IF (buf(1) = '1') THEN IF (ind > (SecNum) OR (ind < 0)) THEN FactoryProt <= '1'; ELSE Sec_Prot(ind) := '1'; END IF; END IF; IF ind <= (SecNum) AND ind >= 0 THEN ind := ind + 1; END IF; END IF; END LOOP; FOR i IN 0 TO SecNum LOOP Sec_Prot(i) := Sec_Prot(GroupProtect(i)); END LOOP; IF TimingModel(11) = 'b' THEN Sec_Prot_tmp := Sec_Prot; FOR i IN 0 TO SecNum LOOP Sec_Prot(i) := Sec_Prot_tmp(SecNum - i); END LOOP; END IF; END IF; ------------------------------------------------------------------------------- -----am29dl323d SecSi preload file format ----------------------------------- ------------------------------------------------------------------------------- -- / - comment -- @aaaa - stands for address within secSI -- dd - is word to be written at SecSI(aaaa++) -- (aaaa is incremented at every load) -- only first 1-5 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------------- -- Secure Silicon Sector Region preload IF (SecSi_file_name /= "none" AND UserPreload ) THEN SecSi := (OTHERS => MaxData); ind := 0; WHILE (not ENDFILE (SecSi_file)) LOOP READLINE (SecSi_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 TO 5)); ELSE IF ind <= SecSiSize THEN SecSi(ind) := h(buf(1 TO 2)); END IF; IF ind < SecSiSize THEN ind := ind + 1; END IF; END IF; END LOOP; END IF; END PROCESS MemPreload; ----------------------------------------------------------------------- -- Path Delay Section ----------------------------------------------------------------------- OutputDelay: PROCESS(DOut_zd) VARIABLE tOD : time := 0 ns; VARIABLE tCD : time := 0 ns; VARIABLE tAD : time := 0 ns; VARIABLE tDD : time := 0 ns; VARIABLE twait : time ;--:= 0 ns; BEGIN IF DOut_zd(0) /= 'Z' THEN --open tristate buffers tpd_from_OE := FALSE; tpd_from_CE := FALSE; Open3state := TRUE; tOD := -gOE_n'LAST_EVENT + tpd_OENeg_DQ0(trz1); tCD := -gCE_n'LAST_EVENT + tpd_CENeg_DQ0(trz1); tAD := -A'LAST_EVENT + tpd_A0_DQ0(tr10); tDD := -Din(15)'LAST_EVENT + tpd_A0_DQ0(tr10); IF BYTENeg = '0' THEN IF (tAD < tDD) THEN --twait : = tDD; ELSE twait := tAD; END IF; ELSE twait := tAD; END IF; IF tOD >= tCD AND tOD > 0 ns THEN tpd_from_OE := TRUE; ELSIF tCD >= tOD AND tCD > 0 ns THEN tpd_from_CE := TRUE; END IF; IF tAD >= 0 ns AND ((tAD >= tOD AND tpd_from_OE = TRUE) OR (tAD >= tCD AND tpd_from_CE = TRUE)) THEN Dout_z(7 downto 0) <= "XXXXXXXX", Dout_zd(7 downto 0) AFTER tAD; IF BYTENeg = '1' THEN Dout_z(15 downto 8)<= "XXXXXXXX", Dout_zd(15 downto 8) AFTER tAD; END IF; ELSE Dout_z <= Dout_zd; END IF; ELSE Open3state := FALSE; Dout_z <= Dout_zd; END IF; END PROCESS OutputDelay; RY_OUT: PROCESS(RY_zd) VARIABLE RY_GlitchData : VitalGlitchDataType; VARIABLE RY_DATA : std_logic; BEGIN IF RY_zd = '0' THEN RY_DATA := '0'; ELSE RY_DATA := 'Z'; END IF; VitalPathDelay01( OutSignal => RY, OutSignalName => "RY/BY#", OutTemp => RY_DATA, Mode => VitalTransport, GlitchData => RY_GlitchData, Paths => ( 0 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_WENeg_RY, PathCondition => TRUE), 1 => (InputChangeTime => WENeg'LAST_EVENT, PathDelay => tpd_WENeg_RY, PathCondition => TRUE), 2 => (InputChangeTime => READY_out'LAST_EVENT, PathDelay => VitalZeroDelay01, PathCondition => EDONE = '1'), 3 => (InputChangeTime => EDONE'LAST_EVENT, PathDelay => VitalZeroDelay01, PathCondition => EDONE = '1'), 4 => (InputChangeTime => PDONE'LAST_EVENT, PathDelay => VitalZeroDelay01, PathCondition => PDONE = '1') ) ); END PROCESS RY_Out; --------------------------------------------------------------------------- -- Path Delay Section for DOut signal --------------------------------------------------------------------------- D_Out_PathDelay_Gen : FOR i IN 0 TO 7 GENERATE --Dout_zd'RANGE GENERATE PROCESS(DOut_z(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; VARIABLE OE :boolean := false; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_z(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_DQ0, PathCondition =>(NOT open3state OR (open3state AND tpd_from_CE)) ), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ0, PathCondition => (NOT open3state OR (open3state AND tpd_from_OE)) ), 2 => (InputChangeTime => A'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => DOut_z(i) /= 'X'),--true), 3 => (InputChangeTime => Din(15)'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => BYTENeg='0' AND DOut_z(i) /= 'X') ) ); END PROCESS; END GENERATE D_Out_PathDelay_Gen; --------------------------------------------------------------------------- -- Path Delay Section for DOut signal --------------------------------------------------------------------------- D_Out_15_7_PathDelay_Gen : FOR i IN 8 TO 15 GENERATE PROCESS(DOut_z(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_z(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_DQ0, PathCondition => ((NOT open3state OR (open3state AND tpd_from_CE))) ), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ0, PathCondition => ( (NOT open3state OR (open3state AND tpd_from_OE))) ), 2 => (InputChangeTime => A'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => DOut_z(i) /= 'X'),--true), 3 => (InputChangeTime => BYTENeg'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BYTENeg_DQ15), PathCondition => true)--BYTENeg = '1'),--rising ) ); END PROCESS; END GENERATE D_Out_15_7_PathDelay_Gen; END BLOCK behavior; END vhdl_behavioral;