------------------------------------------------------------------------------- -- File name : am29bds320g.vhd ------------------------------------------------------------------------------- -- Copyright (C) 2004 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V1.0 A.Savic 04 Jan 16 Initial release -- V1.1 A.Savic 04 Feb 19 Preload section update - last -- memory address preload -- Memory wrap with busy sector check -- HW RESET flag update -- Erase suspended sector programming -- restriciton -- ------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FLASH -- Technology: Flash Memory -- Part: am29bds320g -- -- Description: 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only -- Simultaneous Read/Write, Burst Mode Flash Memory -- ------------------------------------------------------------------------------- -- Known Bugs: -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.all; USE FMF.conversions.all; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY am29bds320g IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A6 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A7 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A9 : VitalDelayType01 := VitalZeroDelay01; --address tipd_A10 : VitalDelayType01 := VitalZeroDelay01; --lines tipd_A11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A16 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A17 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A18 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A19 : VitalDelayType01 := VitalZeroDelay01; -- tipd_A20 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; -- data tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; -- lines tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; -- tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; -- tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_AVDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WPNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ACC : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A0_DQ0 : VitalDelayType01 := UnitDelay01; --tACC tpd_CENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z;--tCE,tCEZ tpd_OENeg_DQ0 : VitalDelayType01Z := UnitDelay01Z;--tOE,tOEZ tpd_CLK_DQ0 : VitalDelayType01 := UnitDelay01; --tBACC tpd_CLK_RDY : VitalDelayType01 := UnitDelay01; --tRACC --tsetup values tsetup_A0_CLK : VitalDelayType := UnitDelay;--tACS tsetup_A0_AVDNeg : VitalDelayType := UnitDelay;--tAAVDS,tAAS,/ tsetup_A0_WENeg : VitalDelayType := UnitDelay;--tAS,\ tsetup_DQ0_WENeg : VitalDelayType := UnitDelay;--tDS,/ tsetup_CLK_WENeg : VitalDelayType := UnitDelay;--tCSW1 tsetup_AVDNeg_WENeg : VitalDelayType := UnitDelay;--tAVSW tsetup_CENeg_CLK : VitalDelayType := UnitDelay;--tCES tsetup_CENeg_AVDNeg : VitalDelayType := UnitDelay;--tCAS tsetup_AVDNeg_CLK : VitalDelayType := UnitDelay;--tAVC tsetup_CENeg_WENeg : VitalDelayType := UnitDelay;--tCS -- For Synchronous mode, condition of no importance - will -- change within TimingCheck tsetup_CLK_WENeg_RESETNeg_EQ_1_noedge_negedge : VitalDelayType := UnitDelay;--tCSW2 --thold values thold_A0_CLK : VitalDelayType := UnitDelay;--tACH thold_A0_AVDNeg : VitalDelayType := UnitDelay;--tAAVDH,tAAH,/ thold_A0_WENeg : VitalDelayType := UnitDelay;--tAH,\ thold_DQ0_WENeg : VitalDelayType := UnitDelay;--tDH / thold_CLK_WENeg : VitalDelayType := UnitDelay;--tCHW,\ thold_AVDNeg_WENeg : VitalDelayType := UnitDelay;--tAVHC,\ thold_OENeg_WENeg : VitalDelayType := UnitDelay;--tOEH,/ thold_CENeg_WENeg : VitalDelayType := UnitDelay;--tCH,\ thold_WENeg_OENeg : VitalDelayType := UnitDelay;--tGHWL,/ thold_AVDNeg_CLK : VitalDelayType := UnitDelay;--tAVHC thold_OENeg_RESETNeg: VitalDelayType := UnitDelay;--tAVHC --tpw values: pulse width tpw_RESETNeg_negedge: VitalDelayType := UnitDelay; --tRP tpw_WENeg_negedge : VitalDelayType := UnitDelay; --tWP tpw_WENeg_posedge : VitalDelayType := UnitDelay; --tWPH tpw_AVDNeg_negedge : VitalDelayType := UnitDelay; --tAVDP --tdevice values: values for internal delays --Program Operation --word write tdevice_POW : VitalDelayType := 11.5 us; --Sector Erase Operation tWHWH2 tdevice_SEO : VitalDelayType := 400 ms; --Timing Limit Exceeded tdevice_HANG : VitalDelayType := 400 ms; --program/erase suspend timeout tdevice_START : VitalDelayType := 20 us; --sector erase command sequence timeout tdevice_CTMOUTP : VitalDelayType := 50 us; -- Initial Access for Burst Read tdevice_TIACC_ODD : VitalDelayType := 106 ns; tdevice_TIACC_EVEN : VitalDelayType := 87 ns; --device ready after Hardware reset(during embeded algorithm) tdevice_READYP : VitalDelayType := 35 us; --tReady -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING := "none"; prot_file_name : STRING := "none"; UserPreload : BOOLEAN ; LongTiming : BOOLEAN := TRUE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A20 : IN std_ulogic := 'U'; -- A19 : IN std_ulogic := 'U'; -- A18 : IN std_ulogic := 'U'; -- A17 : IN std_ulogic := 'U'; -- A16 : IN std_ulogic := 'U'; -- A15 : IN std_ulogic := 'U'; -- A14 : IN std_ulogic := 'U'; -- A13 : IN std_ulogic := 'U'; --address A12 : IN std_ulogic := 'U'; --lines A11 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A8 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- A6 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A1 : IN std_ulogic := 'U'; -- A0 : IN std_ulogic := 'U'; -- DQ15 : INOUT std_ulogic := 'U'; -- DQ14 : INOUT std_ulogic := 'U'; -- DQ13 : INOUT std_ulogic := 'U'; -- DQ12 : INOUT std_ulogic := 'U'; -- DQ11 : INOUT std_ulogic := 'U'; -- DQ10 : INOUT std_ulogic := 'U'; -- DQ9 : INOUT std_ulogic := 'U'; -- data DQ8 : INOUT std_ulogic := 'U'; -- lines DQ7 : INOUT std_ulogic := 'U'; -- DQ6 : INOUT std_ulogic := 'U'; -- DQ5 : INOUT std_ulogic := 'U'; -- DQ4 : INOUT std_ulogic := 'U'; -- DQ3 : INOUT std_ulogic := 'U'; -- DQ2 : INOUT std_ulogic := 'U'; -- DQ1 : INOUT std_ulogic := 'U'; -- DQ0 : INOUT std_ulogic := 'U'; -- CENeg : IN std_logic := 'U'; OENeg : IN std_logic := 'U'; WENeg : IN std_logic := 'U'; CLK : IN std_logic := 'U'; AVDNeg : IN std_logic := 'U'; RESETNeg : IN std_logic := 'U'; WPNeg : IN std_logic := 'U'; ACC : IN std_logic := 'U'; RDY : OUT std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of am29bds320g : ENTITY IS TRUE; END am29bds320g; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of am29bds320g IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT PartID : STRING := "am29bds320g"; CONSTANT MaxData : NATURAL := 16#FFFF#; --255; CONSTANT SecSize : NATURAL := 16#7FFF#; --32KW CONSTANT SecNum : NATURAL := 69; CONSTANT HiAddrBit : NATURAL := 20; CONSTANT AddrRANGE : NATURAL := 16#1FFFFF#; -- interconnect path delay signals SIGNAL A20_ipd : std_ulogic := 'U'; SIGNAL A19_ipd : std_ulogic := 'U'; SIGNAL A18_ipd : std_ulogic := 'U'; SIGNAL A17_ipd : std_ulogic := 'U'; SIGNAL A16_ipd : std_ulogic := 'U'; SIGNAL A15_ipd : std_ulogic := 'U'; SIGNAL A14_ipd : std_ulogic := 'U'; SIGNAL A13_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL CENeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL CLK_ipd : std_ulogic := 'U'; SIGNAL AVDNeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; SIGNAL WPNeg_ipd : std_ulogic := 'U'; SIGNAL ACC_ipd : std_ulogic := 'U'; --- internal delays SIGNAL HANG_out : std_ulogic := '0'; --Program/Erase Timing Limit SIGNAL HANG_in : std_ulogic := '0'; SIGNAL START_T1 : std_ulogic := '0'; --Start TimeOut; SUSPEND SIGNAL START_T1_in : std_ulogic := '0'; SIGNAL CTMOUT : std_ulogic := '0'; --Sector Erase TimeOut SIGNAL CTMOUT_in : std_ulogic := '0'; SIGNAL TIACC_out : std_ulogic := '0'; --Burst Initial Access SIGNAL TIACC_in : std_ulogic := '0'; SIGNAL READY : std_ulogic := '0'; -- Device ready after reset SIGNAL READY_in : std_ulogic := '0'; -- Annotate SIGNAL P1_in : std_ulogic := '0'; SIGNAL P1_out : std_ulogic := '0'; SIGNAL P2_in : std_ulogic := '0'; SIGNAL P2_out : std_ulogic := '0'; SIGNAL P3_in : std_ulogic := '0'; SIGNAL P3_out : std_ulogic := '0'; SIGNAL P4_in : std_ulogic := '0'; SIGNAL P4_out : std_ulogic := '0'; BEGIN --------------------------------------------------------------------------- -- Internal Delays --------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays HANG :VitalBuf(HANG_out,HANG_in, (tdevice_HANG ,UnitDelay)); START :VitalBuf(START_T1,START_T1_in,(tdevice_START ,UnitDelay)); CTMOUTP :VitalBuf(CTMOUT, CTMOUT_in, (tdevice_CTMOUTP ,UnitDelay)); READYP :VitalBuf(READY, READY_in, (tdevice_READYP ,UnitDelay)); --------------------------------------------------------------------------- -- Annotate --------------------------------------------------------------------------- POW : VitalBuf(P1_out,P1_in, (tdevice_POW ,UnitDelay)); SEO : VitalBuf(P2_out,P1_in, (tdevice_SEO ,UnitDelay)); TIACC_ODD : VitalBuf(P3_out,P3_in, (tdevice_TIACC_ODD ,UnitDelay)); TIACC_EVEN : VitalBuf(P4_out,P4_in, (tdevice_TIACC_EVEN ,UnitDelay)); --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_44 : VitalWireDelay (A20_ipd, A20, tipd_A20); w_0 : VitalWireDelay (A19_ipd, A19, tipd_A19); w_1 : VitalWireDelay (A18_ipd, A18, tipd_A18); w_2 : VitalWireDelay (A17_ipd, A17, tipd_A17); w_3 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_4 : VitalWireDelay (A15_ipd, A15, tipd_A15); w_5 : VitalWireDelay (A14_ipd, A14, tipd_A14); w_6 : VitalWireDelay (A13_ipd, A13, tipd_A13); w_7 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_8 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_9 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_10 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_11 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_12 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_13 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_14 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_15 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_16 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_17 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_18 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_19 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_20 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15); w_21 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14); w_22 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13); w_23 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12); w_24 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11); w_25 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10); w_26 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9); w_27 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8); w_28 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7); w_29 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6); w_30 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5); w_31 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4); w_32 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_33 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_34 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_35 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_36 : VitalWireDelay (OENeg_ipd , OENeg , tipd_OENeg); w_37 : VitalWireDelay (WENeg_ipd , WENeg , tipd_WENeg); w_38 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg); w_39 : VitalWireDelay (CENeg_ipd , CENeg , tipd_CENeg); w_40 : VitalWireDelay (WPNeg_ipd , WPNeg , tipd_WPNeg); w_41 : VitalWireDelay (ACC_ipd , ACC , tipd_ACC); w_42 : VitalWireDelay (CLK_ipd , CLK , tipd_CLK); w_43 : VitalWireDelay (AVDNeg_ipd, AVDNeg, tipd_AVDNeg); END BLOCK; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior: BLOCK PORT ( A : IN std_logic_vector(HiAddrBit downto 0) := (OTHERS => 'U'); DIn : IN std_logic_vector(15 downto 0) := (OTHERS => 'U'); DOut : OUT std_ulogic_vector(15 downto 0) := (OTHERS => 'Z'); CENeg : IN std_logic := 'U'; OENeg : IN std_logic := 'U'; WENeg : IN std_logic := 'U'; CLK : IN std_logic := 'U'; AVDNeg : IN std_logic := 'U'; RESETNeg : IN std_logic := 'U'; WPNeg : IN std_logic := 'U'; ACC : IN std_logic := 'U'; RDY : OUT std_logic := 'U' ); PORT MAP ( A(20) => A20_ipd, A(19) => A19_ipd, A(18) => A18_ipd, A(17) => A17_ipd, A(16) => A16_ipd, A(15) => A15_ipd, A(14) => A14_ipd, A(13) => A13_ipd, A(12) => A12_ipd, A(11) => A11_ipd, A(10) => A10_ipd, A(9) => A9_ipd, A(8) => A8_ipd, A(7) => A7_ipd, A(6) => A6_ipd, A(5) => A5_ipd, A(4) => A4_ipd, A(3) => A3_ipd, A(2) => A2_ipd, A(1) => A1_ipd, A(0) => A0_ipd, DIn(15) => DQ15_ipd, DIn(14) => DQ14_ipd, DIn(13) => DQ13_ipd, DIn(12) => DQ12_ipd, DIn(11) => DQ11_ipd, DIn(10) => DQ10_ipd, DIn(9) => DQ9_ipd, DIn(8) => DQ8_ipd, DIn(7) => DQ7_ipd, DIn(6) => DQ6_ipd, DIn(5) => DQ5_ipd, DIn(4) => DQ4_ipd, DIn(3) => DQ3_ipd, DIn(2) => DQ2_ipd, DIn(1) => DQ1_ipd, DIn(0) => DQ0_ipd, DOut(15) => DQ15, DOut(14) => DQ14, DOut(13) => DQ13, DOut(12) => DQ12, DOut(11) => DQ11, DOut(10) => DQ10, DOut(9) => DQ9, DOut(8) => DQ8, DOut(7) => DQ7, DOut(6) => DQ6, DOut(5) => DQ5, DOut(4) => DQ4, DOut(3) => DQ3, DOut(2) => DQ2, DOut(1) => DQ1, DOut(0) => DQ0, CENeg => CENeg_ipd, OENeg => OENeg_ipd, WENeg => WENeg_ipd, CLK => CLK_ipd, AVDNeg => AVDNeg_ipd, RESETNeg => RESETNeg_ipd, WPNeg => WPNeg_ipd, ACC => ACC_ipd, RDY => RDY ); -- State Machine : State_Type TYPE state_type IS ( RESET, PREL_SLOCK1, SEC_LOCK, Z001, PREL_SETBWB, PREL_ULBYPASS, RES_ULBYPASS, CFI, AS, A0SEEN, C8, C8_Z001, C8_PREL, ERS, SERS, ESPS, SERS_EXEC, ESP, ESP_Z001, ESP_PREL, ESP_CFI, ESP_A0SEEN, ESP_AS, PGMS ); --Flash Memory Array TYPE SecType IS ARRAY (0 TO SecSize) OF INTEGER RANGE -1 TO MaxData; TYPE MemArray IS ARRAY (0 TO SecNum) OF SecType; -- alias, four bank architecture TYPE Bank IS (ABank, BBank, CBank, DBank); TYPE burst_modes IS ( NOSYNC, CONTINUOUS, LINEAR, SYNCR); -- states SIGNAL current_state : state_type; -- SIGNAL next_state : state_type; -- SIGNAL READ_MODE : burst_modes; -- powerup SIGNAL PoweredUp : std_logic := '0'; --zero delay signals SIGNAL DOut_zd : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL DOut_Pass : std_logic_vector(15 downto 0):=(OTHERS=>'Z'); SIGNAL RY_zd : std_logic := 'Z'; --FSM control signals SIGNAL ULBYPASS : std_logic := '0'; --Unlock Bypass Active SIGNAL ESP_ACT : std_logic := '0'; --Erase Suspend --Model should never hang!!!!!!!!!!!!!!! SIGNAL HANG : std_logic := '0'; SIGNAL PDONE : std_logic := '1'; --Prog. Done SIGNAL PSTART : std_logic := '0'; --Start Programming --Program location is in protected sector SIGNAL PERR : std_logic := '0'; SIGNAL EDONE : std_logic := '1'; --Ers. Done SIGNAL ESTART : std_logic := '0'; --Start Erase SIGNAL ESUSP : std_logic := '0'; --Suspend Erase SIGNAL ERES : std_logic := '0'; --Resume Erase --All sectors selected for erasure are protected SIGNAL EERR : std_logic := '0'; --Sectors selected for erasure SIGNAL ERS_QUEUE : std_logic_vector(SecNum downto 0) := (OTHERS => '0'); --Command Register SIGNAL WRITE : std_logic := '1'; SIGNAL READ : std_logic := '1'; SIGNAL BURST : std_logic := '1'; SIGNAL ReadINIT : std_logic := '1'; SIGNAL AddrREF : std_logic := '0'; SHARED VARIABLE BankID : BANK; SHARED VARIABLE BankASEL : BANK; SHARED VARIABLE BankPROGRAM : BANK; SHARED VARIABLE BankUBPASS : BANK; SHARED VARIABLE BankSLOCK : BANK; SHARED VARIABLE BurstDelay : NATURAL RANGE 0 TO 10; SHARED VARIABLE RY_temp : std_logic; SHARED VARIABLE BankERASE : std_logic_vector(3 downto 0); SHARED VARIABLE FROMOE : BOOLEAN; SHARED VARIABLE FROMCE : BOOLEAN; SIGNAL SecAddr : NATURAL RANGE 0 TO SecNum := 0; SIGNAL SA : NATURAL RANGE 0 TO SecNum := 0; SIGNAL D_tmp : NATURAL RANGE 0 TO MaxData := 0; --Address within sector SIGNAL Addr : NATURAL RANGE 0 TO SecSize := 0; --glitch protection SIGNAL gWE_n : std_logic := '1'; SIGNAL gCE_n : std_logic := '1'; SIGNAL gOE_n : std_logic := '1'; SIGNAL OE_burst : std_logic := '1'; SIGNAL RST : std_logic := '1'; SIGNAL reseted : std_logic := '0'; SIGNAL CLKMerge : std_logic; -- Mem(SecAddr)(Address).... SHARED VARIABLE Mem : MemArray := (OTHERS =>(OTHERS=> MaxData)); SHARED VARIABLE ConfReg : std_logic_vector(19 downto 0); SHARED VARIABLE WP1 : NATURAL RANGE 0 TO SecNum; SHARED VARIABLE WP2 : NATURAL RANGE 0 TO SecNum; SHARED VARIABLE Sec_Prot : std_logic_vector(SecNum downto 0) := (OTHERS => '0'); -- timing check violation SIGNAL Viol : X01 := '0'; FUNCTION ReturnSectorID(ADDR : NATURAL) RETURN NATURAL IS VARIABLE result : NATURAL; VARIABLE conv : NATURAL; BEGIN conv := ADDR / 16#8000#; IF ( conv = 0 ) THEN result := ADDR / 16#2000#; ELSIF ( conv >= 1 ) AND ( conv <= 62 ) THEN result := 3 + conv; ELSE result := 66 + (ADDR - 16#1F8000#)/16#2000#; END IF; RETURN result; END ReturnSectorID; FUNCTION ReturnBank(ADDR : NATURAL) RETURN BANK IS VARIABLE BankResult : BANK; BEGIN CASE ADDR / 16#80000# IS WHEN 0 => BankResult := DBank; WHEN 1 => BankResult := CBank; WHEN 2 => BankResult := BBank; WHEN OTHERS => BankResult := ABank; END CASE; RETURN BankREsult; END ReturnBank; FUNCTION BusyBankE ( BankERASE : std_logic_vector; BankID : BANK ) RETURN BOOLEAN IS VARIABLE result : BOOLEAN; BEGIN result := ((BankID = DBank) AND BankERASE(0) = '1') OR ((BankID = CBank) AND BankERASE(1) = '1') OR ((BankID = BBank) AND BankERASE(2) = '1') OR ((BankID = ABank) AND BankERASE(3) = '1'); RETURN result; END BusyBankE; PROCEDURE BankE( VARIABLE BankERASE : INOUT std_logic_vector; BankID : BANK; SetBankVars : boolean ) IS BEGIN IF ( SetBankVars ) THEN IF BankID = DBank THEN BankERASE(0) := '1'; ELSIF BankID = CBank THEN BankERASE(1) := '1'; ELSIF BankID = BBank THEN BankERASE(2) := '1'; ELSE--ABank BankERASE(3) := '1'; END IF; ELSE BankERASE := "0000"; END IF; END; PROCEDURE ADDRHILO( VARIABLE AddrLOW : INOUT NATURAL RANGE 0 to ADDRRange; VARIABLE AddrHIGH : INOUT NATURAL RANGE 0 to ADDRRange; VARIABLE SectorID : NATURAL) IS BEGIN IF (SectorID <= 3) THEN AddrLOW := SectorID*16#02000#; AddrHIGH := SectorID*16#02000# + 16#01FFF#; ELSIF (SectorID > 3) AND (SectorID < 66) THEN AddrLOW := (SectorID-3)*16#08000#; AddrHIGH := (SectorID-3)*16#08000#+16#07FFF#; ELSE AddrLOW := (SectorID - 66)*16#2000# + 16#1F8000#; AddrHIGH := (SectorID - 66)*16#2000# + 16#1F8000# + 16#1FFF#; END IF; END ADDRHILO; FUNCTION READMEM(Data : INTEGER RANGE -1 TO MaxData) RETURN STD_LOGIC_VECTOR IS VARIABLE ReadData : STD_LOGIC_VECTOR(15 downto 0); BEGIN IF Data = -1 THEN ReadData := (OTHERS=>'X'); ELSE ReadData := to_slv(Data,16); END IF; RETURN ReadData; END READMEM; BEGIN ---------------------------------------------------------------------------- --Power Up time 100 ns; --------------------------------------------------------------------------- PoweredUp <= '1' AFTER 100 ns; RST <= RESETNeg AFTER 500 ns;-- WHEN RESETNeg = '0' --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS(A, Din, CENeg, OENeg, WENeg, RESETNeg, CLK, AVDNeg) -- Timing Check Variables VARIABLE Tviol_A0_CLKP : X01 := '0'; VARIABLE TD_A0_CLKP : VitalTimingDataType; VARIABLE Tviol_A0_CLKN : X01 := '0'; VARIABLE TD_A0_CLKN : VitalTimingDataType; VARIABLE Tviol_CENeg_CLKP : X01 := '0'; VARIABLE TD_CENeg_CLKP : VitalTimingDataType; VARIABLE Tviol_CENeg_CLKN : X01 := '0'; VARIABLE TD_CENeg_CLKN : VitalTimingDataType; VARIABLE Tviol_A0_AVDNeg : X01 := '0'; VARIABLE TD_A0_AVDNeg : VitalTimingDataType; VARIABLE Tviol_CENeg_AVDNeg : X01 := '0'; VARIABLE TD_CENeg_AVDNeg : VitalTimingDataType; VARIABLE Tviol_AVDNeg_CLKP : X01 := '0'; VARIABLE TD_AVDNeg_CLKP : VitalTimingDataType; VARIABLE Tviol_AVDNeg_CLKN : X01 := '0'; VARIABLE TD_AVDNeg_CLKN : VitalTimingDataType; VARIABLE Tviol_A0_WENeg : X01 := '0'; VARIABLE TD_A0_WENeg : VitalTimingDataType; VARIABLE Tviol_DQ0_WENeg : X01 := '0'; VARIABLE TD_DQ0_WENeg : VitalTimingDataType; VARIABLE Tviol_WENeg_OENeg : X01 := '0'; VARIABLE TD_WENeg_OENeg : VitalTimingDataType; VARIABLE Tviol_CENeg_WENegS : X01 := '0'; VARIABLE TD_CENeg_WENegS : VitalTimingDataType; VARIABLE Tviol_CENeg_WENegH : X01 := '0'; VARIABLE TD_CENeg_WENegH : VitalTimingDataType; VARIABLE Tviol_CLK_WENegA : X01 := '0'; VARIABLE TD_CLK_WENegA : VitalTimingDataType; VARIABLE Tviol_CLK_WENegS : X01 := '0'; VARIABLE TD_CLK_WENegS : VitalTimingDataType; VARIABLE Tviol_AVDNeg_WENeg : X01 := '0'; VARIABLE TD_AVDNeg_WENeg : VitalTimingDataType; VARIABLE Tviol_OENeg_WENeg : X01 := '0'; VARIABLE TD_OENeg_WENeg : VitalTimingDataType; VARIABLE Tviol_OENeg_RESETNeg : X01 := '0'; VARIABLE TD_OENeg_RESETNeg : VitalTimingDataType; VARIABLE Tviol_CENeg_RESETNeg : X01 := '0'; VARIABLE TD_CENeg_RESETNeg : VitalTimingDataType; VARIABLE Pviol_AVDNeg : X01 := '0'; VARIABLE PD_AVDNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RESETNeg : X01 := '0'; VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg : X01 := '0'; VARIABLE PD_WENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01; BEGIN --------------------------------------------------------------------------- -- Timing Check Section --------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Setup/Hold Check between A and CLK active edge --tACS, tACH VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => CLK, RefSignalName => "CLK", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => ConfReg(19) = '0' AND ConfReg(17) = '1' AND AVDNeg = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CLKP, Violation => Tviol_A0_CLKP ); VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => CLK, RefSignalName => "CLK", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => ConfReg(19) = '0' AND ConfReg(17) = '0' AND AVDNeg = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CLKN, Violation => Tviol_A0_CLKN ); -- CE# setup time to CLK -- tCES VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => CLK, RefSignalName => "CLK", SetupLow => tsetup_CENeg_CLK, CheckEnabled => ConfReg(19) = '0' AND ConfReg(17) = '1' AND AVDNeg = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_CLKP, Violation => Tviol_CENeg_CLKP ); VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => CLK, RefSignalName => "CLK", SetupLow => tsetup_CENeg_CLK, CheckEnabled => ConfReg(19) = '0' AND ConfReg(17) = '0' AND AVDNeg = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_CLKN, Violation => Tviol_CENeg_CLKN ); -- Setup/Hold Check between A and AVDNeg rising edge -- tAAS, tAAH VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => AVDNeg, RefSignalName => "AVDNeg", SetupHigh => tsetup_A0_AVDNeg, SetupLow => tsetup_A0_AVDNeg, HoldHigh => thold_A0_AVDNeg, HoldLow => thold_A0_AVDNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_AVDNeg, Violation => Tviol_A0_AVDNeg ); -- CE# setup time to AVD# -- tCAS VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => AVDNeg, RefSignalName => "AVDNeg", SetupLow => tsetup_CENeg_AVDNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_AVDNeg, Violation => Tviol_CENeg_AVDNeg ); -- AVD# setup/hold time to CLK -- tAVC,tAVHC VitalSetupHoldCheck ( TestSignal => AVDNeg, TestSignalName => "AVDNeg", RefSignal => CLK, RefSignalName => "CLK", SetupLow => tsetup_AVDNeg_CLK, HoldLow => thold_AVDNeg_CLK, CheckEnabled => ConfReg(19) = '0' AND ConfReg(17) = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_AVDNeg_CLKP, Violation => Tviol_AVDNeg_CLKP ); VitalSetupHoldCheck ( TestSignal => AVDNeg, TestSignalName => "AVDNeg", RefSignal => CLK, RefSignalName => "CLK", SetupLow => tsetup_AVDNeg_CLK, HoldLow => thold_AVDNeg_CLK, CheckEnabled => ConfReg(19) = '0' AND ConfReg(17) = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_AVDNeg_CLKN, Violation => Tviol_AVDNeg_CLKN ); -- Setup/Hold Check between A and WENeg falling edge -- tAS, tAH VitalSetupHoldCheck ( TestSignal => A, TestSignalName => "A", RefSignal => WENeg, RefSignalName => "WENeg", SetupHigh => tsetup_A0_WENeg, SetupLow => tsetup_A0_WENeg, HoldHigh => thold_A0_WENeg, HoldLow => thold_A0_WENeg, CheckEnabled => ConfReg(19) = '1', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_WENeg, Violation => Tviol_A0_WENeg ); -- Setup/Hold Check between DATA and WENeg rising edge -- tDS, tDH VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "DIn", RefSignal => WENeg, RefSignalName => "WENeg", SetupHigh => tsetup_DQ0_WENeg, SetupLow => tsetup_DQ0_WENeg, HoldHigh => thold_DQ0_WENeg, HoldLow => thold_DQ0_WENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_WENeg, Violation => Tviol_DQ0_WENeg ); -- WE# hold HIGH time after OE# rising edge -- tGHWL VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WENeg", RefSignal => OENeg, RefSignalName => "OENeg", HoldHigh => thold_WENeg_OENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_OENeg, Violation => Tviol_WENeg_OENeg ); -- CE# hold LOW time after WE# rising edge -- tCH VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => WENeg, RefSignalName => "WENeg", HoldLow => thold_CENeg_WENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_WENegH, Violation => Tviol_CENeg_WENegH ); -- CLK setup LOW time to WENeg falling edge ( Asynchronous ) -- tCSW1 VitalSetupHoldCheck ( TestSignal => CLK, TestSignalName => "CLK", RefSignal => WENeg, RefSignalName => "WENeg", SetupLow => tsetup_CLK_WENeg, HoldLow => thold_CLK_WENeg, CheckEnabled => ConfReg(19) = '1', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CLK_WENegA, Violation => Tviol_CLK_WENegA ); -- CLK active edge setup time to WE# falling edge ( Synchronous ) -- tCSW2 VitalSetupHoldCheck ( TestSignal => CLK, TestSignalName => "CLK", RefSignal => WENeg, RefSignalName => "WENeg", SetupLow => tsetup_CLK_WENeg_RESETNeg_EQ_1_noedge_negedge, HoldLow => thold_CLK_WENeg, CheckEnabled => ConfReg(19) = '0' AND AVDNeg = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CLK_WENegS, Violation => Tviol_CLK_WENegS ); -- CE# setup LOW time before WE# falling edge -- tCS VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => WENeg, RefSignalName => "WENeg", SetupLow => tsetup_CENeg_WENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_WENegS, Violation => Tviol_CENeg_WENegS ); -- AVD# setup/hold LOW time around WE# falling edge -- tAVSW, tAVHW VitalSetupHoldCheck ( TestSignal => AVDNeg, TestSignalName => "AVDNeg", RefSignal => WENeg, RefSignalName => "WENeg", SetupLow => tsetup_AVDNeg_WENeg, HoldLow => thold_AVDNeg_WENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_AVDNeg_WENeg, Violation => Tviol_AVDNeg_WENeg ); -- OE# hold HIGH time after WE# rising edge -- tOEH VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OENeg", RefSignal => WENeg, RefSignalName => "WENeg", HoldHigh => thold_OENeg_WENeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_WENeg, Violation => Tviol_OENeg_WENeg ); -- OE# hold HIGH time after RESET rising edge -- tRH VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OENeg", RefSignal => RESETNeg, RefSignalName => "RESETNeg", HoldHigh => thold_OENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_RESETNeg, Violation => Tviol_OENeg_RESETNeg ); -- CE# hold HIGH time after RESET rising edge -- tRH VitalSetupHoldCheck ( TestSignal => CENeg, TestSignalName => "CENeg", RefSignal => RESETNeg, RefSignalName => "RESETNeg", HoldHigh => thold_OENeg_RESETNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CENeg_RESETNeg, Violation => Tviol_CENeg_RESETNeg ); -- PulseWidth Check for AVDNeg VitalPeriodPulseCheck ( TestSignal => AVDNeg, TestSignalName => "AVDNeg", PulseWidthLow => tpw_AVDNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AVDNeg, Violation => Pviol_AVDNeg ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESETNeg", PulseWidthLow => tpw_RESETNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg, Violation => Pviol_RESETNeg ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_WENeg_negedge, PulseWidthHigh => tpw_WENeg_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg, Violation => Pviol_WENeg ); Violation := Tviol_A0_CLKP OR Tviol_A0_CLKN OR Tviol_CENeg_CLKP OR Tviol_CENeg_CLKN OR Tviol_A0_AVDNeg OR Tviol_CENeg_AVDNeg OR Tviol_AVDNeg_CLKP OR Tviol_AVDNeg_CLKN OR Tviol_A0_WENeg OR Tviol_DQ0_WENeg OR Tviol_WENeg_OENeg OR Tviol_CENeg_WENegS OR Tviol_CENeg_WENegH OR Tviol_CLK_WENegA OR Tviol_CLK_WENegS OR Tviol_AVDNeg_WENeg OR Tviol_OENeg_WENeg OR Tviol_OENeg_RESETNeg OR Tviol_CENeg_RESETNeg OR Pviol_WENeg OR Pviol_RESETNeg OR Pviol_AVDNeg ; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS VITALTimingCheck; --------------------------------------------------------------------------- -- Burst Access Time control --------------------------------------------------------------------------- TIACCB : PROCESS(TIACC_in) BEGIN IF TIACC_in = '0' THEN TIACC_out <= '0'; ELSE IF ( TimingModel(14) = '8' OR TimingModel(14) = '3' ) AND Addr mod 2 = 0 THEN TIACC_out <= '1' AFTER (tdevice_TIACC_EVEN - 1 ns); ELSE TIACC_out <= '1' AFTER (tdevice_TIACC_ODD - 1 ns); END IF; END IF; END PROCESS TIACCB; --------------------------------------------------------------------------- -- sequential process for reset control and FSM state transition --------------------------------------------------------------------------- StateTransition : PROCESS(next_state, RESETNeg, RST, READY, PDone, EDone, PoweredUp) VARIABLE R : std_logic := '0'; --prog or erase in progress VARIABLE E : std_logic := '0'; --reset timming error BEGIN IF PoweredUp='1' THEN --Hardware reset timing control IF falling_edge(RESETNeg) THEN E := '0'; IF (PDONE='0' OR EDONE='0') THEN --if program or erase in progress READY_in <= '1'; R :='1'; ELSE READY_in <= '0'; R:='0'; --prog or erase not in progress END IF; ELSIF rising_edge(RESETNeg) AND RST='1' THEN --RESET# pulse < tRP READY_in <= '0'; R := '0'; E := '1'; END IF; IF RESETNeg='1' AND ( R='0' OR (R='1' AND READY='1')) THEN current_state <= next_state; READY_in <= '0'; E := '0'; R := '0'; reseted <= '1'; ELSIF (R='0' AND RESETNeg='0' AND RST='0')OR (R='1' AND RESETNeg='0' AND RST='0' AND READY='0')OR (R='1' AND RESETNeg='1' AND RST='0' AND READY='0')OR (R='1' AND RESETNeg='1' AND RST='1' AND READY='0') THEN --no state transition while RESET# low current_state <= RESET; --reset start reseted <= '0'; END IF; ELSE current_state <= RESET; -- reset reseted <= '0'; E := '0'; R := '0'; END IF; END PROCESS StateTransition; --------------------------------------------------------------------------- --Glitch Protection: Inertial Delay does not propagate pulses <5ns --------------------------------------------------------------------------- gWE_n <= WENeg AFTER 5 ns WHEN WENeg = '0' ELSE WENeg; gCE_n <= CENeg AFTER 5 ns WHEN CENeg = '0' ELSE CENeg; gOE_n <= OENeg AFTER 5 ns WHEN OENeg = '0' ELSE OENeg; --------------------------------------------------------------------------- -- Latch open detection, needed for burst sequences --------------------------------------------------------------------------- OE_burst <= OENeg AFTER tpd_OENeg_DQ0(trz0) WHEN OENeg = '0' ELSE '1'; --------------------------------------------------------------------------- -- Clock active edge --> CLKMerge rising edge, needed for burst sequences --------------------------------------------------------------------------- CLKGen : PROCESS(CLK) BEGIN IF ConfReg(17) = '0' THEN CLKMerge <= NOT CLK; ELSE CLKMerge <= CLK; END IF; END PROCESS CLKGen; --------------------------------------------------------------------------- -- Address Latch and Bus Cycle Decode --------------------------------------------------------------------------- BusCycleDecode : PROCESS(A, gWE_n, gCE_n, gOE_n, WENeg, CENeg, OENeg, reseted, AVDNeg, CLKMerge) VARIABLE AddressLatched : NATURAL RANGE 0 TO ADDRRange; VARIABLE AddrLO : NATURAL RANGE 0 TO ADDRRange; VARIABLE AddrHI : NATURAL RANGE 0 TO ADDRRange; VARIABLE READCYCLE : BOOLEAN; VARIABLE WRITECYCLE : BOOLEAN; VARIABLE LATCHEDR : BOOLEAN; VARIABLE LATCHEDW : BOOLEAN; VARIABLE LATCHED : BOOLEAN; VARIABLE SecLatched : NATURAL; BEGIN IF reseted='1' AND ConfReg(19) = '1' THEN -- Asynchronous Mode address latch IF RESETNeg /= '0' AND ((falling_edge(gWE_n) OR falling_edge(gCE_n)) AND gCE_n = '0' AND gWE_n = '0' AND OENeg = '1' AND AVDNeg = '0') THEN AddressLatched := to_nat(A); SecLatched := ReturnSectorID(AddressLatched); ADDRHILO(AddrLO, AddrHI, SecLatched); END IF; IF ( (falling_edge(AVDNeg) OR (A'EVENT AND AVDNeg = '0')) AND CENeg = '0' AND WENeg = '1') THEN -- tACC count AddrREF <= NOT AddrREF; END IF; IF (rising_edge(AVDNeg) AND CENeg = '0' AND WENeg = '1') OR (A'EVENT AND AVDNeg = '0' AND WENeg = '1' AND CENeg = '0') THEN AddressLatched := to_nat(A); SecLatched := ReturnSectorID(AddressLatched); ADDRHILO(AddrLO, AddrHI, SecLatched); END IF; IF ((falling_edge(OENeg) OR falling_edge(CENeg) OR (A'EVENT AND AVDNeg = '0')) AND WENeg = '1' AND CENeg = '0' AND OENeg = '0') THEN -- Initiate READ SecAddr <= ReturnSectorID(AddressLatched); BankID := ReturnBank(AddressLatched); Addr <= AddressLatched - AddrLO; READ <= '0', '1' AFTER 1 ns; END IF; IF RESETNeg /= '0' AND ((rising_edge(gWE_n) AND gCE_n = '0') OR (rising_edge(gCE_n) AND gWE_n = '0') OR (rising_edge(gWE_n) AND rising_edge(gCE_n))) AND OENeg = '1' THEN -- WRITE operation SecAddr <= ReturnSectorID(AddressLatched); BankID := ReturnBank(AddressLatched); Addr <= AddressLatched - AddrLO; D_tmp <= to_nat(Din(15 downto 0)); WRITE <= '0', '1' AFTER 1 ns; END IF; ELSIF reseted = '1' AND ConfReg(19) = '0' THEN IF falling_edge(AVDNeg) THEN LATCHED := FALSE; READCYCLE := FALSE; WRITECYCLE := FALSE; RY_temp := '0'; END IF; --Initiate READ (Burst mode) IF rising_edge(CLKMerge) AND READCYCLE THEN READCYCLE := FALSE; BURST <= '0', '1' AFTER 2 ns; END IF; -- Synchronous CLK active edge address latch IF rising_edge(CLKMerge) AND gWE_n = '1' AND --gOE_n = '1' AND gCE_n = '0' AND AVDNeg = '0' AND NOT LATCHED THEN READCYCLE := TRUE; LATCHED := TRUE; AddressLatched := to_nat(A); SecAddr <= ReturnSectorID(AddressLatched); BankID := ReturnBank(AddressLatched); SecLatched := ReturnSectorID(AddressLatched); ADDRHILO(AddrLO, AddrHI, SecLatched); Addr <= AddressLatched - AddrLO; BurstDelay := 0; TIACC_in <= '0', '1' AFTER 1 ns; AddrREF <= NOT AddrREF; IF OENeg = '0' THEN READ <= '0', '1' AFTER 1 ns; END IF; END IF; -- Synchronous AVD# rising edge address latch IF rising_edge(AVDNeg) AND gWE_n = '1' AND --gOE_n = '1' AND gCE_n = '0' AND NOT LATCHED THEN READCYCLE := TRUE; LATCHED := TRUE; AddressLatched := to_nat(A); SecAddr <= ReturnSectorID(AddressLatched); BankID := ReturnBank(AddressLatched); SecLatched := ReturnSectorID(AddressLatched); ADDRHILO(AddrLO, AddrHI, SecLatched); Addr <= AddressLatched - AddrLO; BurstDelay := 1; TIACC_in <= '0', '1' AFTER 1 ns; AddrREF <= NOT AddrREF; IF OENeg = '0' THEN READ <= '0', '1' AFTER 1 ns; END IF; END IF; -- Synchronous WRITE cycle IF (falling_edge(gWE_n) OR falling_edge(gCE_n)) AND gCE_n = '0' AND gWE_n = '0' AND gOE_n = '1' AND READCYCLE THEN READCYCLE := FALSE; WRITECYCLE := TRUE; END IF; -- Synchronous WRITE operation data latch IF ((rising_edge(gWE_n) AND gCE_n = '0') OR (rising_edge(gCE_n) AND gWE_n = '0') OR (rising_edge(gWE_n) AND rising_edge(gCE_n))) AND WRITECYCLE AND gOE_n = '1' AND RESETNeg /= '0' THEN WRITECYCLE := FALSE; SecAddr <= ReturnSectorID(AddressLatched); BankID := ReturnBank(AddressLatched); SecLatched := ReturnSectorID(AddressLatched); ADDRHILO(AddrLO, AddrHI, SecLatched); Addr <= AddressLatched - AddrLO; D_tmp <= to_nat(Din(15 downto 0)); WRITE <= '0', '1' AFTER 1 ns; END IF; -- Inititate READ, Syncronous mode IF (falling_edge(OENeg) AND WENeg = '1' AND CENeg = '0') THEN -- Initiate READ SecAddr <= ReturnSectorID(AddressLatched); BankID := ReturnBank(AddressLatched); Addr <= AddressLatched - AddrLO; READ <= '0', '1' AFTER 1 ns; END IF; END IF; END PROCESS BusCycleDecode; --------------------------------------------------------------------------- -- Timing control for the Program operation -- start/ suspend/ resume --------------------------------------------------------------------------- ProgTime :PROCESS(PSTART, reseted) --ESP_ACT VARIABLE pow : time; BEGIN pow := tdevice_POW; IF rising_edge(reseted) THEN PDONE <= '1'; -- reset done, programming terminated ELSIF reseted = '1' THEN IF rising_edge(PSTART) AND PDONE='1' THEN IF ( Sec_Prot(SA) = '1' AND (Ers_queue(SA) = '0' OR ESP_ACT = '0') AND NOT (ACC = '0') AND NOT (WPNeg = '0' AND (SA = WP1 OR SA = WP2))) THEN PDONE <= '0', '1' AFTER pow; ELSE PERR <= '1', '0' AFTER 1 us; END IF; END IF; END IF; END PROCESS ProgTime; --------------------------------------------------------------------------- -- Timing control for the Erase Operations --------------------------------------------------------------------------- ErsTime :PROCESS(ESTART, ESUSP, ERES, reseted)--,Ers_Queue VARIABLE cnt : NATURAL RANGE 0 TO SecNum := 0; VARIABLE elapsed : time; VARIABLE duration : time; VARIABLE start : time; VARIABLE seo : time; BEGIN IF NOT LongTiming THEN seo := tdevice_SEO/10000; ELSE seo := tdevice_SEO; END IF; IF rising_edge(reseted) THEN EDONE <= '1'; -- reset done, ERASE terminated ELSIF reseted = '1' THEN IF rising_edge(ESTART) AND EDONE = '1' THEN cnt := 0; FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '0' AND NOT (WPNeg = '0' AND ( i = WP1 OR i = WP2 )) AND NOT (ACC = '0') THEN cnt := cnt +1; END IF; END LOOP; IF cnt > 0 THEN elapsed := 0 ns; duration := cnt* seo; EDONE <= '0', '1' AFTER duration; start := NOW; ELSE EERR <= '1', '0' AFTER 100 us; END IF; ELSIF rising_edge(ESUSP) AND EDONE = '0' THEN elapsed := NOW - start; duration := duration - elapsed; EDONE <= '0'; ELSIF rising_edge(ERES) AND EDONE = '0' THEN start := NOW; EDONE <= '0', '1' AFTER duration; END IF; END IF; END PROCESS; --------------------------------------------------------------------------- -- Main Behavior Process -- combinational process for next state generation --------------------------------------------------------------------------- StateGen :PROCESS(WRITE, PDONE, EDONE, HANG, CTMOUT, BURST, START_T1, reseted, PERR, EERR, gCE_n, AVDNeg, RST) VARIABLE PATTERN_1 : BOOLEAN := FALSE; VARIABLE PATTERN_2 : BOOLEAN := FALSE; VARIABLE A_PAT_1 : BOOLEAN := FALSE; VARIABLE Data : NATURAL RANGE 0 TO MaxData := 0; VARIABLE DataLo : NATURAL RANGE 0 TO 16#FF# := 0; VARIABLE BURST_TR : BOOLEAN; VARIABLE SYNCREAD : BOOLEAN; BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(WRITE) THEN Data := D_tmp; DataLo := D_tmp mod 16#100#; PATTERN_1 := (Addr mod 16#1000# = 16#555#) AND (DataLo = 16#AA#) ; PATTERN_2 := (Addr mod 16#1000# = 16#2AA#) AND (DataLo = 16#55#) ; A_PAT_1 := (Addr mod 16#1000# = 16#555#); END IF; BURST_TR := FALSE; SYNCREAD := FALSE; IF falling_edge(RST) AND RESETNeg = '0' THEN READ_MODE <= NOSYNC; END IF; IF reseted /= '1' THEN next_state <= current_state; ELSE CASE current_state IS WHEN RESET => IF falling_edge(WRITE) THEN IF (PATTERN_1)THEN next_state <= Z001; ELSIF ((Addr mod 16#100# = 16#55#) AND (DataLo=16#98#))THEN next_state <= CFI; ELSIF (DataLo = 16#60#) THEN next_state <= PREL_SLOCK1; ELSE next_state <= RESET; END IF; END IF; IF falling_edge(BURST) THEN BURST_TR := TRUE; END IF; WHEN PREL_SLOCK1 => IF falling_edge(WRITE) THEN IF (DataLo = 16#60# AND BankID = BankSLOCK) THEN next_state <= SEC_LOCK; ELSE next_state <= RESET; END IF; END IF; WHEN SEC_LOCK => IF falling_edge(WRITE) THEN IF (DataLo = 16#F0#) THEN next_state <= RESET; END IF; ELSIF falling_edge(BURST) THEN IF BankID /= BankSLOCK THEN BURST_TR := TRUE; END IF; END IF; WHEN Z001 => IF falling_edge(WRITE) THEN IF (PATTERN_2) THEN next_state <= PREL_SETBWB; ELSE next_state <= RESET; END IF; END IF; WHEN PREL_SETBWB => IF falling_edge(WRITE) THEN IF (A_PAT_1 AND (DataLo = 16#20#)) THEN next_state <= PREL_ULBYPASS; ELSIF (A_PAT_1 AND (DataLo = 16#90#)) THEN next_state <= AS; ELSIF (A_PAT_1 AND (DataLo = 16#A0#)) THEN next_state <= A0SEEN; ELSIF (A_PAT_1 AND (DataLo = 16#80#)) THEN next_state <= C8; ELSIF (A_PAT_1 AND (DataLo = 16#C0#)) THEN next_state <= RESET; ELSE next_state <= RESET; END IF; END IF; WHEN PREL_ULBYPASS => IF falling_edge(WRITE) THEN IF (DataLo = 16#A0#) THEN next_state <= A0SEEN; ELSIF (DataLo = 16#80#) THEN next_state <= C8_PREL; ELSIF (DataLo = 16#90# AND BankID = BankUBPASS) THEN next_state <= RES_ULBYPASS; ELSE next_state <= PREL_ULBYPASS; END IF; ELSIF falling_edge(BURST) THEN IF BankID /= BankUBPASS THEN BURST_TR := TRUE; END IF; END IF; WHEN RES_ULBYPASS => IF falling_edge(WRITE) THEN IF (DataLo = 16#00#) THEN next_state <= RESET; ELSE next_state <= PREL_ULBYPASS; END IF; END IF; WHEN CFI => IF falling_edge(WRITE) THEN IF (DataLo = 16#F0#) THEN next_state <= RESET; ELSE next_state <= CFI; END IF; ELSIF falling_edge(BURST) THEN SYNCREAD := TRUE; END IF; WHEN AS => IF falling_edge(WRITE) THEN IF (DataLo = 16#F0#) THEN next_state <= RESET; ELSE next_state <= AS; END IF; ELSIF falling_edge(BURST) THEN IF BankID = BankASEL THEN SYNCREAD := TRUE; ELSE BURST_TR := TRUE; END IF; END IF; WHEN A0SEEN => IF falling_edge(WRITE) THEN IF ULBYPASS = '1' THEN IF BankID = BankUBPASS THEN next_state <= PGMS; ELSE next_state <= PREL_ULBYPASS; END IF; ELSE next_state <= PGMS; END IF; END IF; WHEN C8 => IF falling_edge(WRITE) THEN IF PATTERN_1 THEN next_state <= C8_Z001; ELSE next_state <= RESET; END IF; END IF; WHEN C8_Z001 => IF falling_edge(WRITE) THEN IF PATTERN_2 THEN next_state <= C8_PREL; ELSE next_state <= RESET; END IF; END IF; WHEN C8_PREL => IF falling_edge(WRITE) THEN IF ( A_PAT_1 OR ULBYPASS = '1' ) AND DataLo = 16#10# THEN next_state <= ERS; ELSIF DataLo = 16#30# AND NOT (ULBYPASS = '1' AND BankID /= BankUBPASS ) THEN next_state <= SERS; ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; END IF; WHEN ERS => IF rising_edge(EDONE) OR falling_edge(EERR) THEN IF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; END IF; IF falling_edge(BURST) THEN SYNCREAD := TRUE; END IF; WHEN SERS => IF CTMOUT'EVENT AND CTMOUT = '1' THEN next_state <= SERS_EXEC; ELSIF falling_edge(WRITE) THEN IF (DataLo = 16#B0# AND BusyBankE(BankERASE,BankID)) THEN next_state <= ESP; -- ESP according to datasheet ELSIF (DataLo = 16#30#) THEN next_state <= SERS; ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS;--C8_PREL; ELSE next_state <= RESET; END IF; END IF; IF falling_edge(BURST) THEN IF BusyBankE(BankERASE,BankID) THEN SYNCREAD := TRUE; ELSE BURST_TR := TRUE; END IF; END IF; WHEN ESPS => IF (START_T1 = '1') THEN next_state <= ESP; END IF; IF falling_edge(BURST) THEN IF BusyBankE(BankERASE,BankID) THEN SYNCREAD := TRUE; ELSE BURST_TR := TRUE; END IF; END IF; WHEN SERS_EXEC => IF rising_edge(EDONE) OR falling_edge(EERR) THEN IF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; ELSIF EERR /= '1' THEN IF falling_edge(WRITE) THEN IF DataLo = 16#B0# AND BusyBankE(BankERASE,BankID) THEN next_state <= ESPS; END IF; END IF; END IF; IF falling_edge(BURST) THEN IF BusyBankE(BankERASE,BankID) THEN SYNCREAD := TRUE; ELSE BURST_TR := TRUE; END IF; END IF; WHEN ESP => IF falling_edge(WRITE) THEN IF DataLo = 16#30# AND BusyBankE(BankERASE,BankID) THEN next_state <= SERS_EXEC; ELSIF (DataLo = 16#A0#) AND ULBYPASS = '1' AND BankID = BankUBPASS THEN next_state <= ESP_A0SEEN; ELSIF Addr mod 16#100# = 16#55# AND DataLo = 16#98# THEN next_state <= ESP_CFI; ELSIF PATTERN_1 THEN next_state <= ESP_Z001; END IF; ELSIF falling_edge(BURST) THEN IF BusyBankE(BankERASE,BankID) AND Ers_Queue(SecAddr) = '1' THEN SYNCREAD := TRUE; ELSE BURST_TR := TRUE; END IF; END IF; WHEN ESP_Z001 => IF falling_edge(WRITE) THEN IF PATTERN_2 THEN next_state <= ESP_PREL; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_PREL => IF falling_edge(WRITE) THEN IF A_PAT_1 AND DataLo = 16#A0# THEN next_state <= ESP_A0SEEN; ELSIF A_PAT_1 AND DataLo = 16#90# THEN next_state <= ESP_AS; ELSE next_state <= ESP; END IF; END IF; WHEN ESP_CFI => IF falling_edge(WRITE) AND DataLo = 16#F0# THEN next_state <= ESP; ELSIF falling_edge(BURST) THEN SYNCREAD := TRUE; END IF; WHEN ESP_A0SEEN => IF falling_edge(WRITE) AND Ers_Queue(SecAddr) /= '1' THEN next_state <= PGMS; --set ESP END IF; WHEN ESP_AS => IF falling_edge(WRITE) THEN IF DataLo = 16#F0# THEN -- reset ULBYPASS next_state <= ESP; END IF; ELSIF falling_edge(BURST) THEN IF BankID = BankASEL THEN SYNCREAD := TRUE; ELSIF BusyBankE(BankERASE,BankID) AND BankID /= BankASEL AND Ers_Queue(SecAddr) = '1' THEN SYNCREAD := TRUE; ELSE BURST_TR := TRUE; END IF; END IF; WHEN PGMS => IF rising_edge(PDONE) OR falling_edge(PERR) THEN IF ESP_ACT = '1' THEN next_state <= ESP; ELSIF ULBYPASS = '1' THEN next_state <= PREL_ULBYPASS; ELSE next_state <= RESET; END IF; END IF; IF falling_edge(BURST) THEN IF BankID = BankPROGRAM THEN SYNCREAD := TRUE; ELSIF BankID /= BankPROGRAM AND ESP_ACT = '1' AND BusyBankE(BankERASE,BankID) AND Ers_Queue(SecAddr) = '1' THEN SYNCREAD := TRUE; ELSE BURST_TR := TRUE; END IF; END IF; END CASE; IF (rising_edge(gCE_n) OR falling_edge(AVDNeg)) AND (READ_MODE /= NOSYNC) THEN READ_MODE <= NOSYNC; END IF; IF BURST_TR THEN IF ConfReg(16 downto 15) = "00" THEN READ_MODE <= CONTINUOUS; ELSE READ_MODE <= LINEAR; END IF; ReadINIT <= '0', '1' AFTER 2 ns; ELSIF SYNCREAD THEN READ_MODE <= SYNCR; ReadINIT <= '0', '1' AFTER 2 ns; END IF; END IF; END PROCESS StateGen; --------------------------------------------------------------------------- --FSM Output generation and general funcionality --------------------------------------------------------------------------- Functional : PROCESS(WRITE, READ, BURST, Addr, SecAddr, CLKMerge,ReadINIT, PDONE, EDONE, HANG, START_T1, CTMOUT, RST, reseted, READY, gOE_n, current_state, OENeg, CENeg, WENeg, PERR, EERR) --Common Flash Interface Query codes TYPE CFItype IS ARRAY (16#10# TO 16#5B#) OF NATURAL RANGE 0 TO 16#FF#; TYPE ASELtype IS ARRAY (0 TO 16#0F#) OF NATURAL RANGE 0 TO 16#FFFF#; --Program VARIABLE CFI_array : CFItype :=(OTHERS=>0); VARIABLE ASEL_array : ASELtype :=(OTHERS=>0); VARIABLE WData : INTEGER RANGE -1 TO MaxData; VARIABLE WAddr : INTEGER RANGE -1 TO SecSize; VARIABLE cnt : NATURAL RANGE 0 TO 31 := 0; VARIABLE PATTERN_1 : boolean := FALSE; VARIABLE PATTERN_2 : boolean := FALSE; VARIABLE A_PAT_1 : boolean := FALSE; VARIABLE oe : boolean := FALSE; --Status reg. VARIABLE Status : std_logic_vector(15 downto 0) := (OTHERS=>'0'); VARIABLE old_bit : std_logic_vector(15 downto 0); VARIABLE new_bit : std_logic_vector(15 downto 0); VARIABLE old_int : INTEGER RANGE -1 to MaxData; VARIABLE new_int : INTEGER RANGE -1 to MaxData; VARIABLE wr_cnt : NATURAL RANGE 0 TO 31; VARIABLE Data : NATURAL RANGE 0 TO MaxData := 0; VARIABLE DOut_temp : std_logic_vector(15 downto 0); VARIABLE ASELInd : NATURAL RANGE 0 TO 15; VARIABLE temp : std_logic_vector(7 downto 0); VARIABLE tmpA : std_logic_vector(HiAddrBit downto 0); VARIABLE AddrCFI : NATURAL; VARIABLE tmpSect : NATURAL RANGE 0 TO SecNum; VARIABLE ReadOK : BOOLEAN; VARIABLE RYData : STD_LOGIC; VARIABLE ReadData : std_logic_vector(15 downto 0); VARIABLE DataLo : NATURAL RANGE 0 TO MaxData; VARIABLE AddrLOW : NATURAL RANGE 0 TO ADDRRange; VARIABLE AddrHIGH : NATURAL RANGE 0 TO ADDRRange; VARIABLE AddrCHECK : NATURAL RANGE 0 TO ADDRRange; VARIABLE BurstAddr : NATURAL RANGE 0 TO ADDRRange; VARIABLE BurstSect : NATURAL RANGE 0 TO SecNum; VARIABLE BurstBorder : NATURAL RANGE 0 TO 32; VARIABLE WrapMax : NATURAL RANGE 0 TO 128; VARIABLE BankCHECK : BANK; VARIABLE SectorCHECK : NATURAL RANGE 0 TO SecNum; VARIABLE BusyBOUND : BOOLEAN; VARIABLE CrossData : std_logic_vector(15 downto 0); VARIABLE BusyDelay : NATURAL RANGE 0 TO 10; VARIABLE BoundDelay : NATURAL RANGE 0 TO 10; VARIABLE PriorIACC : NATURAL RANGE 0 TO 10; VARIABLE LATCHED_3E_3F : BOOLEAN; VARIABLE OutputD : std_logic_vector(15 downto 0); VARIABLE SyncData : std_logic_vector(15 downto 0); BEGIN ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- IF falling_edge(WRITE) THEN Data := D_tmp; DataLo := Data mod 16#100#; PATTERN_1 := (Addr mod 16#1000# = 16#555#) AND (DataLo = 16#AA#) ; PATTERN_2 := (Addr mod 16#1000# = 16#2AA#) AND (DataLo = 16#55#) ; A_PAT_1 := (Addr mod 16#1000# = 16#555#); END IF; oe := falling_edge(READ); IF falling_edge(RST) AND RESETNeg = '0' THEN BankERASE := "0000"; ConfReg(19 downto 12) := "11100101"; ULBYPASS <= '0'; ESP_ACT <= '0'; END IF; IF falling_edge(BURST) THEN BurstBorder := to_nat(ConfReg(16 downto 15))*8; IF ConfReg(16 downto 15) = "11" THEN BurstBorder := 32; END IF; BurstAddr := Addr; BurstSect := SecAddr; BurstDelay := BurstDelay + to_nat(ConfReg(14 downto 12)) + 1; RY_temp := '0'; IF ConfReg(16 downto 15) = "00" THEN LATCHED_3E_3F := FALSE; PriorIACC := 0; BusyDelay := 0; BoundDelay := 0; IF TimingModel(14) = '8' OR TimingModel(14) = '3' THEN IF BurstAddr mod 16#40# = 16#3D# THEN PriorIACC := 1; ELSIF BurstAddr mod 16#40# = 16#3E# THEN PriorIACC := 2; LATCHED_3E_3F := TRUE; ELSIF BurstAddr mod 16#40# = 16#3F# THEN PriorIACC := 3; LATCHED_3E_3F := TRUE; ELSIF BurstAddr mod 2 = 1 THEN PriorIACC := 1; END IF; END IF; ELSE WrapMax := 128; IF (TimingModel(14) = '8' OR TimingModel(14) = '3') AND BurstAddr mod 2 = 1 THEN BurstDelay := BurstDelay + 1; END IF; END IF; END IF; IF reseted = '1' THEN CASE current_state IS WHEN RESET => ESP_ACT <= '0'; IF oe THEN DOut_zd <= READMEM(Mem(SecAddr)(Addr)); ELSIF falling_edge(WRITE) AND DataLo = 16#60# THEN BankSLOCK := BankID; END IF; WHEN PREL_SLOCK1 => NULL; WHEN SEC_LOCK => IF falling_edge(WRITE) AND BankID = BankSLOCK AND DataLo = 16#60# THEN temp := to_slv(Addr,8); Sec_Prot(SecAddr) := temp(6); END IF; IF BankID = BankSLOCK THEN OutputD := (OTHERS => 'Z'); ELSE OutputD := READMEM(Mem(SecAddr)(Addr)); END IF; IF oe THEN SyncData := OutputD; DOut_zd <= OutputD; END IF; WHEN Z001 => NULL; WHEN PREL_SETBWB => IF falling_edge(WRITE) THEN IF (A_PAT_1 AND (DataLo = 16#20#)) THEN ULBYPASS <= '1'; BankUBPASS := BankID; ELSIF (A_PAT_1 AND DataLo = 16#90#) THEN BankASEL := BankID; ELSIF (A_PAT_1 AND DataLo = 16#C0#) THEN tmpSect := SecAddr; ADDRHILO(AddrLOW, AddrHIGH, tmpSect); tmpA := to_slv((AddrLOW+Addr),HiAddrBit+1); ConfReg(19 downto 12) := tmpA(19 downto 12); IF to_nat(tmpA(14 downto 12)) = 0 THEN ConfReg(18) := '1'; END IF; END IF; END IF; WHEN PREL_ULBYPASS => IF BankID = BankUBPASS THEN OutputD := (OTHERS => 'Z'); ELSE OutputD := READMEM(Mem(SecAddr)(Addr)); END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; WHEN RES_ULBYPASS => IF falling_edge(WRITE) AND (DataLo = 16#00#) THEN ULBYPASS <= '0'; END IF; WHEN CFI => OutputD := (OTHERS=>'0'); IF (( Addr >= 16#10#) AND (Addr <= 16#3C#)) OR ((Addr >= 16#40#) AND (Addr <= 16#50#)) OR ((Addr >= 16#57#) AND (Addr <= 16#5B#)) THEN OutputD(7 downto 0) := to_slv(CFI_array(Addr),8); ELSIF oe THEN--OR falling_edge(BURST) THEN ASSERT FALSE REPORT "Invalid CFI query address" SEVERITY warning; END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; WHEN AS => IF BankID = BankASEL THEN ASELInd := Addr mod 16; IF ASELInd = 0 OR ASELInd = 1 OR ASELInd = 3 OR ASELInd = 16#0E# OR ASELInd = 16#0F# THEN OutputD := to_slv(ASEL_array(ASELInd),16); ELSIF ASELInd = 2 THEN OutputD := to_slv(0,16); OutputD(0) := NOT Sec_Prot(SecAddr); END IF; ELSE OutputD := READMEM(Mem(SecAddr)(Addr)); END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; WHEN A0SEEN => IF falling_edge(WRITE) AND NOT (ULBYPASS = '1' AND BankID /= BankUBPASS) THEN BankPROGRAM := BankID; PSTART <= '1', '0' AFTER 1 ns; WData := Data; WAddr := Addr; SA <= SecAddr; temp := to_slv(Data, 8); Status(7) := NOT temp(7); END IF; WHEN C8 => NULL; WHEN C8_Z001 => NULL; WHEN C8_PREL => IF falling_edge(WRITE) THEN IF ( A_PAT_1 OR ULBYPASS = '1' )AND DataLo = 16#10# THEN --Start Chip Erase ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; Ers_Queue <= (OTHERS => '1'); Status := "0000000000001000"; ELSIF ( DataLo = 16#30# ) AND NOT (ULBYPASS = '1' AND BankID /= BankUBPASS) THEN BankE(BankERASE, BankID, TRUE); --put selected sector to sec. ers. queue --start timeout Ers_Queue <= (OTHERS => '0'); Ers_Queue(SecAddr) <= '1'; CTMOUT_in <= '0', '1' AFTER 2 ns; END IF; END IF; WHEN ERS => ----------------------------------------------------------- -- read status / embeded erase algorithm - Chip Erase ----------------------------------------------------------- IF oe THEN--OR falling_edge(BURST) THEN Status(5) := '0'; Status(3) := '1'; Status(6) := NOT Status(6); --toggle Status(7) := '0'; Status(2) := NOT Status(2); --toggle OutputD := Status; END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; IF falling_edge(EDONE) AND EERR /= '1' THEN FOR i IN 0 TO SecNum LOOP IF ( Sec_Prot(i) /= '0' AND NOT (WPNeg = '0' AND ( i = WP1 OR i = WP2 )) AND NOT (ACC = '0')) THEN Mem(i):= (OTHERS => -1); END IF; END LOOP; END IF; IF rising_edge(EDONE) AND EERR /= '1' THEN FOR i IN 0 TO SecNum LOOP IF ( Sec_Prot(i) /= '0' AND NOT (WPNeg = '0' AND ( i = WP1 OR i = WP2 )) AND NOT (ACC = '0')) THEN Mem(i):= (OTHERS => MaxData); END IF; END LOOP; END IF; WHEN SERS => IF CTMOUT'EVENT AND CTMOUT = '1' THEN CTMOUT_in <= '0'; START_T1_in <= '0'; ESTART <= '1', '0' AFTER 1 ns; ESUSP <= '0'; ERES <= '0'; ELSIF falling_edge(WRITE) THEN IF (DataLo = 16#B0#) AND BusyBankE(BankERASE,BankID) THEN ESTART <= '1', '0' AFTER 1 ns; ERES <= '0'; --suspend timeout (should be 0 according to datasheet) START_T1_in <= '0';--- ?????????????????? ESUSP <= '1' AFTER 2 ns, '0' AFTER 3 ns; ELSIF (DataLo = 16#30#) THEN -- No restriction AND BankID = BankErase THEN BankE(BankERASE, BankID, TRUE); CTMOUT_in <= '0', '1' AFTER 2 ns; Ers_Queue(SecAddr) <= '1'; END IF; END IF; Status(7) := '1'; Status(3) := '0'; IF BusyBankE(BankERASE,BankID) THEN OutputD := Status; ELSE OutputD := READMEM(Mem(SecAddr)(Addr)); END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; WHEN ESPS => IF (START_T1 = '1') THEN ESP_ACT <= '1'; START_T1_in <= '0'; END IF; ----------------------------------------------------------- --read status / erase suspend timeout - stil erasing ----------------------------------------------------------- IF oe THEN--OR falling_edge(BURST) THEN Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; IF Ers_Queue(SecAddr) = '1' THEN Status(7) := '0'; Status(2) := NOT Status(2); --toggle END IF; IF BusyBankE(BankERASE,BankID) THEN OutputD := Status; ELSE OutputD := READMEM(Mem(SecAddr)(Addr)); END IF; END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; WHEN SERS_EXEC => IF oe THEN--OR falling_edge(BURST) THEN Status(6) := NOT Status(6); --toggle Status(5) := '0'; Status(3) := '1'; IF Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); --toggle Status(7) := '0'; END IF; IF BusyBankE(BankERASE,BankID) THEN OutputD := Status; ELSE OutputD := READMEM(Mem(SecAddr)(Addr)); END IF; END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; IF falling_edge(EDONE) AND EERR /= '1' THEN FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '0' AND NOT (WPNeg = '0' AND ( i = WP1 OR i = WP2 )) AND NOT (ACC = '0') THEN Mem(i) := (OTHERS => -1); END IF; END LOOP; END IF; IF rising_edge(EDONE) AND EERR /= '1' THEN FOR i IN Ers_Queue'RANGE LOOP IF Ers_Queue(i) = '1' AND Sec_Prot(i) /= '0' AND NOT (WPNeg = '0' AND ( i = WP1 OR i = WP2 )) AND NOT (ACC = '0') THEN Mem(i) := (OTHERS => MaxData); END IF; END LOOP; END IF; IF rising_edge(EDONE) THEN BankERASE := "0000"; END IF; IF falling_edge(WRITE) AND EERR /= '1' AND DataLo = 16#B0# THEN START_T1_in <= '1'; ESUSP <= '1', '0' AFTER 1 ns; END IF; WHEN ESP => IF falling_edge(WRITE) THEN IF DataLo = 16#30# AND BusyBankE(BankERASE,BankID) THEN --resume erase ERES <= '1', '0' AFTER 1 ns; END IF; END IF; IF oe THEN--OR falling_edge(BURST) THEN Status(5) := '0'; IF Ers_Queue(SecAddr) = '1' THEN Status(7) := '1'; Status(2) := NOT Status(2); --toggle END IF; IF ( Ers_Queue(SecAddr) /= '1' ) THEN OutputD := READMEM(Mem(SecAddr)(Addr)); ELSE OutputD := Status; END IF; END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; WHEN ESP_Z001 => NULL; WHEN ESP_PREL => IF falling_edge(WRITE) AND DataLo = 16#90# THEN BankASEL := BankID; END IF; WHEN ESP_CFI => OutputD := (OTHERS=>'0'); IF ((Addr >= 16#10#) AND (Addr <= 16#3C#)) OR ((Addr >= 16#40#) AND (Addr <= 16#50#)) OR ((Addr >= 16#57#) AND (Addr <= 16#5B#)) THEN OutputD(7 downto 0) := to_slv(CFI_array(Addr) ,8); ELSIF oe THEN--OR falling_edge(BURST) THEN ASSERT FALSE REPORT "Invalid CFI query address" SEVERITY warning; END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; WHEN ESP_A0SEEN => IF falling_edge(WRITE) AND Ers_Queue(SecAddr) /= '1' THEN ESP_ACT <= '1'; PSTART <= '1', '0' AFTER 1 ns; WData := Data; WAddr := Addr; SA <= SecAddr; temp := to_slv(Data, 8); Status(7) := NOT temp(7); BankPROGRAM := BankID; END IF; WHEN ESP_AS => IF BankID = BankASEL THEN ASELInd := Addr mod 16; IF ASELInd = 0 OR ASELInd = 1 OR ASELInd = 3 OR ASELInd = 16#0E# OR ASELInd = 16#0F# THEN OutputD := to_slv(ASEL_array(ASELInd),16); ELSIF ASELInd = 2 THEN OutputD := to_slv(0,16); OutputD(0) := NOT Sec_Prot(SecAddr); END IF; ELSIF BankID /= BankASEL AND BusyBankE(BankERASE,BankID) AND ( oe ) AND Ers_Queue(SecAddr) = '1' THEN Status(7) := '1'; Status(5) := '0'; Status(2) := NOT Status(2); --toggle OutputD := Status; ELSE OutputD := READMEM(Mem(SecAddr)(Addr)); END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; WHEN PGMS => IF oe THEN--OR falling_edge(BURST) THEN Status(6) := NOT Status(6); --toggle Status(5) := '0'; -- Status(2) no toggle Status(1) := '0'; IF BankID = BankPROGRAM THEN OutputD := Status; ELSIF BankID /= BankPROGRAM AND ESP_ACT = '1' AND BusyBankE(BankERASE,BankID) AND Ers_Queue(SecAddr) = '1' THEN Status(2) := NOT Status(2); OutputD := Status; ELSE OutputD := READMEM(Mem(SecAddr)(Addr)); END IF; END IF; IF oe THEN DOut_zd <= OutputD; SyncData := OutputD; END IF; IF PERR/='1' THEN new_int:= WData; old_int:=Mem(SA)(WAddr); IF new_int>-1 THEN new_bit:=to_slv(new_int,16); IF old_int>-1 THEN old_bit:=to_slv(old_int,16); FOR j IN 0 TO 15 LOOP IF old_bit(j) = '0' THEN new_bit(j):='0'; END IF; END LOOP; new_int:=to_nat(new_bit); END IF; WData:= new_int; ELSE WData := -1; END IF; IF NOT falling_edge(PERR) THEN Mem(SA)(WAddr) := -1; END IF; IF HANG /= '1' AND PDONE = '1' AND (NOT PERR'EVENT) THEN Mem(SA)(WAddr) := WData; END IF; END IF; END CASE; IF falling_edge(READ) AND READ_MODE /= NOSYNC THEN DOut_temp := DOut_zd; END IF; CASE READ_MODE IS WHEN LINEAR => IF (rising_edge(CLKMerge) OR falling_edge(ReadINIT)) THEN -- Linear Burst 8/16/32 ReadOK := OE_burst = '0' AND CENeg = '0' AND WENeg ='1'; IF ( BurstDelay > 0 ) THEN -- IND/WAIT# active one cycle before data BurstDelay := BurstDelay - 1; IF ConfReg(18) = '0' AND BurstDelay = 1 THEN IF ReadOK THEN RY_zd <= '1'; ELSE RY_temp := '1'; END IF; ELSE IF ReadOK THEN RY_zd <= '0'; ELSE RY_temp := '0'; END IF; END IF; END IF; IF BurstDelay = 0 AND WrapMax > 0 AND TIACC_out = '1' THEN WrapMax := WrapMax - 1; ReadData := READMEM(Mem(BurstSect)(BurstAddr)); RYData := '1'; IF ReadOK THEN Dout_zd <= ReadData; RY_zd <= RYData; ELSE Dout_temp := ReadData; RY_temp := RYData; END IF; BurstAddr := BurstAddr + 1; IF BurstAddr mod BurstBorder = 0 THEN BurstAddr := BurstAddr - BurstBorder; END IF; ELSIF BurstDelay = 0 AND WrapMax = 0 THEN IF ReadOK THEN RY_zd <= '0'; ELSE RY_temp := '0'; END IF; END IF; IF TIACC_out /= '1' THEN IF ReadOK THEN RY_zd <= '0'; ELSE RY_temp := '0'; END IF; END IF; END IF; WHEN CONTINUOUS => --Continuous Burst IF (rising_edge(CLKMerge) OR falling_edge(ReadINIT)) THEN ReadOK := OE_burst = '0' AND CENeg = '0' AND WENeg ='1'; IF PriorIACC > 0 THEN PriorIACC := PriorIACC -1 ; IF ReadOK THEN RY_zd <= '0'; ELSE RY_temp := '0'; END IF; ELSIF BurstDelay > 0 THEN BurstDelay := BurstDelay - 1; RYData := '0'; IF ConfReg(18) = '0' AND BurstDelay = 1 THEN RYData := '1'; END IF; IF ReadOK THEN RY_zd <= RYData; ELSE RY_temp := RYData; END IF; ELSIF BoundDelay > 0 THEN BoundDelay := BoundDelay - 1; IF BusyDelay > 0 THEN IF (BoundDelay = 1) THEN RYData := NOT ConfReg(18); ELSE RYData := ConfReg(18); END IF; ELSE IF (BoundDelay = 2) THEN RYData := NOT ConfReg(18); ELSE RYData := '1'; END IF; END IF; IF ReadOK THEN RY_zd <= RYData; ELSE RY_temp := RYData; END IF; ELSIF BusyDelay > 0 THEN IF BusyDelay = 2 THEN BusyDelay := 1; RYData := NOT ConfReg(18); ELSE -- No progress RYData := '1'; ReadData := CrossData; END IF; IF ReadOK THEN Dout_zd <= ReadData; RY_zd <= RYData; ELSE Dout_temp := ReadData; RY_temp := RYData; END IF; END IF; IF BurstDelay = 0 AND BoundDelay = 0 AND BusyDelay = 0 AND TIACC_out = '1' THEN ReadData := READMEM(Mem(BurstSect)(BurstAddr)); IF ((BurstAddr mod 16#40# = 16#3F#) OR (BurstAddr mod 16#40#=16#3E# AND ConfReg(18)='0')) AND (TimingModel(14) = '8' OR TimingModel(14) = '3') AND NOT LATCHED_3E_3F THEN RYData := '0'; ELSE RYData := '1'; END IF; IF (BurstAddr mod 16#40# = 16#3F#) THEN ADDRHILO(AddrLOW, AddrHIGH, BurstSect); AddrCHECK := AddrLOW + BurstAddr; --Bank Boundary Check --Reduced Handshake devices BankCHECK := ReturnBank((AddrCHECK+1) mod (ADDRRange+1)); SectorCHECK := ReturnSectorID((AddrCHECK+1) mod (ADDRRange+1)); BusyBOUND := FALSE; BoundDelay := 0; BusyDelay := 0; IF (BankCHECK = BankASEL AND (current_state=AS OR current_state=ESP_AS))THEN CrossData := to_slv(ASEL_array(0),16); BusyBOUND := TRUE; ELSIF (BankCHECK=BankPROGRAM AND current_state=PGMS) THEN CrossData := Status; BusyBOUND := TRUE; ELSIF (BusyBankE(BankERASE,BankCHECK) AND (current_state=SERS OR current_state=SERS_EXEC OR current_state=ESPS)) THEN CrossData := Status; BusyBOUND := TRUE; ELSIF (BankCHECK=BankUBPASS AND current_state=PREL_ULBYPASS) THEN CrossData := (OTHERS => 'Z'); BusyBOUND := TRUE; ELSIF (BankCHECK=BankSLOCK AND current_state = SEC_LOCK) THEN CrossData := (OTHERS => 'Z'); BusyBOUND := TRUE; ELSIF (Ers_Queue(SectorCHECK) = '1' AND (current_state = ESP OR current_state = ESPS)) THEN CrossData := Status; BusyBOUND := TRUE; ELSIF (Ers_Queue(SectorCHECK) = '1' AND (current_state = PGMS AND ESP_ACT = '1')) THEN CrossData := Status; CrossData(7) := '1'; BusyBOUND := TRUE; END IF; IF BusyBOUND AND ReturnBank(AddrCHECK)/= BankCHECK THEN IF NOT LATCHED_3E_3F AND (TimingModel(14) = '8' OR TimingModel(14) = '3') THEN BoundDelay := 2; END IF; BusyDelay := 2; --?? ELSIF BusyBOUND AND ReturnSectorID(AddrCHECK)/= SectorCHECK THEN IF NOT LATCHED_3E_3F AND (TimingModel(14) = '8' OR TimingModel(14) = '3') THEN BoundDelay := 2; END IF; BusyDelay := 2; --?? ELSIF ReturnBank(AddrCHECK)/= BankCHECK AND NOT LATCHED_3E_3F AND (TimingModel(14) = '8' OR TimingModel(14) = '3' ) THEN -- Bank Boundary, NOT Program/Erase bank BoundDelay := 3; BusyDelay := 0; ELSIF (TimingModel(14) = '8' OR TimingModel(14) = '3') AND NOT LATCHED_3E_3F THEN -- Reduced Hadshake devices -- 3F address boundary latency BoundDelay := 3; BusyDelay := 0; END IF; --Sector Boundary Check --Address Update IF ReturnSectorID(AddrCHECK) /= ReturnSectorID((AddrCHECK+1) mod (ADDRRange+1)) THEN IF BurstSect = SecNum THEN BurstSect := 0; ELSE BurstSect := BurstSect + 1; END IF; BurstAddr := 0; ELSE BurstAddr := BurstAddr + 1; END IF; IF LATCHED_3E_3F THEN LATCHED_3E_3F := FALSE; END IF; IF BoundDelay = 0 AND BusyDelay > 0 AND ConfReg(18) = '0' THEN RYData := '0'; END IF; ELSE BurstAddr := BurstAddr + 1; END IF; IF ReadOK THEN Dout_zd <= ReadData; RY_zd <= RYData; ELSE Dout_temp := ReadData; RY_temp := RYData; END IF; END IF; IF TIACC_out /= '1' THEN IF ReadOK THEN RY_zd <= '0'; ELSE RY_temp := '0'; END IF; END IF; END IF; WHEN SYNCR => -- sync READ operation, does not iterate like BURST MODE -- Data returned after initial delay IF (rising_edge(CLKMerge) OR falling_edge(ReadINIT)) THEN ReadOK := OE_burst = '0' AND CENeg = '0' AND WENeg ='1'; IF ( BurstDelay > 0 ) THEN BurstDelay := BurstDelay - 1; IF ConfReg(18) = '0' AND BurstDelay = 1 THEN IF ReadOK THEN RY_zd <= '1'; ELSE RY_temp := '1'; END IF; ELSE IF ReadOK THEN RY_zd <= '0'; ELSE RY_temp := '0'; END IF; END IF; END IF; IF BurstDelay = 0 THEN IF ReadOK THEN Dout_zd <= SyncData; RY_zd <= '1'; ELSE Dout_temp := SyncData; RY_temp := '1'; END IF; END IF; END IF; WHEN NOSYNC => NULL; END CASE; END IF; --Output Disable Control IF (((rising_edge(CENeg) OR rising_edge(OENeg)) AND (WENeg = '1')) OR ((falling_edge(RST) AND RESETNeg = '0'))) THEN IF DOut_zd(0) /= 'Z' THEN DOut_temp := DOut_zd; RY_temp := RY_zd; END IF; DOut_zd <= (OTHERS=>'Z'); RY_zd <= 'Z'; END IF; -- Sync mode IF ((falling_edge(CENeg) AND OENeg = '0') OR ( falling_edge(OENeg) AND CENeg = '0')) AND gWE_n = '1' AND RST = '1' AND ConfReg(19) = '0' THEN Dout_zd <= Dout_temp; RY_zd <= RY_temp; END IF; IF NOW = 0 ns THEN ------------------------------------------------------------------- --CFI array data / AM29BDS320G DEVICE SPECIFIC ------------------------------------------------------------------- --CFI query identification string CFI_array(16#10#) := 16#51#; CFI_array(16#11#) := 16#52#; CFI_array(16#12#) := 16#59#; CFI_array(16#13#) := 16#02#; CFI_array(16#14#) := 16#00#; CFI_array(16#15#) := 16#40#; CFI_array(16#16#) := 16#00#; CFI_array(16#17#) := 16#00#; CFI_array(16#18#) := 16#00#; CFI_array(16#19#) := 16#00#; CFI_array(16#1A#) := 16#00#; --system interface string CFI_array(16#1B#) := 16#17#; CFI_array(16#1C#) := 16#19#; CFI_array(16#1D#) := 16#00#; CFI_array(16#1E#) := 16#00#; CFI_array(16#1F#) := 16#04#; CFI_array(16#20#) := 16#00#; CFI_array(16#21#) := 16#09#; CFI_array(16#22#) := 16#00#; CFI_array(16#23#) := 16#04#; CFI_array(16#24#) := 16#00#; CFI_array(16#25#) := 16#04#; CFI_array(16#26#) := 16#00#; --device geometry definition CFI_array(16#27#) := 16#16#; CFI_array(16#28#) := 16#01#; CFI_array(16#29#) := 16#00#; CFI_array(16#2A#) := 16#00#; CFI_array(16#2B#) := 16#00#; CFI_array(16#2C#) := 16#03#; CFI_array(16#2D#) := 16#03#; CFI_array(16#2E#) := 16#00#; CFI_array(16#2F#) := 16#04#; CFI_array(16#30#) := 16#00#; CFI_array(16#31#) := 16#3D#; CFI_array(16#32#) := 16#00#; CFI_array(16#33#) := 16#00#; CFI_array(16#34#) := 16#01#; CFI_array(16#35#) := 16#03#; CFI_array(16#36#) := 16#00#; CFI_array(16#37#) := 16#04#; CFI_array(16#38#) := 16#00#; CFI_array(16#39#) := 16#00#; CFI_array(16#3A#) := 16#00#; CFI_array(16#3B#) := 16#00#; CFI_array(16#3C#) := 16#00#; --primary vendor-specific extended query CFI_array(16#40#) := 16#50#; CFI_array(16#41#) := 16#52#; CFI_array(16#42#) := 16#49#; CFI_array(16#43#) := 16#31#; CFI_array(16#44#) := 16#33#; CFI_array(16#45#) := 16#04#; CFI_array(16#46#) := 16#02#; CFI_array(16#47#) := 16#01#; CFI_array(16#48#) := 16#00#; CFI_array(16#49#) := 16#05#; CFI_array(16#4A#) := 16#33#; CFI_array(16#4B#) := 16#01#; CFI_array(16#4C#) := 16#00#; CFI_array(16#4D#) := 16#B5#; CFI_array(16#4E#) := 16#C5#; IF TimingModel(12) = 'T' THEN CFI_array(16#4F#) := 16#03#; ELSE CFI_array(16#4F#) := 16#02#; END IF; CFI_array(16#50#) := 16#00#; CFI_array(16#57#) := 16#04#; CFI_array(16#58#) := 16#13#; CFI_array(16#59#) := 16#10#; CFI_array(16#5A#) := 16#10#; CFI_array(16#5B#) := 16#13#; ASEL_array(16#00#) := 16#0001#; ASEL_array(16#01#) := 16#227E#; IF TimingModel(14) = '9' OR TimingModel(14) = '4' THEN -- Standard Handshake ASEL_array(16#03#) := 16#0042#; ELSIF TimingModel(14) = '8' OR TimingModel(14) = '3' THEN -- REduced Handshake ASEL_array(16#03#) := 16#0043#; END IF; IF TimingModel(14) = '8' OR TimingModel(14) = '9' THEN --1.8 V IF TimingModel(12) = 'T' THEN ASEL_array(16#0E#) := 16#2222#; ELSE ASEL_array(16#0E#) := 16#2223#; END IF; ELSIF TimingModel(14) = '4' OR TimingModel(14) = '3' THEN --3 V IF TimingModel(12) = 'T' THEN ASEL_array(16#0E#) := 16#2214#; ELSE ASEL_array(16#0E#) := 16#2234#; END IF; END IF; ASEL_array(16#0F#) := 16#2200#; END IF; END PROCESS Functional; --------------------------------------------------------------------------- ---- File Read Section - Preload Control --------------------------------------------------------------------------- MemPreload : PROCESS -- text file input variables FILE mem_file : text is mem_file_name; FILE prot_file : text is prot_file_name; VARIABLE ind : NATURAL RANGE 0 TO SecSize:= 0; VARIABLE buf : line; VARIABLE BASE : NATURAL; VARIABLE addr_ind : NATURAL; VARIABLE sec_ind : NATURAL RANGE 0 TO SecNum; VARIABLE offset : NATURAL RANGE 0 TO SecSize; VARIABLE A_Low : NATURAL; VARIABLE A_High : NATURAL; CONSTANT MemSize : NATURAL := 16#1FFFFF#;--Bytes BEGIN ConfReg := "11100101000000000000"; BankERASE := "0000"; IF (mem_file_name /= "none" AND UserPreload ) THEN ind := 0; addr_ind := 0; Mem := (OTHERS => (OTHERS => MaxData)); --#am29bds320g memory file -- // - comment -- @aaaa - stands for address -- dddd - is word to be written at Mem(aaaa++) -- (aaaa is incremented at every load) -- 32 words region for BURST mode testing starts at 00B0 -- NO EMPTY LINES -- preload sector 7 in bank A with recognizable data -- for burst read mode testing -- address range to be filled is 90h to FFh -- Fill region near bank boundary B-->A with recognizable data -- preload last sector in bank B (50) and first one in bank A (51) -- for burst read mode with bank cross testing -- address range to be filled is 16#7FF0# to 16#7FFF# for within -- sector 50 and 16#00# to 16#6F# in sector 51 -- verify bank boundary read bahavior with crosses to busy and -- non-busy bank WHILE (not ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '/' THEN --comment NEXT; ELSIF buf(1) = '@' THEN --address addr_ind := h(buf(2 to 7)); sec_ind := ReturnSectorID(addr_ind); ADDRHILO(A_Low,A_High,sec_ind); offset := addr_ind - A_Low; ELSE IF addr_ind <= MemSize THEN Mem(sec_ind)(offset) := h(buf(1 to 4)); addr_ind := (addr_ind + 1) mod (MemSize + 1); sec_ind := ReturnSectorID(addr_ind); ADDRHILO(A_Low,A_High,sec_ind); offset := addr_ind - A_Low; END IF; END IF; END LOOP; END IF; --am29bds320g_prot sector protect file -- // - comment -- @aa - stands for sector identification 0..45 -- If nothing specified for sector group in this file the -- corresponding group will be unprotected ( default ). -- NO empty lines -- Note that sector number length must be strictly 2 -- ( 01 insted of 1 etc. ) IF (prot_file_name /= "none" AND UserPreload ) THEN ind := 0; Sec_Prot := (OTHERS => '1'); WHILE (not ENDFILE (prot_file)) LOOP READLINE (prot_file, buf); IF buf(1) = '/' THEN --comment NEXT; ELSIF buf(1) = '@' THEN --address ind := h(buf(2 to 3)); ELSE IF (buf(1) = '1') THEN Sec_Prot(ind) := '0'; END IF; ind := ind + 1; END IF; END LOOP; END IF; IF TimingModel(12) = 'T' THEN WP1 := SecNum; WP2 := SecNum -1; ELSE WP1 := 0; WP2 := 1; END IF; WAIT; END PROCESS MemPreload; ----------------------------------------------------------------------- -- Path Delay Section ----------------------------------------------------------------------- RY_OUT: PROCESS(RY_zd) VARIABLE RY_GlitchData : VitalGlitchDataType; VARIABLE SWITCH : BOOLEAN; VARIABLE CEDQ_t : TIME; VARIABLE OEDQ_t : TIME; BEGIN IF RY_zd /= 'Z' THEN IF ConfReg(19) = '0' THEN SWITCH := FALSE; ELSE SWITCH := TRUE; CEDQ_t := -CENeg'LAST_EVENT + tpd_CENeg_DQ0(trz0); OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_DQ0(trz0); END IF; ELSE SWITCH := FALSE; END IF; IF ConfReg(19) = '0' OR RY_zd = 'Z' THEN VitalPathDelay01Z( OutSignal => RDY, OutSignalName => "RY/BY#", OutTemp => RY_zd, Mode => VitalTransport, GlitchData => RY_GlitchData, Paths => ( 0 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ0, PathCondition => (NOT SWITCH OR (SWITCH AND OEDQ_t >= CEDQ_t))), 1 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_DQ0, PathCondition => (NOT SWITCH OR (SWITCH AND CEDQ_t >= OEDQ_t))), 2 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CLK_RDY), PathCondition => OENeg = '0' AND CENeg = '0' AND ConfReg(17) = '1' AND (ConfReg(19) = '0' AND CLK = '1' AND OE_burst = '0')), 3 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CLK_RDY), PathCondition => OENeg = '0' AND CENeg = '0' AND ConfReg(17) = '0' AND (ConfReg(19) = '0' AND CLK = '0' AND OE_burst = '0')) ) ); END IF; END PROCESS RY_Out; --------------------------------------------------------------------------- -- Path Delay Section for DOut signal --------------------------------------------------------------------------- DQValueGen : PROCESS( DOut_zd ) VARIABLE ValidData : std_logic_vector(15 downto 0); VARIABLE CEDQ_t : TIME; VARIABLE OEDQ_t : TIME; VARIABLE ADDRDQ_t : TIME; BEGIN IF DOut_zd(0) /= 'Z' THEN CEDQ_t := -CENeg'LAST_EVENT + tpd_CENeg_DQ0(trz0); OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_DQ0(trz0); ADDRDQ_t := -AddrREF'LAST_EVENT + tpd_A0_DQ0(tr01);-- FROMOE := (OEDQ_t >= CEDQ_t) AND (OEDQ_t > 0 ns); FROMCE := (CEDQ_t > OEDQ_t) AND (CEDQ_t > 0 ns); ValidData := "XXXXXXXXXXXXXXXX"; IF ((ADDRDQ_t > 0 ns) AND (((ADDRDQ_t > CEDQ_t) AND FROMCE) OR ((ADDRDQ_t > OEDQ_t) AND FROMOE))) THEN DOut_Pass <= ValidData, DOut_zd AFTER ADDRDQ_t; ELSE DOut_Pass <= DOut_zd; END IF; ELSE DOut_Pass <= DOut_zd; FROMOE := TRUE; FROMCE := TRUE; END IF; END PROCESS DQValueGen; D_Out_PathDelay_Gen : FOR i IN 0 TO 15 GENERATE PROCESS(DOut_Pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_Pass(i), GlitchData => D0_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => false, Paths => ( 0 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_DQ0, PathCondition => FROMOE), 1 => (InputChangeTime => CENeg'LAST_EVENT, PathDelay => tpd_CENeg_DQ0, PathCondition => FROMCE), 2 => (InputChangeTime => AddrREF'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => TRUE), 3 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CLK_DQ0), PathCondition => OENeg = '0' AND CENeg = '0' AND ConfReg(17) = '1' AND ConfReg(19) = '0' AND (READ_MODE = CONTINUOUS OR READ_MODE = LINEAR) AND CLK = '1' AND OE_burst = '0'), 4 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CLK_DQ0), PathCondition => OENeg = '0' AND CENeg = '0' AND ConfReg(17) = '0' AND ConfReg(19) = '0' AND (READ_MODE = CONTINUOUS OR READ_MODE = LINEAR) AND CLK = '0' AND OE_burst = '0') ) ); END PROCESS; END GENERATE D_Out_PathDelay_Gen; END BLOCK behavior; END vhdl_behavioral;