-------------------------------------------------------------------------------- -- File Name: sy69167.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Steele 98 JAN 12 Conformed to style guide -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FIFO -- Technology: ECL -- Part: SY69167 -- -- Description: 64 X 18 FIFO -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY sy69167 IS GENERIC ( -- tipd delays: interconnect path delays tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_RDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RSTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_INHIBIT : VitalDelayType01 := VitalZeroDelay01; tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CLK_Q0 : VitalDelayType01 := UnitDelay01; tpd_CLK_FULL : VitalDelayType01 := UnitDelay01; tpd_CLK_HALF : VitalDelayType01 := UnitDelay01; tpd_CLK_EMPTY : VitalDelayType01 := UnitDelay01; tpd_CLK_OVFLOW : VitalDelayType01 := UnitDelay01; tpd_CLK_UNFLOW : VitalDelayType01 := UnitDelay01; tpd_RSTNeg_FULL : VitalDelayType01 := UnitDelay01; tpd_RSTNeg_HALF : VitalDelayType01 := UnitDelay01; tpd_RSTNeg_EMPTY : VitalDelayType01 := UnitDelay01; tpd_RSTNeg_OVFLOW : VitalDelayType01 := UnitDelay01; tpd_RSTNeg_UNFLOW : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths tpw_WRNeg_negedge : VitalDelayType := UnitDelay; tpw_CLK_posedge : VitalDelayType := UnitDelay; tpw_CLK_negedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times tsetup_D0_CLK : VitalDelayType := UnitDelay; -- thold values: hold times thold_D0_CLK : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( CLK : IN std_logic := 'X'; CLKNeg : IN std_logic := 'X'; RDNeg : IN std_logic := 'X'; WRNeg : IN std_logic := 'X'; RSTNeg : IN std_logic := 'X'; INHIBIT : IN std_logic := 'X'; D0 : IN std_logic := 'X'; D1 : IN std_logic := 'X'; D2 : IN std_logic := 'X'; D3 : IN std_logic := 'X'; D4 : IN std_logic := 'X'; D5 : IN std_logic := 'X'; D6 : IN std_logic := 'X'; D7 : IN std_logic := 'X'; D8 : IN std_logic := 'X'; D9 : IN std_logic := 'X'; D10 : IN std_logic := 'X'; D11 : IN std_logic := 'X'; D12 : IN std_logic := 'X'; D13 : IN std_logic := 'X'; D14 : IN std_logic := 'X'; D15 : IN std_logic := 'X'; D16 : IN std_logic := 'X'; D17 : IN std_logic := 'X'; FULL : OUT std_logic := 'U'; HALF : OUT std_logic := 'U'; EMPTY : OUT std_logic := 'U'; OVFLOW : OUT std_logic := 'U'; UNFLOW : OUT std_logic := 'U'; Q0 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q4 : OUT std_logic := 'U'; Q5 : OUT std_logic := 'U'; Q6 : OUT std_logic := 'U'; Q7 : OUT std_logic := 'U'; Q8 : OUT std_logic := 'U'; Q9 : OUT std_logic := 'U'; Q10 : OUT std_logic := 'U'; Q11 : OUT std_logic := 'U'; Q12 : OUT std_logic := 'U'; Q13 : OUT std_logic := 'U'; Q14 : OUT std_logic := 'U'; Q15 : OUT std_logic := 'U'; Q16 : OUT std_logic := 'U'; Q17 : OUT std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of sy69167 : ENTITY IS TRUE; END sy69167; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of sy69167 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL D4_ipd : std_ulogic := 'X'; SIGNAL D5_ipd : std_ulogic := 'X'; SIGNAL D6_ipd : std_ulogic := 'X'; SIGNAL D7_ipd : std_ulogic := 'X'; SIGNAL D8_ipd : std_ulogic := 'X'; SIGNAL D9_ipd : std_ulogic := 'X'; SIGNAL D10_ipd : std_ulogic := 'X'; SIGNAL D11_ipd : std_ulogic := 'X'; SIGNAL D12_ipd : std_ulogic := 'X'; SIGNAL D13_ipd : std_ulogic := 'X'; SIGNAL D14_ipd : std_ulogic := 'X'; SIGNAL D15_ipd : std_ulogic := 'X'; SIGNAL D16_ipd : std_ulogic := 'X'; SIGNAL D17_ipd : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; SIGNAL Q3int : std_ulogic := 'X'; SIGNAL Q4int : std_ulogic := 'X'; SIGNAL Q5int : std_ulogic := 'X'; SIGNAL Q6int : std_ulogic := 'X'; SIGNAL Q7int : std_ulogic := 'X'; SIGNAL Q8int : std_ulogic := 'X'; SIGNAL Q9int : std_ulogic := 'X'; SIGNAL Q10int : std_ulogic := 'X'; SIGNAL Q11int : std_ulogic := 'X'; SIGNAL Q12int : std_ulogic := 'X'; SIGNAL Q13int : std_ulogic := 'X'; SIGNAL Q14int : std_ulogic := 'X'; SIGNAL Q15int : std_ulogic := 'X'; SIGNAL Q16int : std_ulogic := 'X'; SIGNAL Q17int : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL FULLint : std_ulogic := 'X'; SIGNAL HALFint : std_ulogic := 'X'; SIGNAL EMPTYint : std_ulogic := 'X'; SIGNAL OVFLOWint : std_ulogic := 'X'; SIGNAL UNFLOWint : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL RDNeg_ipd : std_ulogic := 'X'; SIGNAL WRNeg_ipd : std_ulogic := 'X'; SIGNAL RSTNeg_ipd : std_ulogic := 'X'; SIGNAL INHIBIT_ipd : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_2: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_3: VitalWireDelay (RDNeg_ipd, RDNeg, tipd_RDNeg); w_4: VitalWireDelay (WRNeg_ipd, WRNeg, tipd_WRNeg); w_5: VitalWireDelay (RSTNeg_ipd, RSTNeg, tipd_RSTNeg); w_6: VitalWireDelay (INHIBIT_ipd, INHIBIT, tipd_INHIBIT); w_7: VitalWireDelay (D0_ipd, D0, tipd_D0); w_8: VitalWireDelay (D1_ipd, D1, tipd_D1); w_9: VitalWireDelay (D2_ipd, D2, tipd_D2); w_10: VitalWireDelay (D3_ipd, D3, tipd_D3); w_11: VitalWireDelay (D4_ipd, D4, tipd_D4); w_12: VitalWireDelay (D5_ipd, D5, tipd_D5); w_13: VitalWireDelay (D6_ipd, D6, tipd_D6); w_14: VitalWireDelay (D7_ipd, D7, tipd_D7); w_15: VitalWireDelay (D8_ipd, D8, tipd_D8); w_16: VitalWireDelay (D9_ipd, D9, tipd_D9); w_17: VitalWireDelay (D10_ipd, D10, tipd_D10); w_18: VitalWireDelay (D11_ipd, D11, tipd_D11); w_19: VitalWireDelay (D12_ipd, D12, tipd_D12); w_20: VitalWireDelay (D13_ipd, D13, tipd_D13); w_21: VitalWireDelay (D14_ipd, D14, tipd_D14); w_22: VitalWireDelay (D15_ipd, D15, tipd_D15); w_23: VitalWireDelay (D16_ipd, D16, tipd_D16); w_24: VitalWireDelay (D17_ipd, D17, tipd_D17); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedures ---------------------------------------------------------------------------- a_1: VitalBUF(q => Q0, a => Q0int, Resultmap => ECL_wired_or_rmap); a_2: VitalBUF(q => Q1, a => Q1int, Resultmap => ECL_wired_or_rmap); a_3: VitalBUF(q => Q2, a => Q2int, Resultmap => ECL_wired_or_rmap); a_4: VitalBUF(q => Q3, a => Q3int, Resultmap => ECL_wired_or_rmap); a_5: VitalBUF(q => Q4, a => Q4int, Resultmap => ECL_wired_or_rmap); a_6: VitalBUF(q => Q5, a => Q5int, Resultmap => ECL_wired_or_rmap); a_7: VitalBUF(q => Q6, a => Q6int, Resultmap => ECL_wired_or_rmap); a_8: VitalBUF(q => Q7, a => Q7int, Resultmap => ECL_wired_or_rmap); a_9: VitalBUF(q => Q8, a => Q8int, Resultmap => ECL_wired_or_rmap); a_10: VitalBUF(q => Q9, a => Q9int, Resultmap => ECL_wired_or_rmap); a_11: VitalBUF(q => Q10, a => Q10int, Resultmap => ECL_wired_or_rmap); a_12: VitalBUF(q => Q11, a => Q11int, Resultmap => ECL_wired_or_rmap); a_13: VitalBUF(q => Q12, a => Q12int, Resultmap => ECL_wired_or_rmap); a_14: VitalBUF(q => Q13, a => Q13int, Resultmap => ECL_wired_or_rmap); a_15: VitalBUF(q => Q14, a => Q14int, Resultmap => ECL_wired_or_rmap); a_16: VitalBUF(q => Q15, a => Q15int, Resultmap => ECL_wired_or_rmap); a_17: VitalBUF(q => Q16, a => Q16int, Resultmap => ECL_wired_or_rmap); a_18: VitalBUF(q => Q17, a => Q17int, Resultmap => ECL_wired_or_rmap); a_19: VitalBUF(q => FULL, a => FULLint, Resultmap => ECL_wired_or_rmap); a_20: VitalBUF(q => HALF, a => HALFint, Resultmap => ECL_wired_or_rmap); a_21: VitalBUF(q => EMPTY, a => EMPTYint, Resultmap => ECL_wired_or_rmap); a_22: VitalBUF(q => OVFLOW, a => OVFLOWint, Resultmap => ECL_wired_or_rmap); a_23: VitalBUF(q => UNFLOW, a => UNFLOWint, Resultmap => ECL_wired_or_rmap); ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (CLK_ipd, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab (CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode), Result => CLKint_zd, PreviousDataIn => PrevData ); CLKint <= CLKint_zd; END PROCESS; ---------------------------------------------------------------------------- -- Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, RSTNeg_ipd) TYPE MemStore IS ARRAY (0 to 63) OF BIT_VECTOR(17 DOWNTO 0); -- Functionality Results Variables VARIABLE FULL_zd : std_ulogic; VARIABLE HALF_zd : std_ulogic; VARIABLE EMPTY_zd : std_ulogic; VARIABLE OVFLOW_zd : std_ulogic; VARIABLE UNFLOW_zd : std_ulogic; VARIABLE DataGet : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'X'); VARIABLE DataDrive : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'X'); VARIABLE DataIn : BIT_VECTOR(17 DOWNTO 0) := (OTHERS => '0'); VARIABLE DataOut : BIT_VECTOR(17 DOWNTO 0) := (OTHERS => '0'); VARIABLE RDPoint : INTEGER RANGE 0 TO 63 := 0; VARIABLE WRPoint : INTEGER RANGE 0 TO 63 := 0; VARIABLE Count : INTEGER RANGE 0 TO 63 := 0; VARIABLE MemData : MemStore; ALIAS Q0_zd : std_logic IS DataDrive(0); ALIAS Q1_zd : std_logic IS DataDrive(1); ALIAS Q2_zd : std_logic IS DataDrive(2); ALIAS Q3_zd : std_logic IS DataDrive(3); ALIAS Q4_zd : std_logic IS DataDrive(4); ALIAS Q5_zd : std_logic IS DataDrive(5); ALIAS Q6_zd : std_logic IS DataDrive(6); ALIAS Q7_zd : std_logic IS DataDrive(7); ALIAS Q8_zd : std_logic IS DataDrive(8); ALIAS Q9_zd : std_logic IS DataDrive(9); ALIAS Q10_zd : std_logic IS DataDrive(10); ALIAS Q11_zd : std_logic IS DataDrive(11); ALIAS Q12_zd : std_logic IS DataDrive(12); ALIAS Q13_zd : std_logic IS DataDrive(13); ALIAS Q14_zd : std_logic IS DataDrive(14); ALIAS Q15_zd : std_logic IS DataDrive(15); ALIAS Q16_zd : std_logic IS DataDrive(16); ALIAS Q17_zd : std_logic IS DataDrive(17); -- Timing Check Variables VARIABLE Tviol_D0_CLK : X01 := '0'; VARIABLE TD_D0_CLK : VitalTimingDataType; VARIABLE Tviol_D1_CLK : X01 := '0'; VARIABLE TD_D1_CLK : VitalTimingDataType; VARIABLE Tviol_D2_CLK : X01 := '0'; VARIABLE TD_D2_CLK : VitalTimingDataType; VARIABLE Tviol_D3_CLK : X01 := '0'; VARIABLE TD_D3_CLK : VitalTimingDataType; VARIABLE Tviol_D4_CLK : X01 := '0'; VARIABLE TD_D4_CLK : VitalTimingDataType; VARIABLE Tviol_D5_CLK : X01 := '0'; VARIABLE TD_D5_CLK : VitalTimingDataType; VARIABLE Tviol_D6_CLK : X01 := '0'; VARIABLE TD_D6_CLK : VitalTimingDataType; VARIABLE Tviol_D7_CLK : X01 := '0'; VARIABLE TD_D7_CLK : VitalTimingDataType; VARIABLE Tviol_D8_CLK : X01 := '0'; VARIABLE TD_D8_CLK : VitalTimingDataType; VARIABLE Tviol_D9_CLK : X01 := '0'; VARIABLE TD_D9_CLK : VitalTimingDataType; VARIABLE Tviol_D10_CLK : X01 := '0'; VARIABLE TD_D10_CLK : VitalTimingDataType; VARIABLE Tviol_D11_CLK : X01 := '0'; VARIABLE TD_D11_CLK : VitalTimingDataType; VARIABLE Tviol_D12_CLK : X01 := '0'; VARIABLE TD_D12_CLK : VitalTimingDataType; VARIABLE Tviol_D13_CLK : X01 := '0'; VARIABLE TD_D13_CLK : VitalTimingDataType; VARIABLE Tviol_D14_CLK : X01 := '0'; VARIABLE TD_D14_CLK : VitalTimingDataType; VARIABLE Tviol_D15_CLK : X01 := '0'; VARIABLE TD_D15_CLK : VitalTimingDataType; VARIABLE Tviol_D16_CLK : X01 := '0'; VARIABLE TD_D16_CLK : VitalTimingDataType; VARIABLE Tviol_D17_CLK : X01 := '0'; VARIABLE TD_D17_CLK : VitalTimingDataType; VARIABLE Tviol_WRNeg_CLK: X01 := '0'; VARIABLE TD_WRNeg_CLK : VitalTimingDataType; VARIABLE Tviol_RDNeg_CLK: X01 := '0'; VARIABLE TD_RDNeg_CLK : VitalTimingDataType; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_WRNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WRNeg : X01 := '0'; VARIABLE Violation : X01 := '0'; -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; VARIABLE Q3_GlitchData : VitalGlitchDataType; VARIABLE Q4_GlitchData : VitalGlitchDataType; VARIABLE Q5_GlitchData : VitalGlitchDataType; VARIABLE Q6_GlitchData : VitalGlitchDataType; VARIABLE Q7_GlitchData : VitalGlitchDataType; VARIABLE Q8_GlitchData : VitalGlitchDataType; VARIABLE Q9_GlitchData : VitalGlitchDataType; VARIABLE Q10_GlitchData : VitalGlitchDataType; VARIABLE Q11_GlitchData : VitalGlitchDataType; VARIABLE Q12_GlitchData : VitalGlitchDataType; VARIABLE Q13_GlitchData : VitalGlitchDataType; VARIABLE Q14_GlitchData : VitalGlitchDataType; VARIABLE Q15_GlitchData : VitalGlitchDataType; VARIABLE Q16_GlitchData : VitalGlitchDataType; VARIABLE Q17_GlitchData : VitalGlitchDataType; VARIABLE FULL_GlitchData : VitalGlitchDataType; VARIABLE HALF_GlitchData : VitalGlitchDataType; VARIABLE EMPTY_GlitchData : VitalGlitchDataType; VARIABLE OVFLOW_GlitchData : VitalGlitchDataType; VARIABLE UNFLOW_GlitchData : VitalGlitchDataType; -- No Weak Values Variables VARIABLE RDNeg_nwv : UX01 := 'X'; VARIABLE WRNeg_nwv : UX01 := 'X'; VARIABLE RSTNeg_nwv : UX01 := 'X'; VARIABLE INHIBIT_nwv : UX01 := 'X'; BEGIN RDNeg_nwv := To_UX01 (s => RDNeg_ipd); WRNeg_nwv := To_UX01 (s => WRNeg_ipd); RSTNeg_nwv := To_UX01 (s => RSTNeg_ipd); INHIBIT_nwv := To_UX01 (s => INHIBIT_ipd); ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D0_ipd, TestSignalName => "D0_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_CLK ); VitalSetupHoldCheck ( TestSignal => D1_ipd, TestSignalName => "D1_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D1_CLK ); VitalSetupHoldCheck ( TestSignal => D2_ipd, TestSignalName => "D2_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D2_CLK ); VitalSetupHoldCheck ( TestSignal => D3_ipd, TestSignalName => "D3_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D3_CLK ); VitalSetupHoldCheck ( TestSignal => D4_ipd, TestSignalName => "D4_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D4_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D4_CLK ); VitalSetupHoldCheck ( TestSignal => D5_ipd, TestSignalName => "D5_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D5_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D5_CLK ); VitalSetupHoldCheck ( TestSignal => D6_ipd, TestSignalName => "D6_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D6_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D6_CLK ); VitalSetupHoldCheck ( TestSignal => D7_ipd, TestSignalName => "D7_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D7_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D7_CLK ); VitalSetupHoldCheck ( TestSignal => D8_ipd, TestSignalName => "D8_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D8_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D8_CLK ); VitalSetupHoldCheck ( TestSignal => D9_ipd, TestSignalName => "D9_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D9_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D9_CLK ); VitalSetupHoldCheck ( TestSignal => D10_ipd, TestSignalName => "D10_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D10_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D10_CLK ); VitalSetupHoldCheck ( TestSignal => D11_ipd, TestSignalName => "D11_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D11_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D11_CLK ); VitalSetupHoldCheck ( TestSignal => D12_ipd, TestSignalName => "D12_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D12_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D12_CLK ); VitalSetupHoldCheck ( TestSignal => D13_ipd, TestSignalName => "D13_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D13_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D13_CLK ); VitalSetupHoldCheck ( TestSignal => D14_ipd, TestSignalName => "D14_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D14_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D14_CLK ); VitalSetupHoldCheck ( TestSignal => D15_ipd, TestSignalName => "D15_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D15_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D15_CLK ); VitalSetupHoldCheck ( TestSignal => D16_ipd, TestSignalName => "D16_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D16_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D16_CLK ); VitalSetupHoldCheck ( TestSignal => D17_ipd, TestSignalName => "D17_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D17_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D17_CLK ); VitalSetupHoldCheck ( TestSignal => WRNeg_ipd, TestSignalName => "WRNeg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_WRNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WRNeg_CLK ); VitalSetupHoldCheck ( TestSignal => RDNeg_ipd, TestSignalName => "RDNeg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_RDNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RDNeg_CLK ); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & "/sy69167", CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => WRNeg_ipd, TestSignalName => "WRNeg_ipd", PulseWidthLow => tpw_WRNeg_negedge, PeriodData => PD_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WRNeg, HeaderMsg => InstancePath & "/sy69167", CheckEnabled => TRUE ); END IF; -- Timing Check Section ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_CLK OR Pviol_WRNeg OR Tviol_WRNeg_CLK OR Tviol_D0_CLK OR Tviol_D1_CLK OR Tviol_D2_CLK OR Tviol_D3_CLK OR Tviol_D4_CLK OR Tviol_D5_CLK OR Tviol_D6_CLK OR Tviol_D7_CLK OR Tviol_D8_CLK OR Tviol_D9_CLK OR Tviol_D10_CLK OR Tviol_D11_CLK OR Tviol_D12_CLK OR Tviol_D13_CLK OR Tviol_D14_CLK OR Tviol_D15_CLK OR Tviol_D16_CLK OR Tviol_D17_CLK OR Tviol_RDNeg_CLK; IF (Violation = 'X') THEN DataDrive := (OTHERS => 'X'); FULL_zd := 'X'; HALF_zd := 'X'; EMPTY_zd := 'X'; OVFLOW_zd := 'X'; UNFLOW_zd := 'X'; ELSIF (RSTNeg_nwv = '0') THEN RDPoint := 0; WRPoint := 0; Count := 0; FULL_zd := '0'; HALF_zd := '0'; EMPTY_zd := '1'; OVFLOW_zd := '0'; UNFLOW_zd := '0'; ELSIF (CLKint = '1' and CLKint'EVENT) THEN IF (WRNeg_nwv = '0') THEN IF (FULL_zd = '1' AND INHIBIT_nwv = '1') THEN NULL; ELSE DataGet(17) := D17_ipd; DataGet(16) := D16_ipd; DataGet(15) := D15_ipd; DataGet(14) := D14_ipd; DataGet(13) := D13_ipd; DataGet(12) := D12_ipd; DataGet(11) := D11_ipd; DataGet(10) := D10_ipd; DataGet(9) := D9_ipd; DataGet(8) := D8_ipd; DataGet(7) := D7_ipd; DataGet(6) := D6_ipd; DataGet(5) := D5_ipd; DataGet(4) := D4_ipd; DataGet(3) := D3_ipd; DataGet(2) := D2_ipd; DataGet(1) := D1_ipd; DataGet(0) := D0_ipd; -- Check for unusable data bits FOR i IN 0 TO 17 LOOP IF ((DataGet(i) = '1' NOR DataGet(i) = '0') NOR (DataGet(i) = 'L' NOR DataGet(i) = 'H')) THEN ASSERT FALSE REPORT "DATA BUS ERRROR! ZEROS LOADED INTO MEMORY!" SEVERITY WARNING; END IF; END LOOP; DataIn := To_bitvector(DataGet); MemData(WRPoint) := DataIn; EMPTY_zd := '0'; IF (FULL_zd = '1') THEN OVFLOW_zd := '1'; ELSE OVFLOW_zd := '0'; END IF; IF (Count >= 32) THEN HALF_zd := '1'; ELSE HALF_zd := '0'; END IF; IF (Count = 63) THEN FULL_zd := '1'; ELSE FULL_zd := '0'; Count := Count + 1; END IF; IF (WRPoint = 63) THEN WRPoint := 0; ELSE WRPoint := WRPoint + 1; END IF; END IF; ELSIF (RDNeg_nwv = '0') THEN IF (EMPTY_zd = '1' AND INHIBIT_nwv = '1') THEN NULL; ELSE DataOut := MemData(RDPoint); DataDrive := To_StdLogicVector(DataOut); FULL_zd := '0'; IF (EMPTY_zd = '1') THEN UNFLOW_zd := '1'; ELSE UNFLOW_zd := '0'; END IF; IF (Count >= 32) THEN HALF_zd := '1'; ELSE HALF_zd := '0'; END IF; IF (Count = 0) THEN EMPTY_zd := '1'; ELSE EMPTY_zd := '0'; Count := Count - 1; END IF; IF (RDPoint = 63) THEN RDPoint := 0; ELSE RDPoint := RDPoint + 1; END IF; END IF; END IF; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0", OutTemp => Q0_zd, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1", OutTemp => Q1_zd, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2", OutTemp => Q2_zd, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q3int, OutSignalName => "Q3", OutTemp => Q3_zd, GlitchData => Q3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q4int, OutSignalName => "Q4", OutTemp => Q4_zd, GlitchData => Q4_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q5int, OutSignalName => "Q5", OutTemp => Q5_zd, GlitchData => Q5_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q6int, OutSignalName => "Q6", OutTemp => Q6_zd, GlitchData => Q6_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q7int, OutSignalName => "Q7", OutTemp => Q7_zd, GlitchData => Q7_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q8int, OutSignalName => "Q8", OutTemp => Q8_zd, GlitchData => Q8_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q9int, OutSignalName => "Q9", OutTemp => Q9_zd, GlitchData => Q9_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q10int, OutSignalName => "Q10", OutTemp => Q10_zd, GlitchData => Q10_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q11int, OutSignalName => "Q11", OutTemp => Q11_zd, GlitchData => Q11_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q12int, OutSignalName => "Q12", OutTemp => Q12_zd, GlitchData => Q12_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q13int, OutSignalName => "Q13", OutTemp => Q13_zd, GlitchData => Q13_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q14int, OutSignalName => "Q14", OutTemp => Q14_zd, GlitchData => Q14_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q15int, OutSignalName => "Q15", OutTemp => Q15_zd, GlitchData => Q15_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q16int, OutSignalName => "Q16", OutTemp => Q16_zd, GlitchData => Q16_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q17int, OutSignalName => "Q17", OutTemp => Q17_zd, GlitchData => Q17_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => FULLint, OutSignalName => "FULL", OutTemp => FULL_zd, GlitchData => FULL_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_FULL, PathCondition => TRUE), 1 => (InputChangeTime => RSTNeg_ipd'LAST_EVENT, PathDelay => tpd_RSTNeg_FULL, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => HALFint, OutSignalName => "HALF", OutTemp => HALF_zd, GlitchData => HALF_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_HALF, PathCondition => TRUE), 1 => (InputChangeTime => RSTNeg_ipd'LAST_EVENT, PathDelay => tpd_RSTNeg_HALF, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => EMPTYint, OutSignalName => "EMPTY", OutTemp => EMPTY_zd, GlitchData => EMPTY_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_EMPTY, PathCondition => TRUE), 1 => (InputChangeTime => RSTNeg_ipd'LAST_EVENT, PathDelay => tpd_RSTNeg_EMPTY, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => OVFLOWint, OutSignalName => "OVFLOW", OutTemp => OVFLOW_zd, GlitchData => OVFLOW_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_OVFLOW, PathCondition => TRUE), 1 => (InputChangeTime => RSTNeg_ipd'LAST_EVENT, PathDelay => tpd_RSTNeg_OVFLOW, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => UNFLOWint, OutSignalName => "UNFLOW", OutTemp => UNFLOW_zd, GlitchData => UNFLOW_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_UNFLOW, PathCondition => TRUE), 1 => (InputChangeTime => RSTNeg_ipd'LAST_EVENT, PathDelay => tpd_RSTNeg_UNFLOW, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;