-------------------------------------------------------------------------------- -- File name : idt72v845.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998 Integrated Device Technology; http://www.idt.com/ -- Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT -- and supported by Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no -- warranty with respect to the information contained herein. IDT DISCLAIMS -- AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE -- ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN -- NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN -- CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, -- CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR -- APPLICATION OF THE VHDL model. Further, IDT reserves the right to make -- changes without notice to any product herein to improve reliability, -- function, or design. IDT does not convey any license under patent rights -- or any other intellectual property rights, including those of third parties. -- IDT is not obligated to provide maintenance or support for the licensed VHDL -- model. -- -- MODIFICATION HISTORY : -- -- version | author: | mod date: | changes made -- V1.0 | Igor Oznobikhin | 98 MAY 15 | initial release -- V1.1 | R. Munden | 02 MAY 19 | licensing changed to GPL -------------------------------------------------------------------------------- -- -- PART DESCRIPTION : -- -- Library: FIFO -- Technology: 3.3 VOLT CMOS -- Part: IDT72V845 -- -- Descripton: Dual SyncFIFO 4096x18-bit -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ff_package.ALL; USE FMF.gen_utils.ALL; USE FMF.conversions.to_nat; USE FMF.conversions.to_slv; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -- -------------------------------------------------------------------------------- ENTITY IDT72V845 IS GENERIC ( -- tipd delays: interconnect path delays -- (there must be one generic for each input pin) tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_RSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK : VitalDelayType01 := VitalZeroDelay01; tipd_WENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_LDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_FLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WXINeg : VitalDelayType01 := VitalZeroDelay01; tipd_RXINeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays -- tRSF tpd_RSNeg_EFORNeg : VitalDelayType01 := UnitDelay01; -- tRSF tpd_RSNeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tA (applicable for RCLK - Q ) tpd_RCLK_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tOLZ/tOE/tOHZ tpd_OENeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tWFF tpd_WCLK_FFIRNeg : VitalDelayType01 := UnitDelay01; -- tREF tpd_RCLK_EFORNeg : VitalDelayType01 := UnitDelay01; -- tPAFA tpd_RCLK_PAFNeg : VitalDelayType01 := UnitDelay01; -- tPAFS tpd_WCLK_PAFNeg : VitalDelayType01 := UnitDelay01; -- tPAEA tpd_WCLK_PAENeg : VitalDelayType01 := UnitDelay01; -- tPAES tpd_RCLK_PAENeg : VitalDelayType01 := UnitDelay01; -- tHF (applicable for both WCLK and RCLK) tpd_RCLK_WXOHFNeg : VitalDelayType01 := UnitDelay01; -- tXO tpd_RCLK_RXONeg : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths -- tCLKH tpw_RCLK_posedge : VitalDelayType := UnitDelay; -- tCLKL tpw_RCLK_negedge : VitalDelayType := UnitDelay; -- tRS tpw_RSNeg_negedge : VitalDelayType := UnitDelay; -- tXI tpw_RXINeg_negedge : VitalDelayType := UnitDelay; -- tperiod min (calculated as 1/max freq) -- tCLK (applicable for both WCLK and RCLK) tperiod_RCLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS tsetup_D0_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tENS (applicable for both WEN/WCLK and REN/RCLK) tsetup_RENNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tRSS (applicable for REN,WEN,LD) tsetup_LDNeg_RSNeg_noedge_posedge : VitalDelayType := UnitDelay; -- tXIS tsetup_RXINeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH thold_D0_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tENH thold_RENNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tskew values: skew times -- tSKEW1 tdevice_SKEW1 : VitalDelayType := UnitDelay; -- tSKEW2 tdevice_SKEW2 : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN std_logic := 'X'; -- Data Input Bus D1 : IN std_logic := 'X'; D2 : IN std_logic := 'X'; D3 : IN std_logic := 'X'; D4 : IN std_logic := 'X'; D5 : IN std_logic := 'X'; D6 : IN std_logic := 'X'; D7 : IN std_logic := 'X'; D8 : IN std_logic := 'X'; D9 : IN std_logic := 'X'; D10 : IN std_logic := 'X'; D11 : IN std_logic := 'X'; D12 : IN std_logic := 'X'; D13 : IN std_logic := 'X'; D14 : IN std_logic := 'X'; D15 : IN std_logic := 'X'; D16 : IN std_logic := 'X'; D17 : IN std_logic := 'X'; RSNeg : IN std_logic := 'X'; -- Reset WCLK : IN std_logic := 'X'; -- Write Clock WENNeg : IN std_logic := 'X'; -- Write Enable RCLK : IN std_logic := 'X'; -- Read Clock RENNeg : IN std_logic := 'X'; -- Read Enable OENeg : IN std_logic := 'X'; -- Output Enable LDNeg : IN std_logic := 'X'; -- Load FLNeg : IN std_logic := 'X'; -- First Load WXINeg : IN std_logic := 'X'; -- Write Expansion Input RXINeg : IN std_logic := 'X'; -- Read Expansion Input EFORNeg : OUT std_logic := 'U'; -- Empty Flag / Output Ready PAENeg : OUT std_logic := 'U'; -- Programmable Almost Empty Flag PAFNeg : OUT std_logic := 'U'; -- Programmable Almost Full Flag FFIRNeg : OUT std_logic := 'U'; -- Full Flag / Input Ready WXOHFNeg: OUT std_logic := 'U'; -- Write Expansion Out/Half-Full Flag RXONeg : OUT std_logic := 'U'; -- Read Expansion Out Q0 : OUT std_logic := 'U'; -- Data Output Bus Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q4 : OUT std_logic := 'U'; Q5 : OUT std_logic := 'U'; Q6 : OUT std_logic := 'U'; Q7 : OUT std_logic := 'U'; Q8 : OUT std_logic := 'U'; Q9 : OUT std_logic := 'U'; Q10 : OUT std_logic := 'U'; Q11 : OUT std_logic := 'U'; Q12 : OUT std_logic := 'U'; Q13 : OUT std_logic := 'U'; Q14 : OUT std_logic := 'U'; Q15 : OUT std_logic := 'U'; Q16 : OUT std_logic := 'U'; Q17 : OUT std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 OF IDT72V845 : ENTITY IS TRUE; END IDT72V845; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF IDT72V845 IS ATTRIBUTE VITAL_LEVEL1 OF vhdl_behavioral : ARCHITECTURE IS FALSE; -- RAM definition CONSTANT RAMWordLength : positive := 18; -- number of bits in RAM word CONSTANT AddrBitNum : positive := 12; -- number of bits in RAM address CONSTANT RAMSize : positive := 2**AddrBitNum; CONSTANT HalfSize : positive := RAMSize/2; CONSTANT OffsetLength : positive := 12; -- number of bits in Offset Reg CONSTANT Default_Val : natural := 127; -- for Offset Reg after Reset CONSTANT partID : String := "IDT72V845"; SUBTYPE RAM_Word IS Std_Logic_Vector (RAMWordLength-1 DOWNTO 0); TYPE RAM_Array IS ARRAY (RAMSize-1 DOWNTO 0) OF RAM_Word; SUBTYPE Point IS Std_Logic_Vector (AddrBitNum-1 DOWNTO 0); -- delayed inputs SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL D4_ipd : std_ulogic := 'X'; SIGNAL D5_ipd : std_ulogic := 'X'; SIGNAL D6_ipd : std_ulogic := 'X'; SIGNAL D7_ipd : std_ulogic := 'X'; SIGNAL D8_ipd : std_ulogic := 'X'; SIGNAL D9_ipd : std_ulogic := 'X'; SIGNAL D10_ipd : std_ulogic := 'X'; SIGNAL D11_ipd : std_ulogic := 'X'; SIGNAL D12_ipd : std_ulogic := 'X'; SIGNAL D13_ipd : std_ulogic := 'X'; SIGNAL D14_ipd : std_ulogic := 'X'; SIGNAL D15_ipd : std_ulogic := 'X'; SIGNAL D16_ipd : std_ulogic := 'X'; SIGNAL D17_ipd : std_ulogic := 'X'; SIGNAL RSNeg_ipd : std_ulogic := 'X'; SIGNAL WCLK_ipd : std_ulogic := 'X'; SIGNAL WENNeg_ipd : std_ulogic := 'X'; SIGNAL RCLK_ipd : std_ulogic := 'X'; SIGNAL RENNeg_ipd : std_ulogic := 'X'; SIGNAL OENeg_ipd : std_ulogic := 'X'; SIGNAL LDNeg_ipd : std_ulogic := 'X'; SIGNAL FLNeg_ipd : std_ulogic := 'X'; SIGNAL WXINeg_ipd : std_ulogic := 'X'; SIGNAL RXINeg_ipd : std_ulogic := 'X'; -- internal signals SIGNAL RAM : RAM_Array ; SIGNAL Write_Pointerint, WritePnt_Sumint : Natural; SIGNAL Read_Pointerint : Natural ; SIGNAL Write_PRint,Read_PRint: Point; SIGNAL Wr_Pnt_Delint: Point; SIGNAL PAE_Offset_Regint,PAF_Offset_Regint: std_logic_vector( OffsetLength-1 Downto 0); SIGNAL Zerosint : std_logic_vector(RAMWordLength-OffsetLength-1 Downto 0); SIGNAL Fullint,Emptyint,HFint,FF_Delint : std_logic; SIGNAL Almost_Fullint,Almost_Emptyint : std_logic; SIGNAL AlmEmp_Setint,AlmEmp_Resint : std_logic; SIGNAL AlmFull_Setint,SAlmFull_Setint,AlmFull_Resint : std_logic; SIGNAL HlfFull_Setint,HlfFull_Resint : std_logic; SIGNAL Read_Flint,Write_Flint : std_logic; SIGNAL Write_Enableint,Read_Enableint,Read_En_Delint : std_logic; SIGNAL Input_Regint : RAM_Word; SIGNAL Wr_Offset_Pntint,Rd_Offset_Pntint : std_logic; SIGNAL WrP_mn_RdPint,RdP_mn_WrPint : integer; SIGNAL WrP_GE_RdPint: std_logic; SIGNAL Depth_Expanint: std_logic; SIGNAL WXOint: std_logic; SIGNAL Output_Regint,Data_Outint : RAM_Word; SIGNAL WXO_Tg1int,WXO_Tg2int: std_logic; SIGNAL RXO_Tg1int, RXO_Tg2int : std_logic; SIGNAL Wr_RAM_Onint,Rd_RAM_Onint: std_logic; SIGNAL Wr_RAM_Delint : std_logic; SIGNAL Wr_Ofs_Onint,Rd_Ofs_Onint: std_logic; SIGNAL No_Expanint : std_logic; SIGNAL FWFTint,Dbl_Bufint,Syncint : std_logic; SIGNAL Res_FWFTint,Res_Dbl_Bufint,Res_Syncint : std_logic; SIGNAL Fst_Wrdint : std_logic; SIGNAL Emp_Setint,Emp_Resint,EmpDint : std_logic; SIGNAL Sng_Emp_Resint,Dbl_Emp_Resint : std_logic; SIGNAL Full_Setint,Full_Resint : std_logic; SIGNAL Sng_Full_Resint,Dbl_Full_Resint : std_logic; SIGNAL PAE_Syncint,PAF_Syncint : std_logic; SIGNAL Wr_En_Setint,Wr_En_Resint : std_logic; SIGNAL Rd_En_Setint,Rd_En_Resint : std_logic; SIGNAL OpenIn, OpenOut : std_logic; -- Additional Delayed Signals SIGNAL Write_PRint_DEL, Read_PRint_DEL: Point; SIGNAL Read_Flint_DEL, Write_Flint_DEL: std_logic; SIGNAL AlmEmp_Setint_DEL, AlmEmp_Resint_DEL : std_logic; SIGNAL SAlmFull_Setint_DEL, AlmFull_Resint_DEL : std_logic; BEGIN -------------------------------------------------------------------------------- -- Dummy instances for exporting tSKEW vals from SDF file -- using DEVICE construct -------------------------------------------------------------------------------- SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1)); SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2)); -------------------------------------------------------------------------------- -- Wire Delays -- -------------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D0_ipd, D0, tipd_D0 ); w_2: VitalWireDelay (D1_ipd, D1, tipd_D1 ); w_3: VitalWireDelay (D2_ipd, D2, tipd_D2 ); w_4: VitalWireDelay (D3_ipd, D3, tipd_D3 ); w_5: VitalWireDelay (D4_ipd, D4, tipd_D4 ); w_6: VitalWireDelay (D5_ipd, D5, tipd_D5 ); w_7: VitalWireDelay (D6_ipd, D6, tipd_D6 ); w_8: VitalWireDelay (D7_ipd, D7, tipd_D7 ); w_9: VitalWireDelay (D8_ipd, D8, tipd_D8 ); w_10: VitalWireDelay (D9_ipd, D9, tipd_D9 ); w_11: VitalWireDelay (D10_ipd, D10, tipd_D10 ); w_12: VitalWireDelay (D11_ipd, D11, tipd_D11 ); w_13: VitalWireDelay (D12_ipd, D12, tipd_D12 ); w_14: VitalWireDelay (D13_ipd, D13, tipd_D13 ); w_15: VitalWireDelay (D14_ipd, D14, tipd_D14 ); w_16: VitalWireDelay (D15_ipd, D15, tipd_D15 ); w_17: VitalWireDelay (D16_ipd, D16, tipd_D16 ); w_18: VitalWireDelay (D17_ipd, D17, tipd_D17 ); w_19: VitalWireDelay (RSNeg_ipd, RSNeg, tipd_RSNeg ); w_20: VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK ); w_21: VitalWireDelay (WENNeg_ipd, WENNeg, tipd_WENNeg ); w_22: VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK ); w_23: VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg ); w_24: VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg ); w_25: VitalWireDelay (LDNeg_ipd, LDNeg, tipd_LDNeg ); w_26: VitalWireDelay (FLNeg_ipd, FLNeg, tipd_FLNeg ); w_27: VitalWireDelay (WXINeg_ipd, WXINeg, tipd_WXINeg ); w_28: VitalWireDelay (RXINeg_ipd, RXINeg, tipd_RXINeg ); END BLOCK; -------------------------------------------------------------------------------- -- Main Behavior Block -- -------------------------------------------------------------------------------- VITALBehavior: BLOCK PORT ( D : IN RAM_Word := (OTHERS => 'X'); RSNeg : IN std_logic := 'X' ; WCLK : IN std_logic := 'X' ; WENNeg : IN std_logic := 'X' ; RCLK : IN std_logic := 'X' ; RENNeg : IN std_logic := 'X' ; OENeg : IN std_logic := 'X' ; LDNeg : IN std_logic := 'X' ; FLNeg : IN std_logic := 'X' ; WXINeg : IN std_logic := 'X' ; RXINeg : IN std_logic := 'X' ; EFORNeg : OUT std_logic := 'U' ; PAENeg : OUT std_logic := 'U' ; PAFNeg : OUT std_logic := 'U' ; FFIRNeg : OUT std_logic := 'U' ; WXOHFNeg: OUT std_logic := 'U' ; RXONeg : OUT std_logic := 'U' ; Q : OUT RAM_Word := (OTHERS => 'U') ); PORT MAP ( D(0) => D0_ipd, D(1) => D1_ipd, D(2) => D2_ipd, D(3) => D3_ipd, D(4) => D4_ipd, D(5) => D5_ipd, D(6) => D6_ipd, D(7) => D7_ipd, D(8) => D8_ipd, D(9) => D9_ipd, D(10) => D10_ipd, D(11) => D11_ipd, D(12) => D12_ipd, D(13) => D13_ipd, D(14) => D14_ipd, D(15) => D15_ipd, D(16) => D16_ipd, D(17) => D17_ipd, RSNeg => RSNeg_ipd, WCLK => WCLK_ipd, WENNeg => WENNeg_ipd, RCLK => RCLK_ipd, RENNeg => RENNeg_ipd, OENeg => OENeg_ipd, LDNeg => LDNeg_ipd, FLNeg => FLNeg_ipd, WXINeg => WXINeg_ipd, RXINeg => RXINeg_ipd, EFORNeg => EFORNeg, PAENeg => PAENeg, PAFNeg => PAFNeg, FFIRNeg => FFIRNeg, WXOHFNeg => WXOHFNeg, RXONeg => RXONeg, Q(0) => Q0, Q(1) => Q1, Q(2) => Q2, Q(3) => Q3, Q(4) => Q4, Q(5) => Q5, Q(6) => Q6, Q(7) => Q7, Q(8) => Q8, Q(9) => Q9, Q(10) => Q10, Q(11) => Q11, Q(12) => Q12, Q(13) => Q13, Q(14) => Q14, Q(15) => Q15, Q(16) => Q16, Q(17) => Q17 ); -- zero delayed outputs; -- actual outports are assigned in Path Delay Section SIGNAL EFORNeg_zd : std_logic ; SIGNAL PAENeg_zd : std_logic ; SIGNAL PAFNeg_zd : std_logic ; SIGNAL FFIRNeg_zd : std_logic ; SIGNAL WXOHFNeg_zd: std_logic ; SIGNAL RXONeg_zd : std_logic ; SIGNAL Q_zd : RAM_Word ; BEGIN -- VitalBehavior block ---------------------------------------------------------------------------- -- Timing Check Section -- ---------------------------------------------------------------------------- TimingChecks: PROCESS (D, RSNeg, WCLK, WENNeg, RCLK, RENNeg, OENeg, LDNeg, WXINeg, RXINeg) -- Timing Check Variables -- Pulse Width & Period Check Variables VARIABLE Pviol_WCLK : X01 := '0'; VARIABLE PD_WCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RCLK : X01 := '0'; VARIABLE PD_RCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RSNeg : X01 := '0'; VARIABLE PD_RSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WXINeg : X01 := '0'; VARIABLE PD_WXINeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RXINeg : X01 := '0'; VARIABLE PD_RXINeg : VitalPeriodDataType := VitalPeriodDataInit; -- Setup/Hold Check Variables VARIABLE Tviol_D0_WCLK : X01 := '0'; VARIABLE TD_D0_WCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_WCLK : X01 := '0'; VARIABLE TD_WENNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_RENNeg_RCLK : X01 := '0'; VARIABLE TD_RENNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_LDNeg_WCLK : X01 := '0'; VARIABLE TD_LDNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_LDNeg_RCLK : X01 := '0'; VARIABLE TD_LDNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_RSNeg : X01 := '0'; VARIABLE TD_WENNeg_RSNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_RSNeg : X01 := '0'; VARIABLE TD_RENNeg_RSNeg : VitalTimingDataType; VARIABLE Tviol_LDNeg_RSNeg : X01 := '0'; VARIABLE TD_LDNeg_RSNeg : VitalTimingDataType; VARIABLE Tviol_WXINeg_WCLK : X01 := '0'; VARIABLE TD_WXINeg_WCLK : VitalTimingDataType; VARIABLE Tviol_RXINeg_RCLK : X01 := '0'; VARIABLE TD_RXINeg_RCLK : VitalTimingDataType; -- Recovery Check Variables VARIABLE Rviol_WENNeg_RSNeg : X01 := '0'; VARIABLE RD_WENNeg_RSNeg : VitalTimingDataType; VARIABLE Rviol_RENNeg_RSNeg : X01 := '0'; VARIABLE RD_RENNeg_RSNeg : VitalTimingDataType; VARIABLE Rviol_LDNeg_RSNeg : X01 := '0'; VARIABLE RD_LDNeg_RSNeg : VitalTimingDataType; -- Skew Check Variables --VARIABLE Sviol_Skew1 : X01 := '0'; --VARIABLE Sviol_Skew2 : X01 := '0'; --VARIABLE WCLK_Last_Front : time :=0 ns; --VARIABLE RCLK_Last_Front : time :=0 ns; -- Violation variable (used to OR all individual violations) VARIABLE Violation : X01 := '0'; BEGIN -- timing checks process IF (TimingChecksOn) THEN Pviol_WCLK := '0'; Pviol_RCLK := '0'; Pviol_RSNeg := '0'; Pviol_WXINeg := '0'; Pviol_RXINeg := '0'; Tviol_D0_WCLK := '0'; Tviol_WENNeg_WCLK := '0'; Tviol_RENNeg_RCLK := '0'; Tviol_LDNeg_WCLK := '0'; Tviol_LDNeg_RCLK := '0'; Tviol_WENNeg_RSNeg := '0'; Tviol_RENNeg_RSNeg := '0'; Tviol_LDNeg_RSNeg := '0'; Tviol_WXINeg_WCLK := '0'; Tviol_RXINeg_RCLK := '0'; Rviol_WENNeg_RSNeg := '0'; Rviol_RENNeg_RSNeg := '0'; Rviol_LDNeg_RSNeg := '0'; --1 WCLK pulse (low & high) width and period check -- (tCLK, tCLKH, tCLKL) IF WCLK'event THEN VitalPeriodPulseCheck ( TestSignal => WCLK, TestSignalName => "WCLK", Period => tperiod_RCLK_posedge, PulseWidthHigh => tpw_RCLK_posedge, PulseWidthLow => tpw_RCLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WCLK); END IF; --2 RCLK pulse (low & high) width and period check -- (tCLK, tCLKH, tCLKL) IF RCLK'event THEN VitalPeriodPulseCheck ( TestSignal => RCLK, TestSignalName => "RCLK", Period => tperiod_RCLK_posedge, PulseWidthHigh => tpw_RCLK_posedge, PulseWidthLow => tpw_RCLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RCLK); END IF; --3 RSNeg low pulse width check (tRS) IF RSNeg'event THEN VitalPeriodPulseCheck ( TestSignal => RSNeg, TestSignalName => "RSNEg", PulseWidthLow => tpw_RSNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_RSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RSNeg); END IF; --4 WXINeg low pulse width check (tXI) IF WXINeg'event THEN VitalPeriodPulseCheck ( TestSignal => WXINeg, TestSignalName => "WXINEg", PulseWidthLow => tpw_RXINeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_WXINeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WXINeg); END IF; --5 RXIeg low pulse width check (tXI) IF RXINeg'event THEN VitalPeriodPulseCheck ( TestSignal => RXINeg, TestSignalName => "RXINEg", PulseWidthLow => tpw_RXINeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_RXINeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RXINeg); END IF; --6 D/WCLK setup/hold time check (tDS, tDH) IF D'event OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => D, TestSignalName => "D", RefSignal => WCLK, RefSignalName => "WCLK", SetupHigh => tsetup_D0_WCLK_noedge_posedge, SetupLow => tsetup_D0_WCLK_noedge_posedge, HoldHigh => thold_D0_WCLK_noedge_posedge, HoldLow => thold_D0_WCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_D0_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_WCLK); END IF; --7 WENNeg/WCLK setup/hold time check (tENS, tENH) IF WENNeg'event OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => WENNEg, TestSignalName => "WENNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_RENNeg_RCLK_noedge_posedge, HoldHigh => thold_RENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_WCLK); END IF; --8 RENNeg/RCLK setup/hold time check (tENS, tENH) IF RENNeg'event OR (RCLK'event AND RCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNEg, TestSignalName => "RENNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RENNeg_RCLK_noedge_posedge, HoldHigh => thold_RENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RCLK); END IF; --9 LDNeg/WCLK setup/hold time check (tLDS, tLDH) IF LDNeg'event OR (WCLK'event AND WCLK = '1' AND WENNeg ='0') THEN VitalSetupHoldCheck ( TestSignal => LDNEg, TestSignalName => "LDNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_RENNeg_RCLK_noedge_posedge, HoldHigh => thold_RENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_WCLK); END IF; --10 LDNeg/RCLK setup/hold time check (tLDS, tLDH) IF LDNeg'event OR (RCLK'event AND RCLK = '1' AND RENNeg ='0') THEN VitalSetupHoldCheck ( TestSignal => LDNEg, TestSignalName => "LDNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RENNeg_RCLK_noedge_posedge, HoldHigh => thold_RENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_RCLK); END IF; --11 RENNeg/RSNeg setup time check (tRSS) IF RENNeg'event OR (RSNeg'event AND RSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNEg, TestSignalName => "RENNeg", RefSignal => RSNEg, RefSignalName => "RSNEg", SetupHigh => tsetup_LDNeg_RSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_RSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RSNeg); END IF; --12 WENNeg/RSNeg setup time check (tRSS) IF WENNeg'event OR (RSNeg'event AND RSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => WENNEg, TestSignalName => "WENNeg", RefSignal => RSNEg, RefSignalName => "RSNEg", SetupHigh => tsetup_LDNeg_RSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_RSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_RSNeg); END IF; --13 LDNeg/RSNeg setup time check (tRSS) IF LDNeg'event OR (RSNeg'event AND RSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => LDNEg, TestSignalName => "LDNeg", RefSignal => RSNEg, RefSignalName => "RSNEg", SetupHigh => tsetup_LDNeg_RSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_RSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_RSNeg); END IF; --14 WXINeg/WCLK setup time check (tXIS) IF WXINeg'event OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => WXINeg, TestSignalName => "WXINeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_RXINeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WXINeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WXINeg_WCLK); END IF; --15 RXINeg/RCLK setup time check (tXIS) IF RXINeg'event OR (RCLK'event AND RCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => RXINeg, TestSignalName => "RXINeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RXINeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RXINeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RXINeg_RCLK); END IF; Violation := Pviol_WCLK OR Pviol_RCLK OR Pviol_RSNeg OR Pviol_WXINeg OR Pviol_RXINeg OR Tviol_D0_WCLK OR Tviol_WENNeg_WCLK OR Tviol_RENNeg_RCLK OR Tviol_LDNeg_WCLK OR Tviol_LDNeg_RCLK OR Tviol_WENNeg_RSNeg OR Tviol_RENNeg_RSNeg OR Tviol_LDNeg_RSNeg OR Tviol_WXINeg_WCLK OR Tviol_RXINeg_RCLK OR Rviol_WENNeg_RSNeg OR Rviol_RENNeg_RSNeg OR Rviol_LDNeg_RSNeg ; ASSERT Violation = '0' REPORT InstancePath & partID & " : signal values may be" & " incorret due timing violation(s)" SEVERITY Warning; END IF; END PROCESS TimingChecks; ---------------------------------------------------------------------------- -- Functionality section --------------------------------------------------- ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- FIFO Array -- ---------------------------------------------------------------------------- Input_Register: PROCESS (WCLK,Wr_RAM_Onint,D) BEGIN IF WCLK = '0' THEN IF (Wr_RAM_Onint='1') THEN Input_Regint <= D; END IF; END IF; END PROCESS; Memory: PROCESS(WCLK,Wr_RAM_Onint,Input_Regint,Wr_Pnt_Delint) BEGIN IF WCLK = '1' THEN IF (Wr_RAM_Delint='1') THEN RAM (to_nat(Wr_Pnt_Delint)) <= Input_Regint; END IF; END IF; END PROCESS; ---------------------------------------------------------------------------- -- Read/Write Pointer Logic -- ---------------------------------------------------------------------------- Wr_RAM_Onint <='1' WHEN (WENNeg='0') and (Fullint='0') and (LDNeg='1') and (Write_Enableint='1') ELSE '0'; Wr_RAM_Delint <='1' WHEN (WENNeg='0') and (FF_Delint='0') and (LDNeg='1') and (Write_Enableint='1') ELSE '0'; Rd_RAM_Onint <='1' WHEN (RENNeg='0') and (Emptyint='0') and (LDNeg='1') and (Read_Enableint='1') ELSE '0'; Write_Pointer_Register: PROCESS (RSNeg, WCLK) BEGIN IF RSNeg = '0' THEN Write_PRint <= (others =>'0') ; Write_Flint<='0'; ELSIF WCLK'event and WCLK='1' THEN IF (Wr_RAM_Onint='1') THEN Write_PRint <= to_slv(WritePnt_Sumint,AddrBitNum); Write_Flint<='1'; ELSE Write_Flint<='0'; END IF; END IF; END PROCESS; Write_Pointerint <= to_nat(Write_PRint) ; WritePnt_Sumint <= Write_Pointerint + 1; Write_Pointer_Delayed_Register: PROCESS (RSNeg, WCLK) BEGIN IF RSNeg = '0' THEN Wr_Pnt_Delint <= (others =>'0') ; ELSIF WCLK'event and WCLK='0' THEN Wr_Pnt_Delint <= Write_PRint; END IF; END PROCESS; Read_Pointer_Register: PROCESS (RSNeg, RCLK) BEGIN IF RSNeg = '0' THEN Read_PRint <= (others =>'0') ; Read_Flint<='0'; ELSIF RCLK'event and RCLK='1' THEN IF (Rd_RAM_Onint='1') or (Fst_Wrdint ='1') THEN Read_PRint <= to_slv(Read_Pointerint+1,AddrBitNum); Read_Flint<='1'; ELSE Read_Flint<='0'; END IF; END IF; END PROCESS; Read_Pointerint <= to_nat(Read_PRint) ; ---------------------------------------------------------------------------- -- Offset Register Logic -- ---------------------------------------------------------------------------- Wr_Ofs_Onint <='1' WHEN (WENNeg='0') and (LDNeg='0') --and (Write_Enableint='1') --always ELSE '0'; Rd_Ofs_Onint <='1' WHEN (RENNeg='0') and (LDNeg='0') and (Read_Enableint='1') ELSE --not always '0'; PAE_Offset_Register: PROCESS (RSNeg, WCLK) BEGIN IF RSNeg = '0' THEN PAE_Offset_Regint <= to_slv(Default_Val,OffsetLength); ELSIF WCLK'event and WCLK='1' THEN IF (Wr_Ofs_Onint='1') and (Wr_Offset_Pntint='0') THEN PAE_Offset_Regint <= D (OffsetLength-1 DOWNTO 0); END IF; END IF; END PROCESS; PAF_Offset_Register: PROCESS (RSNeg, WCLK) BEGIN IF RSNeg = '0' THEN PAF_Offset_Regint <= to_slv(Default_Val,OffsetLength); ELSIF WCLK'event and WCLK='1' THEN IF (Wr_Ofs_Onint='1') and (Wr_Offset_Pntint='1') THEN PAF_Offset_Regint <= D (OffsetLength-1 DOWNTO 0); END IF; END IF; END PROCESS; Wr_Offset_Pointer: PROCESS (RSNeg, WCLK) BEGIN IF RSNeg = '0' THEN Wr_Offset_Pntint <= '0' ; ELSIF WCLK'event and WCLK='1' THEN IF (Wr_Ofs_Onint='1') THEN Wr_Offset_Pntint <= not Wr_Offset_Pntint; END IF; END IF; END PROCESS; Rd_Offset_Pointer: PROCESS (RSNeg, RCLK) BEGIN IF RSNeg = '0' THEN Rd_Offset_Pntint <= '0'; ELSIF RCLK'event and RCLK='1' THEN IF (Rd_Ofs_Onint='1') THEN Rd_Offset_Pntint <= not Rd_Offset_Pntint; END IF; END IF; END PROCESS; ---------------------------------------------------------------------------- -- Flag Logic -- ---------------------------------------------------------------------------- Write_PRint_DEL <= Write_PRint after tdevice_SKEW1; Read_PRint_DEL <= Read_PRint after tdevice_SKEW1; Read_Flint_DEL <= Read_Flint after tdevice_SKEW1; Write_Flint_DEL <= Write_Flint after tdevice_SKEW1; -- Empty Flag -- (tskew1 realization) Emp_Setint <= '1' WHEN ((Write_PRint_DEL= to_slv(Read_Pointerint+1,AddrBitNum)) and (Rd_RAM_Onint='1')) ELSE '0'; Sng_Emp_Resint <= '1' -- for Single_Buffered_Empty_Flag WHEN ((Write_PRint_DEL= to_slv(Read_Pointerint+1,AddrBitNum)) and (Write_Flint_DEL='1')) ELSE '0'; for_Double_Buffered_Empty_Flag: PROCESS (RCLK) BEGIN IF RCLK'event and RCLK='1' THEN Dbl_Emp_Resint <= Sng_Emp_Resint; END IF; END PROCESS; Emp_Resint <= --Trp_Emp_Resint WHEN FWFTint='1' ELSE Dbl_Emp_Resint WHEN (Dbl_Bufint='1') or (FWFTint='1') ELSE Sng_Emp_Resint ; Empty_Flag: PROCESS (RSNeg, RCLK) BEGIN IF RSNeg = '0' THEN Emptyint <= '1' ; ELSIF RCLK'event and RCLK='1' THEN IF Emp_Setint ='1' THEN --sync set Emptyint <= '1' ; ELSIF Emp_Resint ='1' THEN --sync reset Emptyint <= '0' ; END IF; END IF; END PROCESS; --new process Empty_Del_Flag: PROCESS (RSNeg, RCLK) BEGIN IF RSNeg = '0' THEN EmpDint <= '1' ; ELSIF RCLK'event and RCLK='1' THEN EmpDint <= Emptyint ; END IF; END PROCESS; EFORNeg_zd <= EmpDint WHEN FWFTint='1' -- Output_Ready ELSE not Emptyint; ---------------------------------------------------------------------------- WrP_mn_RdPint <= Write_Pointerint - Read_Pointerint ; RdP_mn_WrPint <= Read_Pointerint - Write_Pointerint; -- Write_Pointer is greater that or equal to Read_Pointer WrP_GE_RdPint <= '1' WHEN (Write_Pointerint>=Read_Pointerint) --only for pre_reset simulation and (Write_PRint(0)/='U') and (Read_PRint(0)/='U') ELSE '0'; ---------------------------------------------------------------------------- -- PAE Flag AlmEmp_Setint <='1' WHEN ((WrP_GE_RdPint='1') and (WrP_mn_RdPint=to_nat(PAE_Offset_Regint))) or ((WrP_GE_RdPint='0') and (RdP_mn_WrPint=(RAMSize-to_nat(PAE_Offset_Regint))) ) ELSE '0'; AlmEmp_Resint <='1' WHEN ((WrP_GE_RdPint='1') and (WrP_mn_RdPint=(to_nat(PAE_Offset_Regint)+1)) ) or ((WrP_GE_RdPint='0') and (RdP_mn_WrPint=(RAMSize-(to_nat(PAE_Offset_Regint)+1))) ) ELSE '0'; Async_Almost_Empty_Flag: PROCESS (RSNeg, AlmEmp_Setint, AlmEmp_Resint) BEGIN IF (RSNeg='0') or (AlmEmp_Setint='1') THEN Almost_Emptyint <= '1'; ELSIF (AlmEmp_Resint='1') THEN Almost_Emptyint <= '0'; END IF; END PROCESS; -- (tskew2 realization) Sync_Almost_Empty_Flag: PROCESS (RSNeg, RCLK) BEGIN IF RSNeg = '0' THEN PAE_Syncint <= '1' ; ELSIF RCLK'event and RCLK='1' THEN IF (AlmEmp_Setint_DEL='1') THEN PAE_Syncint <= '1' ; ELSIF (AlmEmp_Resint_DEL='1') THEN PAE_Syncint <= '0' ; END IF; END IF; END PROCESS; PAENeg_zd <= not PAE_Syncint WHEN Syncint='1' ELSE not Almost_Emptyint; ---------------------------------------------------------------------------- -- Full Flag -- (tskew1 realization) Full_Setint <= '1' WHEN ((to_slv(WritePnt_Sumint,AddrBitNum) = Read_PRint_DEL) and (Wr_RAM_Onint='1')) ELSE '0'; --for_Single_Buffered_Full_Flag Sng_Full_Resint <= '1' WHEN (to_slv(WritePnt_Sumint,AddrBitNum)= Read_PRint_DEL) and (Read_Flint_DEL='1') ELSE '0'; for_Double_Buffered_Full_Flag: PROCESS (WCLK) BEGIN IF WCLK'event and WCLK='1' THEN Dbl_Full_Resint <= Sng_Full_Resint; END IF; END PROCESS; Full_Resint <= Dbl_Full_Resint WHEN ((Dbl_Bufint='1') or (FWFTint='1')) ELSE Sng_Full_Resint ; Full_Flag: PROCESS (RSNeg, WCLK) BEGIN IF RSNeg = '0' THEN Fullint <= '0'; ELSIF WCLK'event and WCLK='1' THEN IF Full_Setint = '1' THEN Fullint <= '1' ; --sync set ELSIF Full_Resint = '1' THEN Fullint <= '0' ; --sync reset END IF; END IF; END PROCESS; FFIRNeg_zd <= Fullint WHEN FWFTint='1' -- Input_Ready ELSE not Fullint; Full_Flag_Delayed_Tg: PROCESS (WCLK) BEGIN IF WCLK'event and WCLK='0' THEN FF_Delint <= Fullint; END IF; END PROCESS; ---------------------------------------------------------------------------- -- PAF Flag AlmFull_Setint <= '1' WHEN ((WrP_GE_RdPint='1') and (WrP_mn_RdPint=(RAMSize - to_nat(PAF_Offset_Regint))) ) or ((WrP_GE_RdPint='0') and ((RdP_mn_WrPint=to_nat(PAF_Offset_Regint)) -- only for reset simulation and (PAF_Offset_Regint(0)/='U') ) ) ELSE '0'; AlmFull_Resint <= '1' WHEN ((WrP_GE_RdPint='1') and (WrP_mn_RdPint=(RAMSize - (to_nat(PAF_Offset_Regint)+1))) ) or ((WrP_GE_RdPint='0') and (RdP_mn_WrPint=(to_nat(PAF_Offset_Regint)+1))) ELSE '0'; Async_Almost_Full_Flag: PROCESS (RSNeg, AlmFull_Resint, AlmFull_Setint) BEGIN IF (RSNeg='0') or (AlmFull_Resint='1') THEN Almost_Fullint <= '0'; ELSIF (AlmFull_Setint='1') THEN Almost_Fullint <= '1'; END IF; END PROCESS; SAlmFull_Setint <= '1' WHEN ((WrP_GE_RdPint='1') and (WrP_mn_RdPint=(RAMSize - (to_nat(PAF_Offset_Regint)+1))) ) or ((WrP_GE_RdPint='0') and ((RdP_mn_WrPint=to_nat(PAF_Offset_Regint)+1) -- only for reset simulation and (PAF_Offset_Regint(0)/='U') ) ) ELSE '0'; -- (tskew2 realization) AlmEmp_Setint_DEL <= AlmEmp_Setint after tdevice_SKEW2; AlmEmp_Resint_DEL <= AlmEmp_Resint after tdevice_SKEW2; SAlmFull_Setint_DEL <= SAlmFull_Setint after tdevice_SKEW2; AlmFull_Resint_DEL <= AlmFull_Resint after tdevice_SKEW2; Sync_Almost_Full_Flag: PROCESS (RSNeg, WCLK) BEGIN IF RSNeg = '0' THEN PAF_Syncint <= '0'; ELSIF WCLK'event and WCLK='1' THEN IF (SAlmFull_Setint_DEL='1') and (Wr_RAM_Onint='1') THEN PAF_Syncint <= '1' ; ELSIF (AlmFull_Resint_DEL='1') THEN PAF_Syncint <= '0' ; END IF; END IF; END PROCESS; PAFNeg_zd <= not PAF_Syncint WHEN Syncint='1' ELSE not Almost_Fullint ; ---------------------------------------------------------------------------- -- Half Full Flag HlfFull_Resint <= '1' WHEN ((WrP_GE_RdPint='1') and (WrP_mn_RdPint = HalfSize)) or ((WrP_GE_RdPint='0') and (RdP_mn_WrPint = HalfSize)) ELSE '0'; HlfFull_Setint <= '1' WHEN ((WrP_GE_RdPint='1') and (WrP_mn_RdPint = HalfSize+1)) or ((WrP_GE_RdPint='0') and (RdP_mn_WrPint = HalfSize-1)) ELSE '0'; Half_Full_Flag: PROCESS (RSNeg, HlfFull_Resint, HlfFull_Setint) BEGIN IF (RSNeg='0') or (HlfFull_Resint='1') THEN HFint <= '0'; ELSIF (HlfFull_Setint='1') THEN HFint <= '1'; END IF; END PROCESS; ---------------------------------------------------------------------------- -- Reset Configuration Logic -- ---------------------------------------------------------------------------- No_Expanint <= '1' WHEN (WXINeg='0') or (RXINeg='0') ELSE '0'; Res_FWFTint <= '1' WHEN (WXINeg='1') and (RXINeg='0') ELSE '0'; Res_Dbl_Bufint <= '1' WHEN (WXINeg='0') and (RXINeg='1') ELSE '0'; Res_Syncint <= '1' WHEN (FLNeg='1') and ((WXINeg='0') or (RXINeg='0')) ELSE '0'; Depth_Expansion_Mode: PROCESS (RSNeg, No_Expanint) BEGIN IF RSNeg = '0' THEN Depth_Expanint <= not No_Expanint; END IF; END PROCESS; FWFT_Mode: PROCESS (RSNeg, Res_FWFTint) BEGIN IF RSNeg = '0' THEN FWFTint <= Res_FWFTint; END IF; END PROCESS; PAE_PAF_Sync_Mode: PROCESS (RSNeg, Res_Syncint) BEGIN IF RSNeg = '0' THEN Syncint <= Res_Syncint; END IF; END PROCESS; Double_Buffered_Mode: PROCESS (RSNeg, Res_Dbl_Bufint) BEGIN IF RSNeg = '0' THEN Dbl_Bufint <= Res_Dbl_Bufint; END IF; END PROCESS; ---------------------------------------------------------------------------- -- Expansion Logic -- ---------------------------------------------------------------------------- Wr_En_Setint <= '1' WHEN ((RSNeg = '0') and ((No_Expanint = '1') or (FLNeg='0'))) or ((RSNeg = '1') and (Depth_Expanint='1') and (WXINeg='0')) ELSE '0'; Wr_En_Resint <= '1' WHEN ((RSNeg = '0') and ((No_Expanint = '0') and (FLNeg='1'))) ELSE '0'; Write_Enable_Mode: PROCESS(Wr_En_Setint,Wr_En_Resint,WCLK) BEGIN IF (Wr_En_Setint = '1') THEN Write_Enableint <= '1' ; ELSIF (Wr_En_Resint = '1') THEN Write_Enableint <= '0' ; ELSIF WCLK'event and WCLK='1' THEN IF Depth_Expanint='1' THEN IF (Wr_RAM_Onint='1') and (Write_Pointerint=(RAMSize-1)) THEN Write_Enableint <= '0'; END IF; END IF; END IF; END PROCESS; Rd_En_Setint <= '1' WHEN ((RSNeg = '0') and ((No_Expanint = '1') or (FLNeg='0'))) or ((RSNeg = '1') and (Depth_Expanint='1') and (RXINeg='0')) ELSE '0'; Rd_En_Resint <= '1' WHEN ((RSNeg = '0') and ((No_Expanint = '0') and (FLNeg='1'))) ELSE '0'; Read_Enable_Mode: PROCESS (Rd_En_Resint, Rd_En_Setint, RCLK) BEGIN IF Rd_En_Setint = '1' THEN Read_Enableint <= '1' ; ELSIF Rd_En_Resint='1' THEN Read_Enableint <= '0' ; ELSIF RCLK'event and RCLK='1' THEN IF Depth_Expanint='1' THEN IF (Rd_RAM_Onint='1') and (Read_Pointerint= (RAMSize-1)) THEN Read_Enableint <= '0'; END IF; END IF; END IF; END PROCESS; Read_Enable_Delay:PROCESS (RSNeg, RCLK) BEGIN IF RSNeg = '0' THEN Read_En_Delint <= '0' ; ELSIF RCLK'event and RCLK='1' THEN Read_En_Delint <= Read_Enableint ; END IF; END PROCESS; -- WXONeg Output ---------------------------------------------------------------------------- WXOHFNeg_zd <= not WXOint WHEN (Depth_Expanint='1') ELSE not HFint ; WX0_Trigger1: PROCESS (RSNeg,WXO_Tg2int,WCLK) BEGIN IF (RSNeg='0') or (WXO_Tg2int='1') THEN WXO_Tg1int <= '0'; ELSIF WCLK'event and WCLK='1' THEN IF (Wr_RAM_Onint='1') and (Write_Pointerint=(RAMSize-1)) THEN WXO_Tg1int<= '1'; END IF; END IF; END PROCESS; WX0_Trigger2: PROCESS (RSNeg, WCLK) BEGIN IF (RSNeg='0') THEN WXO_Tg2int <= '0'; ELSIF WCLK'event and WCLK='0' THEN WXO_Tg2int <= WXO_Tg1int; END IF; END PROCESS; WXOint<= WXO_Tg1int and (not WXO_Tg2int); -- RXONeg_zd Output ---------------------------------------------------------------------------- RX0_Trigger1: PROCESS (RSNeg,RXO_Tg2int,RCLK) BEGIN IF (RSNeg='0') or (RXO_Tg2int='1') THEN RXO_Tg1int <= '0'; ELSIF RCLK'event and RCLK='1' THEN IF (Rd_RAM_Onint='1') and (Read_Pointerint=(RAMSize-1)) THEN RXO_Tg1int<= '1'; END IF; END IF; END PROCESS; RX0_Trigger2: PROCESS (RSNeg, RCLK) BEGIN IF (RSNeg='0') THEN RXO_Tg2int <= '0'; ELSIF RCLK'event and RCLK='0' THEN RXO_Tg2int <= RXO_Tg1int; END IF; END PROCESS; RXONeg_zd <= not (RXO_Tg1int and (not RXO_Tg2int)) ; ---------------------------------------------------------------------------- -- Output Logic -- ---------------------------------------------------------------------------- Zerosint <=(others =>'0'); Data_Outint <= RAM(Read_Pointerint) WHEN (LDNeg='1') and (Emptyint='0') ELSE Zerosint&PAE_Offset_Regint WHEN (FWFTint='0') and (LDNeg='0') and (Rd_Offset_Pntint='0') ELSE Zerosint&PAF_Offset_Regint WHEN (FWFTint='0') and (LDNeg='0') and (Rd_Offset_Pntint='1') ELSE Output_Regint; Fst_Wrdint <='1' WHEN ((FWFTint='1') and (EmpDint='1') and (Emptyint ='0')) ELSE '0'; Output_Register: PROCESS (RSNeg, RCLK) BEGIN IF RSNeg = '0' THEN Output_Regint <= (others =>'0') ; ELSIF RCLK'event and RCLK='1' THEN IF (Fst_Wrdint ='1') THEN Output_Regint <= RAM(Read_Pointerint); ELSE IF (RENNeg='0') and (Read_Enableint='1') THEN Output_Regint <= Data_Outint; END IF; END IF; END IF; END PROCESS; Q_zd <= Output_Regint WHEN (OENeg='0') and (Read_En_Delint='1') ELSE (others => 'Z') ; ---------------------------------------------------------------------------- -- Path Delay Section -- ---------------------------------------------------------------------------- -- Path delay for EFORNeg ; PathDelay_EFORNeg: PROCESS (EFORNeg_zd) VARIABLE EFORNeg_GlitchData: VitalGlitchDataType; BEGIN VitalPathDelay01( OutSignal => EFORNeg, OutSignalName=> "EFORNeg", OutTemp => EFORNeg_zd, GlitchData => EFORNeg_GlitchData, Paths => ( 0 => (InputChangeTime => RSNeg'LAST_EVENT,-- PathDelay => tpd_RSNeg_EFORNeg,--tRSF PathCondition => TRUE ), 1 => (InputChangeTime => RCLK'LAST_EVENT,-- PathDelay => tpd_RCLK_EFORNeg,--tREF PathCondition => TRUE ) ) ); END PROCESS; -- Path delay for PAENeg ; PathDelay_PAENeg: PROCESS (PAENeg_zd) VARIABLE PAENeg_GlitchData: VitalGlitchDataType; BEGIN IF Syncint='0' THEN -- (asynchronous) VitalPathDelay01( OutSignal => PAENeg, OutSignalName=> "PAENeg", OutTemp => PAENeg_zd, GlitchData => PAENeg_GlitchData, Paths => ( 0 => (InputChangeTime => RSNeg'LAST_EVENT,-- PathDelay => tpd_RSNeg_EFORNeg,--tRSF PathCondition => TRUE ), 1 => (InputChangeTime => RCLK'LAST_EVENT,-- PathDelay => tpd_WCLK_PAENeg,--tPAEA PathCondition => (RENNeg='0') ), 2 => (InputChangeTime => WCLK'LAST_EVENT,-- PathDelay => tpd_WCLK_PAENeg,--tPAEA PathCondition => (WENNeg='0') ) ) ); ELSE -- (synchronous) VitalPathDelay01( OutSignal => PAENeg, OutSignalName=> "PAENeg", OutTemp => PAENeg_zd, GlitchData => PAENeg_GlitchData, Paths => ( 0 => (InputChangeTime => RSNeg'LAST_EVENT,-- PathDelay => tpd_RSNeg_EFORNeg,--tRSF PathCondition => TRUE ), 1 => (InputChangeTime => RCLK'LAST_EVENT,-- PathDelay => tpd_RCLK_PAENeg,--tPAES PathCondition => TRUE ) ) ); END IF;-- END PROCESS; -- Path delay for PAFNeg ; PathDelay_PAFNeg: PROCESS (PAFNeg_zd) VARIABLE PAFNeg_GlitchData: VitalGlitchDataType; BEGIN IF Syncint='0' THEN -- (asynchronous) VitalPathDelay01( OutSignal => PAFNeg, OutSignalName=> "PAFNeg", OutTemp => PAFNeg_zd, GlitchData => PAFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => RSNeg'LAST_EVENT,-- PathDelay => tpd_RSNeg_EFORNeg,--tRSF PathCondition => TRUE ), 1 => (InputChangeTime => RCLK'LAST_EVENT,-- PathDelay => tpd_RCLK_PAFNeg,--tPAFA PathCondition => (RENNeg='0') ), 2 => (InputChangeTime => WCLK'LAST_EVENT,-- PathDelay => tpd_RCLK_PAFNeg,--tPAFA PathCondition => (WENNeg='0') ) ) ); ELSE -- (synchronous) VitalPathDelay01( OutSignal => PAFNeg, OutSignalName=> "PAFNeg", OutTemp => PAFNeg_zd, GlitchData => PAFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => RSNeg'LAST_EVENT,-- PathDelay => tpd_RSNeg_EFORNeg,--tRSF PathCondition => TRUE ), 1 => (InputChangeTime => WCLK'LAST_EVENT,-- PathDelay => tpd_WCLK_PAFNeg,--tPAFS PathCondition => TRUE ) ) ); END IF;-- END PROCESS; -- Path delay for FFIRNeg ; PathDelay_FFIRNeg: PROCESS (FFIRNeg_zd) VARIABLE FFIRNeg_GlitchData: VitalGlitchDataType; BEGIN VitalPathDelay01( OutSignal => FFIRNeg, OutSignalName=> "FFIRNeg", OutTemp => FFIRNeg_zd, GlitchData => FFIRNeg_GlitchData, Paths => ( 0 => (InputChangeTime => RSNeg'LAST_EVENT,-- PathDelay => tpd_RSNeg_EFORNeg,--tRSF PathCondition => TRUE ), 1 => (InputChangeTime => WCLK'LAST_EVENT,-- PathDelay => tpd_WCLK_FFIRNeg,--tWFF PathCondition => TRUE ) ) ); END PROCESS; -- Path delay for WXOHFNeg ; PathDelay_WXOHFNeg: PROCESS (WXOHFNeg_zd) VARIABLE WXOHFNeg_GlitchData: VitalGlitchDataType; BEGIN VitalPathDelay01( OutSignal => WXOHFNeg, OutSignalName=> "WXOHFNeg", OutTemp => WXOHFNeg_zd, Mode => VitalTransport, GlitchData => WXOHFNeg_GlitchData, Paths => -- HF ( 0 => (InputChangeTime => RSNeg'LAST_EVENT,-- PathDelay => tpd_RSNeg_EFORNeg,--tRSF PathCondition => TRUE ), 1 => (InputChangeTime => RCLK'LAST_EVENT,-- PathDelay => tpd_RCLK_WXOHFNeg,--tHF PathCondition => (Depth_Expanint ='0') and (RENNeg='0') ), 2 => (InputChangeTime => WCLK'LAST_EVENT,-- PathDelay => tpd_RCLK_WXOHFNeg,--tHF PathCondition => (Depth_Expanint ='0') and (WENNeg='0') ), -- WXO 3 => (InputChangeTime => WCLK'LAST_EVENT,-- PathDelay => tpd_RCLK_RXONeg,--tXO PathCondition => (Depth_Expanint ='1') ) ) ); END PROCESS; -- Path delay for RXONeg ; PathDelay_RXONeg: PROCESS (RXONeg_zd) VARIABLE RXONeg_GlitchData: VitalGlitchDataType; BEGIN VitalPathDelay01( OutSignal => RXONeg, OutSignalName=> "RXONeg", OutTemp => RXONeg_zd, Mode => VitalTransport, GlitchData => RXONeg_GlitchData, Paths => ( 0 => (InputChangeTime => RSNeg'LAST_EVENT,-- PathDelay => tpd_RSNeg_EFORNeg,--tRSF PathCondition => TRUE ), 1 => (InputChangeTime => RCLK'LAST_EVENT,-- PathDelay => tpd_RCLK_RXONeg,--tXO PathCondition => TRUE ) ) ); END PROCESS; -- Path delay for Q ; PathDelay_Q_Gen: FOR i IN RAMWordLength-1 DOWNTO 0 GENERATE PathDelay_Q: PROCESS (Q_zd(i)) VARIABLE Q_GlitchData: VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => Q(i), OutSignalName=> "Q", OutTemp => Q_zd(i), GlitchData => Q_GlitchData, Paths => ( 0 => (InputChangeTime => OENeg'LAST_EVENT,-- PathDelay => tpd_OENeg_Q0,-- tOLZ/tOE/tOHZ PathCondition => TRUE ), 1 => (InputChangeTime => RSNeg'LAST_EVENT,-- PathDelay => tpd_RSNeg_Q0,--tRSF PathCondition => TRUE ), 2 => (InputChangeTime => RCLK'LAST_EVENT,-- PathDelay => tpd_RCLK_Q0,--tA PathCondition => (RENNeg='0') ) ), MsgOn => False ); END PROCESS; END GENERATE; END BLOCK VITALBehavior; END vhdl_behavioral;