-------------------------------------------------------------------------------- -- File Name: idt72v3670.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 B.Bizic 02 Nov 30 Initial release -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FIFO -- Technology: CMOS -- Part: IDT72V3670 -- -- Description: Supersync FIFO 8,192 x 36 with Bus Sizing -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY idt72v3670 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_D18 : VitalDelayType01 := VitalZeroDelay01; tipd_D19 : VitalDelayType01 := VitalZeroDelay01; tipd_D20 : VitalDelayType01 := VitalZeroDelay01; tipd_D21 : VitalDelayType01 := VitalZeroDelay01; tipd_D22 : VitalDelayType01 := VitalZeroDelay01; tipd_D23 : VitalDelayType01 := VitalZeroDelay01; tipd_D24 : VitalDelayType01 := VitalZeroDelay01; tipd_D25 : VitalDelayType01 := VitalZeroDelay01; tipd_D26 : VitalDelayType01 := VitalZeroDelay01; tipd_D27 : VitalDelayType01 := VitalZeroDelay01; tipd_D28 : VitalDelayType01 := VitalZeroDelay01; tipd_D29 : VitalDelayType01 := VitalZeroDelay01; tipd_D30 : VitalDelayType01 := VitalZeroDelay01; tipd_D31 : VitalDelayType01 := VitalZeroDelay01; tipd_D32 : VitalDelayType01 := VitalZeroDelay01; tipd_D33 : VitalDelayType01 := VitalZeroDelay01; tipd_D34 : VitalDelayType01 := VitalZeroDelay01; tipd_D35 : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK : VitalDelayType01 := VitalZeroDelay01; tipd_BENeg : VitalDelayType01 := VitalZeroDelay01; tipd_MRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_PRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_FWFT : VitalDelayType01 := VitalZeroDelay01; tipd_OW : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL1 : VitalDelayType01 := VitalZeroDelay01; tipd_WENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_IW : VitalDelayType01 := VitalZeroDelay01; tipd_PFM : VitalDelayType01 := VitalZeroDelay01; tipd_IP : VitalDelayType01 := VitalZeroDelay01; tipd_BM : VitalDelayType01 := VitalZeroDelay01; tipd_RM : VitalDelayType01 := VitalZeroDelay01; tipd_RTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_LDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK : VitalDelayType01 := VitalZeroDelay01; -- tpd delays -- tWFF tpd_WCLK_FFNeg : VitalDelayType01 := UnitDelay01; -- tPAFA tpd_RCLK_PAFNeg : VitalDelayType01 := UnitDelay01; -- tPAFS tpd_WCLK_PAFNeg : VitalDelayType01 := UnitDelay01; -- tHF tpd_WCLK_HFNeg : VitalDelayType01 := UnitDelay01; -- tRSF tpd_MRSNeg_EFNeg : VitalDelayType01 := UnitDelay01; -- tOLZ, tOHZ, tOE tpd_OENeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tREF tpd_RCLK_EFNeg : VitalDelayType01 := UnitDelay01; -- tPAEA tpd_WCLK_PAENeg : VitalDelayType01 := UnitDelay01; -- tPAES tpd_RCLK_PAENeg : VitalDelayType01 := UnitDelay01; -- tA tpd_RCLK_Q0 : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths -- tRS tpw_MRSNeg_negedge : VitalDelayType := UnitDelay; -- tCLKL tpw_RCLK_negedge : VitalDelayType := UnitDelay; -- tCLKH tpw_RCLK_posedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq -- tCLK tperiod_RCLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS tsetup_D0_WCLK : VitalDelayType := UnitDelay; -- tENS tsetup_RENNeg_RCLK : VitalDelayType := UnitDelay; -- tLDS tsetup_LDNeg_WCLK : VitalDelayType := UnitDelay; -- tRSS tsetup_RENNeg_MRSNeg : VitalDelayType := UnitDelay; -- tRTS tsetup_WENNeg_RCLK : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH thold_D0_WCLK : VitalDelayType := UnitDelay; -- tENH thold_RENNeg_RCLK : VitalDelayType := UnitDelay; -- tLDH thold_LDNeg_WCLK : VitalDelayType := UnitDelay; -- trecovery values: release times -- tRSR trecovery_RENNeg_MRSNeg : VitalDelayType := UnitDelay; -- tSKEW1 (skew time /RCLK/WCLK(for EF/FF) tdevice_SKEW1 : VitalDelayType := UnitDelay; -- tSKEW2 (skew time /RCLK/WCLK(for PAE/PAF) tdevice_SKEW2 : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN std_ulogic := 'U'; D1 : IN std_ulogic := 'U'; D2 : IN std_ulogic := 'U'; D3 : IN std_ulogic := 'U'; D4 : IN std_ulogic := 'U'; D5 : IN std_ulogic := 'U'; D6 : IN std_ulogic := 'U'; D7 : IN std_ulogic := 'U'; D8 : IN std_ulogic := 'U'; D9 : IN std_ulogic := 'U'; D10 : IN std_ulogic := 'U'; D11 : IN std_ulogic := 'U'; D12 : IN std_ulogic := 'U'; D13 : IN std_ulogic := 'U'; D14 : IN std_ulogic := 'U'; D15 : IN std_ulogic := 'U'; D16 : IN std_ulogic := 'U'; D17 : IN std_ulogic := 'U'; D18 : IN std_ulogic := 'U'; D19 : IN std_ulogic := 'U'; D20 : IN std_ulogic := 'U'; D21 : IN std_ulogic := 'U'; D22 : IN std_ulogic := 'U'; D23 : IN std_ulogic := 'U'; D24 : IN std_ulogic := 'U'; D25 : IN std_ulogic := 'U'; D26 : IN std_ulogic := 'U'; D27 : IN std_ulogic := 'U'; D28 : IN std_ulogic := 'U'; D29 : IN std_ulogic := 'U'; D30 : IN std_ulogic := 'U'; D31 : IN std_ulogic := 'U'; D32 : IN std_ulogic := 'U'; D33 : IN std_ulogic := 'U'; D34 : IN std_ulogic := 'U'; D35 : IN std_ulogic := 'U'; Q0 : OUT std_ulogic := 'U'; Q1 : OUT std_ulogic := 'U'; Q2 : OUT std_ulogic := 'U'; Q3 : OUT std_ulogic := 'U'; Q4 : OUT std_ulogic := 'U'; Q5 : OUT std_ulogic := 'U'; Q6 : OUT std_ulogic := 'U'; Q7 : OUT std_ulogic := 'U'; Q8 : OUT std_ulogic := 'U'; Q9 : OUT std_ulogic := 'U'; Q10 : OUT std_ulogic := 'U'; Q11 : OUT std_ulogic := 'U'; Q12 : OUT std_ulogic := 'U'; Q13 : OUT std_ulogic := 'U'; Q14 : OUT std_ulogic := 'U'; Q15 : OUT std_ulogic := 'U'; Q16 : OUT std_ulogic := 'U'; Q17 : OUT std_ulogic := 'U'; Q18 : OUT std_ulogic := 'U'; Q19 : OUT std_ulogic := 'U'; Q20 : OUT std_ulogic := 'U'; Q21 : OUT std_ulogic := 'U'; Q22 : OUT std_ulogic := 'U'; Q23 : OUT std_ulogic := 'U'; Q24 : OUT std_ulogic := 'U'; Q25 : OUT std_ulogic := 'U'; Q26 : OUT std_ulogic := 'U'; Q27 : OUT std_ulogic := 'U'; Q28 : OUT std_ulogic := 'U'; Q29 : OUT std_ulogic := 'U'; Q30 : OUT std_ulogic := 'U'; Q31 : OUT std_ulogic := 'U'; Q32 : OUT std_ulogic := 'U'; Q33 : OUT std_ulogic := 'U'; Q34 : OUT std_ulogic := 'U'; Q35 : OUT std_ulogic := 'U'; FFNeg : OUT std_ulogic := 'U'; PAFNeg : OUT std_ulogic := 'U'; EFNeg : OUT std_ulogic := 'U'; PAENeg : OUT std_ulogic := 'U'; HFNeg : OUT std_ulogic := 'U'; WCLK : IN std_ulogic := 'U'; BENeg : IN std_ulogic := 'U'; MRSNeg : IN std_ulogic := 'U'; PRSNeg : IN std_ulogic := 'U'; FWFT : IN std_ulogic := 'U'; OW : IN std_ulogic := 'U'; FSEL0 : IN std_ulogic := 'U'; FSEL1 : IN std_ulogic := 'U'; WENNeg : IN std_ulogic := 'U'; IW : IN std_ulogic := 'U'; PFM : IN std_ulogic := 'U'; IP : IN std_ulogic := 'U'; BM : IN std_ulogic := 'U'; RM : IN std_ulogic := 'U'; RTNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; LDNeg : IN std_ulogic := 'U'; RENNeg : IN std_ulogic := 'U'; SENNeg : IN std_ulogic := 'U'; RCLK : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of idt72v3670 : ENTITY IS TRUE; END idt72v3670; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of idt72v3670 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : String := "IDT723670"; CONSTANT TotalLoc : POSITIVE := 8192; CONSTANT HalfLoc : POSITIVE := 4096; CONSTANT MaxData : POSITIVE := 511; CONSTANT HiDbit : NATURAL := 35; SIGNAL D0_ipd : std_ulogic := 'U'; SIGNAL D1_ipd : std_ulogic := 'U'; SIGNAL D2_ipd : std_ulogic := 'U'; SIGNAL D3_ipd : std_ulogic := 'U'; SIGNAL D4_ipd : std_ulogic := 'U'; SIGNAL D5_ipd : std_ulogic := 'U'; SIGNAL D6_ipd : std_ulogic := 'U'; SIGNAL D7_ipd : std_ulogic := 'U'; SIGNAL D8_ipd : std_ulogic := 'U'; SIGNAL D9_ipd : std_ulogic := 'U'; SIGNAL D10_ipd : std_ulogic := 'U'; SIGNAL D11_ipd : std_ulogic := 'U'; SIGNAL D12_ipd : std_ulogic := 'U'; SIGNAL D13_ipd : std_ulogic := 'U'; SIGNAL D14_ipd : std_ulogic := 'U'; SIGNAL D15_ipd : std_ulogic := 'U'; SIGNAL D16_ipd : std_ulogic := 'U'; SIGNAL D17_ipd : std_ulogic := 'U'; SIGNAL D18_ipd : std_ulogic := 'U'; SIGNAL D19_ipd : std_ulogic := 'U'; SIGNAL D20_ipd : std_ulogic := 'U'; SIGNAL D21_ipd : std_ulogic := 'U'; SIGNAL D22_ipd : std_ulogic := 'U'; SIGNAL D23_ipd : std_ulogic := 'U'; SIGNAL D24_ipd : std_ulogic := 'U'; SIGNAL D25_ipd : std_ulogic := 'U'; SIGNAL D26_ipd : std_ulogic := 'U'; SIGNAL D27_ipd : std_ulogic := 'U'; SIGNAL D28_ipd : std_ulogic := 'U'; SIGNAL D29_ipd : std_ulogic := 'U'; SIGNAL D30_ipd : std_ulogic := 'U'; SIGNAL D31_ipd : std_ulogic := 'U'; SIGNAL D32_ipd : std_ulogic := 'U'; SIGNAL D33_ipd : std_ulogic := 'U'; SIGNAL D34_ipd : std_ulogic := 'U'; SIGNAL D35_ipd : std_ulogic := 'U'; SIGNAL WCLK_ipd : std_ulogic := 'U'; SIGNAL BENeg_ipd : std_ulogic := 'U'; SIGNAL MRSNeg_ipd : std_ulogic := 'U'; SIGNAL PRSNeg_ipd : std_ulogic := 'U'; SIGNAL FWFT_ipd : std_ulogic := 'U'; SIGNAL OW_ipd : std_ulogic := 'U'; SIGNAL FSEL0_ipd : std_ulogic := 'U'; SIGNAL FSEL1_ipd : std_ulogic := 'U'; SIGNAL WENNeg_ipd : std_ulogic := 'U'; SIGNAL IW_ipd : std_ulogic := 'U'; SIGNAL PFM_ipd : std_ulogic := 'U'; SIGNAL IP_ipd : std_ulogic := 'U'; SIGNAL BM_ipd : std_ulogic := 'U'; SIGNAL RM_ipd : std_ulogic := 'U'; SIGNAL RTNeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL LDNeg_ipd : std_ulogic := 'U'; SIGNAL RENNeg_ipd : std_ulogic := 'U'; SIGNAL SENNeg_ipd : std_ulogic := 'U'; SIGNAL RCLK_ipd : std_ulogic := 'U'; -- SKEW stuff ALIAS tSKEW1 : VitalDelayType IS tdevice_SKEW1; ALIAS tSKEW2 : VitalDelayType IS tdevice_SKEW2; SIGNAL OpenIn, OpenOut : std_logic; BEGIN -------------------------------------------------------------------------------- -- Dummy instances for exporting tSKEW vals from SDF file -- using DEVICE construct -------------------------------------------------------------------------------- SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1)); SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0); w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1); w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2); w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3); w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4); w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5); w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6); w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7); w_9 : VitalWireDelay (D8_ipd, D8, tipd_D8); w_10 : VitalWireDelay (D9_ipd, D9, tipd_D9); w_11 : VitalWireDelay (D10_ipd, D10, tipd_D10); w_12 : VitalWireDelay (D11_ipd, D11, tipd_D11); w_13 : VitalWireDelay (D12_ipd, D12, tipd_D12); w_14 : VitalWireDelay (D13_ipd, D13, tipd_D13); w_15 : VitalWireDelay (D14_ipd, D14, tipd_D14); w_16 : VitalWireDelay (D15_ipd, D15, tipd_D15); w_17 : VitalWireDelay (D16_ipd, D16, tipd_D16); w_18 : VitalWireDelay (D17_ipd, D17, tipd_D17); w_19 : VitalWireDelay (D18_ipd, D18, tipd_D18); w_20 : VitalWireDelay (D19_ipd, D19, tipd_D19); w_21 : VitalWireDelay (D20_ipd, D20, tipd_D20); w_22 : VitalWireDelay (D21_ipd, D21, tipd_D21); w_23 : VitalWireDelay (D22_ipd, D22, tipd_D22); w_24 : VitalWireDelay (D23_ipd, D23, tipd_D23); w_25 : VitalWireDelay (D24_ipd, D24, tipd_D24); w_26 : VitalWireDelay (D25_ipd, D25, tipd_D25); w_27 : VitalWireDelay (D26_ipd, D26, tipd_D26); w_28 : VitalWireDelay (D27_ipd, D27, tipd_D27); w_29 : VitalWireDelay (D28_ipd, D28, tipd_D28); w_30 : VitalWireDelay (D29_ipd, D29, tipd_D29); w_31 : VitalWireDelay (D30_ipd, D30, tipd_D30); w_32 : VitalWireDelay (D31_ipd, D31, tipd_D31); w_33 : VitalWireDelay (D32_ipd, D32, tipd_D32); w_34 : VitalWireDelay (D33_ipd, D33, tipd_D33); w_35 : VitalWireDelay (D34_ipd, D34, tipd_D34); w_36 : VitalWireDelay (D35_ipd, D35, tipd_D35); w_78 : VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK); w_79 : VitalWireDelay (BENeg_ipd, BENeg, tipd_BENeg); w_80 : VitalWireDelay (MRSNeg_ipd, MRSNeg, tipd_MRSNeg); w_81 : VitalWireDelay (PRSNeg_ipd, PRSNeg, tipd_PRSNeg); w_82 : VitalWireDelay (FWFT_ipd, FWFT, tipd_FWFT); w_83 : VitalWireDelay (OW_ipd, OW, tipd_OW); w_84 : VitalWireDelay (FSEL0_ipd, FSEL0, tipd_FSEL0); w_85 : VitalWireDelay (FSEL1_ipd, FSEL1, tipd_FSEL1); w_86 : VitalWireDelay (WENNeg_ipd, WENNeg, tipd_WENNeg); w_87 : VitalWireDelay (IW_ipd, IW, tipd_IW); w_88 : VitalWireDelay (PFM_ipd, PFM, tipd_PFM); w_89 : VitalWireDelay (IP_ipd, IP, tipd_IP); w_90 : VitalWireDelay (BM_ipd, BM, tipd_BM); w_91 : VitalWireDelay (RM_ipd, RM, tipd_RM); w_92 : VitalWireDelay (RTNeg_ipd, RTNeg, tipd_RTNeg); w_93 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_94 : VitalWireDelay (LDNeg_ipd, LDNeg, tipd_LDNeg); w_95 : VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg); w_96 : VitalWireDelay (SENNeg_ipd, SENNeg, tipd_SENNeg); w_97 : VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( DIn : IN std_logic_vector(35 DOWNTO 0); WCLKIn : IN std_ulogic := 'U'; BENegIn : IN std_ulogic := 'U'; MRSNegIn : IN std_ulogic := 'U'; PRSNegIn : IN std_ulogic := 'U'; FWFTIn : IN std_ulogic := 'U'; OWIn : IN std_ulogic := 'U'; FSEL0In : IN std_ulogic := 'U'; FSEL1In : IN std_ulogic := 'U'; WENNegIn : IN std_ulogic := 'U'; IWIn : IN std_ulogic := 'U'; PFMIn : IN std_ulogic := 'U'; IPIn : IN std_ulogic := 'U'; BMIn : IN std_ulogic := 'U'; RMIn : IN std_ulogic := 'U'; RTNegIn : IN std_ulogic := 'U'; OENegIn : IN std_ulogic := 'U'; LDNegIn : IN std_ulogic := 'U'; RENNegIn : IN std_ulogic := 'U'; SENNegIn : IN std_ulogic := 'U'; RCLKIn : IN std_ulogic := 'U'; QOut : OUT std_logic_vector(35 downto 0); FFNegOut : OUT std_ulogic := 'U'; EFNegOut : OUT std_ulogic := 'U'; HFNegOut : OUT std_ulogic := 'U'; PAFNegOut : OUT std_ulogic := 'U'; PAENegOut : OUT std_ulogic := 'U' ); PORT MAP ( DIn(0) => D0_ipd, DIn(1) => D1_ipd, DIn(2) => D2_ipd, DIn(3) => D3_ipd, DIn(4) => D4_ipd, DIn(5) => D5_ipd, DIn(6) => D6_ipd, DIn(7) => D7_ipd, DIn(8) => D8_ipd, DIn(9) => D9_ipd, DIn(10) => D10_ipd, DIn(11) => D11_ipd, DIn(12) => D12_ipd, DIn(13) => D13_ipd, DIn(14) => D14_ipd, DIn(15) => D15_ipd, DIn(16) => D16_ipd, DIn(17) => D17_ipd, DIn(18) => D18_ipd, DIn(19) => D19_ipd, DIn(20) => D20_ipd, DIn(21) => D21_ipd, DIn(22) => D22_ipd, DIn(23) => D23_ipd, DIn(24) => D24_ipd, DIn(25) => D25_ipd, DIn(26) => D26_ipd, DIn(27) => D27_ipd, DIn(28) => D28_ipd, DIn(29) => D29_ipd, DIn(30) => D30_ipd, DIn(31) => D31_ipd, DIn(32) => D32_ipd, DIn(33) => D33_ipd, DIn(34) => D34_ipd, DIn(35) => D35_ipd, QOut(0) => Q0, QOut(1) => Q1, QOut(2) => Q2, QOut(3) => Q3, QOut(4) => Q4, QOut(5) => Q5, QOut(6) => Q6, QOut(7) => Q7, QOut(8) => Q8, QOut(9) => Q9, QOut(10) => Q10, QOut(11) => Q11, QOut(12) => Q12, QOut(13) => Q13, QOut(14) => Q14, QOut(15) => Q15, QOut(16) => Q16, QOut(17) => Q17, QOut(18) => Q18, QOut(19) => Q19, QOut(20) => Q20, QOut(21) => Q21, QOut(22) => Q22, QOut(23) => Q23, QOut(24) => Q24, QOut(25) => Q25, QOut(26) => Q26, QOut(27) => Q27, QOut(28) => Q28, QOut(29) => Q29, QOut(30) => Q30, QOut(31) => Q31, QOut(32) => Q32, QOut(33) => Q33, QOut(34) => Q34, QOut(35) => Q35, WCLKIn => WCLK_ipd, BENegIn => To_UX01(BENeg_ipd), MRSNegIn => To_UX01(MRSNeg_ipd), PRSNegIn => To_UX01(PRSNeg_ipd), FWFTIn => To_UX01(FWFT_ipd), OWIn => To_UX01(OW_ipd), FSEL0In => To_UX01(FSEL0_ipd), FSEL1In => To_UX01(FSEL1_ipd), WENNegIn => To_UX01(WENNeg_ipd), IWIn => To_UX01(IW_ipd), PFMIn => To_UX01(PFM_ipd), IPIn => To_UX01(IP_ipd), BMIn => To_UX01(BM_ipd), RMIn => To_UX01(RM_ipd), RTNegIn => To_UX01(RTNeg_ipd), OENegIn => To_UX01(OENeg_ipd), LDNegIn => To_UX01(LDNeg_ipd), RENNegIn => To_UX01(RENNeg_ipd), SENNegIn => SENNeg_ipd, RCLKIn => RCLK_ipd, FFNegOut => FFNeg, EFNegOut => EFNeg, HFNegOut => HFNeg, PAFNegOut => PAFNeg, PAENegOut => PAENeg ); SIGNAL Q_zd : std_logic_vector(35 downto 0) := (others => 'Z'); SIGNAL mreset : boolean := false; BEGIN ------------------------------------------------------------------------ -- Behavior Process ------------------------------------------------------------------------ Fifo : PROCESS (DIn, WCLKIn, BENegIn, MRSNegIn, PRSNegIn, FWFTIn, OWIn, FSEL0In, FSEL1In, WENNegIn, IWIn, PFMIn, IPIn, BMIn, RMIn, RTNegIn, OENegIn, LDNegIn, RENNegIn, SENNegIn, RCLKIn) TYPE programming_method IS (parallel, serial); TYPE offset_type IS ARRAY (0 TO 7) OF positive; CONSTANT offsetps : offset_type := (127, 255, 511, 63, 1023, 15, 31, 7); -- Timing Check Variables VARIABLE Tviol_D_WCLK : X01 := '0'; VARIABLE TD_D_WCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_WCLK : X01 := '0'; VARIABLE TD_WENNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_RCLK : X01 := '0'; VARIABLE TD_WENNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_SENNeg_WCLK : X01 := '0'; VARIABLE TD_SENNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_LDNeg_WCLK : X01 := '0'; VARIABLE TD_LDNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_LDNeg_RCLK : X01 := '0'; VARIABLE TD_LDNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_MRSNeg : X01 := '0'; VARIABLE TD_WENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_MRSNeg : X01 := '0'; VARIABLE TD_RENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_SENNeg_MRSNeg : X01 := '0'; VARIABLE TD_SENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FWFT_MRSNeg : X01 := '0'; VARIABLE TD_FWFT_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FSEL1_MRSNeg : X01 := '0'; VARIABLE TD_FSEL1_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FSEL0_MRSNeg : X01 := '0'; VARIABLE TD_FSEL0_MRSNeg : VitalTimingDataType; VARIABLE Tviol_BM_MRSNeg : X01 := '0'; VARIABLE TD_BM_MRSNeg : VitalTimingDataType; VARIABLE Tviol_OW_MRSNeg : X01 := '0'; VARIABLE TD_OW_MRSNeg : VitalTimingDataType; VARIABLE Tviol_IW_MRSNeg : X01 := '0'; VARIABLE TD_IW_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RM_MRSNeg : X01 := '0'; VARIABLE TD_RM_MRSNeg : VitalTimingDataType; VARIABLE Tviol_IP_MRSNeg : X01 := '0'; VARIABLE TD_IP_MRSNeg : VitalTimingDataType; VARIABLE Tviol_LDNeg_MRSNeg : X01 := '0'; VARIABLE TD_LDNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_BENeg_MRSNeg : X01 := '0'; VARIABLE TD_BENeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RTNeg_MRSNeg : X01 := '0'; VARIABLE TD_RTNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RTNeg_PRSNeg : X01 := '0'; VARIABLE TD_RTNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_PRSNeg : X01 := '0'; VARIABLE TD_RENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_SENNeg_PRSNeg : X01 := '0'; VARIABLE TD_SENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_WENNeg_PRSNeg : X01 := '0'; VARIABLE TD_WENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_RCLK : X01 := '0'; VARIABLE TD_RENNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_RTNeg_RCLK : X01 := '0'; VARIABLE TD_RTNeg_RCLK : VitalTimingDataType; VARIABLE Rviol_RENNeg_MRSNeg : X01 := '0'; VARIABLE RD_RENNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_WENNeg_MRSNeg : X01 := '0'; VARIABLE RD_WENNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_FWFT_MRSNeg : X01 := '0'; VARIABLE RD_FWFT_MRSNeg : VitalTimingDataType; VARIABLE Rviol_LDNeg_MRSNeg : X01 := '0'; VARIABLE RD_LDNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_RENNeg_PRSNeg : X01 := '0'; VARIABLE RD_RENNeg_PRSNeg : VitalTimingDataType; VARIABLE Rviol_WENNeg_PRSNeg : X01 := '0'; VARIABLE RD_WENNeg_PRSNeg : VitalTimingDataType; VARIABLE Pviol_MRSNeg : X01 := '0'; VARIABLE PD_MRSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRSNeg : X01 := '0'; VARIABLE PD_PRSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RCLK : X01 := '0'; VARIABLE PD_RCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WCLK : X01 := '0'; VARIABLE PD_WCLK : VitalPeriodDataType := VitalPeriodDataInit; -- Memory array declaration TYPE MemStore IS ARRAY (0 to TotalLOC + 1) OF NATURAL RANGE 0 TO MaxData; -- Functionality Results Variables VARIABLE Violation : X01 := '0'; VARIABLE EFNeg_zd : std_ulogic; VARIABLE EFNeg_dly : std_ulogic; VARIABLE HFNeg_zd : std_ulogic; VARIABLE FFNeg_zd : std_ulogic; VARIABLE FFNeg_dly : std_ulogic; VARIABLE PAFNeg_zd : std_ulogic; VARIABLE PAENeg_zd : std_ulogic; VARIABLE Qreg : std_logic_vector(35 downto 0) := (others => '0'); VARIABLE mrs_done : boolean := false; VARIABLE fwft : boolean := false; VARIABLE be : boolean := false; VARIABLE bm : boolean := false; VARIABLE iw : boolean := false; VARIABLE ow : boolean := false; VARIABLE ip : boolean := false; VARIABLE spfm : boolean := false; VARIABLE nlrtm : boolean := false; VARIABLE minskew1RW : boolean := true; VARIABLE minskew2WR : boolean := true; VARIABLE delayed_ef : boolean := false; VARIABLE delayed_ff : boolean := false; VARIABLE memA : MemStore; VARIABLE memB : MemStore; VARIABLE memC : MemStore; VARIABLE memD : MemStore; VARIABLE programming : programming_method; VARIABLE tRCLKposedge : Time := 0 ns; VARIABLE tWCLKposedge : Time := 0 ns; VARIABLE rdptr : natural RANGE 0 TO TotalLOC + 1; --read pointer VARIABLE wrptr : natural RANGE 0 TO TotalLOC + 1; --write pointer VARIABLE paeoff : natural RANGE 0 TO TotalLOC; --pae offset VARIABLE pafoff : natural RANGE 0 TO TotalLOC; --paf offset VARIABLE opi : natural RANGE 0 TO 7; --offset preset index VARIABLE count : natural RANGE 0 TO TotalLOC + 1; --memory used VARIABLE fwftcnt : natural RANGE 0 TO 3; -- fwft RCLK counter VARIABLE opireg : std_logic_vector(2 downto 0); VARIABLE outreg : std_logic_vector(35 downto 0); VARIABLE outtmp : std_logic_vector(35 downto 0); VARIABLE bm_reg : std_logic_vector(2 downto 0); VARIABLE bm_Incnt : natural RANGE 0 TO 3 := 0; VARIABLE bm_Outcnt: natural RANGE 0 TO 3 := 0; VARIABLE fl_Outcnt: natural RANGE 0 TO 3 := 0; VARIABLE tmp_reg : std_logic_vector(16 downto 0); VARIABLE fp_Incnt : natural RANGE 0 to 5 := 0; VARIABLE fs_Incnt : natural RANGE 0 to 26 := 0; VARIABLE tmp_ser_in : std_logic_vector(25 downto 0) := (OTHERS=>'0'); VARIABLE zl_retransmit : boolean :=false; VARIABLE sl_retransmit : boolean :=false; -- Output Glitch Detection Variables VARIABLE FFNeg_GlitchData : VitalGlitchDataType; VARIABLE PAFNeg_GlitchData : VitalGlitchDataType; VARIABLE EFNeg_GlitchData : VitalGlitchDataType; VARIABLE PAENeg_GlitchData : VitalGlitchDataType; VARIABLE HFNeg_GlitchData : VitalGlitchDataType; BEGIN ---------------------------------------------------------------------------- -- Timing Check Section ---------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- tDS, tDH VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "D", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_D0_WCLK, SetupLow => tsetup_D0_WCLK, HoldHigh => thold_D0_WCLK, HoldLow => thold_D0_WCLK, CheckEnabled => (WENNegIn = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_D_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_WCLK ); -- tENS, tENH VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RCLK ); -- tENS, tENH VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_WCLK ); -- tENS, tENH VitalSetupHoldCheck ( TestSignal => SENNegIn, TestSignalName => "SENNeg", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_WCLK ); -- tENS, tENH VitalSetupHoldCheck ( TestSignal => RTNegIn, TestSignalName => "RTNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RTNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_RCLK ); -- tLDS, tLDH VitalSetupHoldCheck ( TestSignal => LDNegIn, TestSignalName => "LDNeg", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_LDNeg_WCLK, SetupLow => tsetup_LDNeg_WCLK, HoldHigh => thold_LDNeg_WCLK, HoldLow => thold_LDNeg_WCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_LDNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_WCLK ); -- tLDS, tLDH VitalSetupHoldCheck ( TestSignal => LDNegIn, TestSignalName => "LDNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_LDNeg_WCLK, SetupLow => tsetup_LDNeg_WCLK, HoldHigh => thold_LDNeg_WCLK, HoldLow => thold_LDNeg_WCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_LDNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_RCLK ); -- tRTS VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_WENNeg_RCLK, SetupLow => tsetup_WENNeg_RCLK, CheckEnabled => (RTNegIn = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_RCLK ); -- tRSS VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => SENNegIn, TestSignalName => "SENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => FWFTIn, TestSignalName => "FWFT", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_FWFT_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFT_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => FSEL1In, TestSignalName => "FSEL1", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_FSEL1_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FSEL1_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => FSEL0In, TestSignalName => "FSEL0", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_FSEL0_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FSEL0_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => BMIn, TestSignalName => "BM", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_BM_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BM_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => OWIn, TestSignalName => "OW", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_OW_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_OW_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => RMIn, TestSignalName => "RM", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RM_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RM_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => IPIn, TestSignalName => "IP", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_IP_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IP_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => IWIn, TestSignalName => "IW", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_IW_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IW_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => LDNegIn, TestSignalName => "LDNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_LDNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => BENegIn, TestSignalName => "BENeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_BENeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BENeg_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => RTNegIn, TestSignalName => "RTNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RTNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_PRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_PRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => SENNegIn, TestSignalName => "SENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_PRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => RTNegIn, TestSignalName => "RTNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RTNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_PRSNeg ); -- tRSR VitalRecoveryRemovalCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_RENNeg_MRSNeg ); -- tRSR VitalRecoveryRemovalCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_WENNeg_MRSNeg ); -- tRSR VitalRecoveryRemovalCheck ( TestSignal => FWFTIn, TestSignalName => "FWFT", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_FWFT_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_FWFT_MRSNeg ); -- tRSR VitalRecoveryRemovalCheck ( TestSignal => LDNegIn, TestSignalName => "LDNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_LDNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_LDNeg_MRSNeg ); -- tRSR VitalRecoveryRemovalCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_RENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_RENNeg_PRSNeg ); -- tRSR VitalRecoveryRemovalCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_WENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_WENNeg_PRSNeg ); -- tRS VitalPeriodPulseCheck ( TestSignal => MRSNegIn, TestSignalName => "MRSNeg", PulseWidthLow => tpw_MRSNeg_negedge, HeaderMsg => InstancePath & partID, CheckEnabled => TRUE, PeriodData => PD_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MRSNeg ); -- tRS VitalPeriodPulseCheck ( TestSignal => PRSNegIn, TestSignalName => "PRSNeg", PulseWidthLow => tpw_MRSNeg_negedge, HeaderMsg => InstancePath & partID, CheckEnabled => TRUE, PeriodData => PD_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_PRSNeg ); -- tCLKL, tCLKH VitalPeriodPulseCheck ( TestSignal => RCLKIn, TestSignalName => "RCLK", PulseWidthLow => tpw_RCLK_negedge, PulseWidthHigh => tpw_RCLK_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => TRUE, PeriodData => PD_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RCLK ); -- tCLKL, tCLKH VitalPeriodPulseCheck ( TestSignal => WCLKIn, TestSignalName => "WCLK", PulseWidthLow => tpw_RCLK_negedge, PulseWidthHigh => tpw_RCLK_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => TRUE, PeriodData => PD_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WCLK ); Violation := Tviol_D_WCLK OR Tviol_WENNeg_WCLK OR Tviol_WENNeg_RCLK OR Tviol_SENNeg_WCLK OR Tviol_LDNeg_WCLK OR Tviol_LDNeg_RCLK OR Tviol_WENNeg_MRSNeg OR Tviol_RENNeg_MRSNeg OR Tviol_SENNeg_MRSNeg OR Tviol_FWFT_MRSNeg OR Tviol_FSEL1_MRSNeg OR Tviol_FSEL0_MRSNeg OR Tviol_BM_MRSNeg OR Tviol_OW_MRSNeg OR Tviol_IW_MRSNeg OR Tviol_RM_MRSNeg OR Tviol_IP_MRSNeg OR Tviol_LDNeg_MRSNeg OR Tviol_BENeg_MRSNeg OR Tviol_RTNeg_MRSNeg OR Tviol_RTNeg_PRSNeg OR Tviol_RENNeg_PRSNeg OR Tviol_SENNeg_PRSNeg OR Tviol_WENNeg_PRSNeg OR Tviol_RENNeg_RCLK OR Tviol_RTNeg_RCLK OR Rviol_RENNeg_MRSNeg OR Rviol_WENNeg_MRSNeg OR Rviol_FWFT_MRSNeg OR Rviol_LDNeg_MRSNeg OR Rviol_RENNeg_PRSNeg OR Rviol_WENNeg_PRSNeg OR Pviol_MRSNeg OR Pviol_PRSNeg OR Pviol_RCLK OR Pviol_WCLK; END IF; ---------------------------------------------------------------------------- -- Functionality Section ---------------------------------------------------------------------------- IF falling_edge(MRSNegIn) THEN mreset<= false, true AFTER 15 ns; fwftcnt := 0; PAENeg_zd := '0'; PAFNeg_zd := '1'; HFNeg_zd := '1'; IF FWFTIn = '1' THEN fwft := true; EFNeg_zd := '1'; FFNeg_zd := '0'; rdptr := 0; wrptr := 0; count := 0; ELSE fwft := false; --idt standard mode EFNeg_zd := '0'; FFNeg_zd := '1'; rdptr := 1; wrptr := 1; count := 0; END IF; delayed_ff:= false; delayed_ef:= false; FFNeg_dly := FFNeg_zd; EFNeg_dly := EFNeg_zd; IF BENegIn = '0' THEN be := true; ELSIF BENegIn = '1' THEN be := false; ELSE ASSERT FALSE REPORT "BENeg has unusable value" SEVERITY error; END IF; IF BMIn = '0' THEN bm := false; ELSIF BMIn = '1' THEN bm := true; ELSE ASSERT FALSE REPORT "BM has unusable value" SEVERITY error; END IF; IF IWIn = '0' THEN iw := false; ELSIF IWIn = '1' THEN iw := true; ELSE ASSERT FALSE REPORT "IW has unusable value" SEVERITY error; END IF; IF OWIn = '0' THEN ow := false; ELSIF OWIn = '1' THEN ow := true; ELSE ASSERT FALSE REPORT "OW has unusable value" SEVERITY error; END IF; --bus matching byte order bm_Incnt :=0; bm_Outcnt:=0; fl_Outcnt:=0; IF IPIn = '0' THEN ip := false; ELSIF IPIn = '1' THEN ip := true; ELSE ASSERT FALSE REPORT "IP has unusable value" SEVERITY error; END IF; IF PFMIn = '0' THEN spfm := false; -- async programmable flag mode ELSIF PFMIn = '1' THEN spfm := true; -- sync programmable flag mode ELSE ASSERT FALSE REPORT "PFM has unusable value" SEVERITY error; END IF; IF RMIn = '0' THEN nlrtm := false; ELSIF RMIn = '1' THEN nlrtm := true; ELSE ASSERT FALSE REPORT "RM has unusable value" SEVERITY error; END IF; IF LDNegIn = '0' THEN programming := parallel; fp_Incnt := 0; ELSE programming := serial; fs_Incnt := 0; END IF; opireg := (LDNegIn, FSEL1In, FSEL0In); opi := To_Nat(opireg); paeoff := offsetps(opi); pafoff := TotalLoc - offsetps(opi); Qreg := (others => '0'); mrs_done := true; ELSIF falling_edge(PRSNegIn) AND NOT MRSNegIn = '0' THEN fwftcnt := 0; PAENeg_zd := '0'; PAFNeg_zd := '1'; HFNeg_zd := '1'; IF fwft THEN EFNeg_zd := '1'; FFNeg_zd := '0'; rdptr := 0; wrptr := 0; count := 0; ELSE EFNeg_zd := '0'; FFNeg_zd := '1'; rdptr := 1; wrptr := 1; count := 0; END IF; delayed_ff:= false; delayed_ef:= false; FFNeg_dly := FFNeg_zd; EFNeg_dly := EFNeg_zd; Qreg := (others => '0'); --bus matching byte order bm_Incnt :=0; bm_Outcnt:=0; fl_Outcnt:=0; END IF; -- write side IF rising_edge(WCLKIn) AND mreset THEN tWCLKposedge := NOW; IF (tWCLKposedge - tRCLKposedge) > tSKEW1 THEN minskew1RW := true; ELSE minskew1RW := false; END IF; IF (tWCLKposedge - tRCLKposedge) > tSKEW2 THEN minskew2WR := true; ELSE minskew2WR := false; END IF; IF LDNegIn = '1' THEN -- write to memory IF delayed_ff THEN FFNeg_zd := FFNeg_dly; delayed_ff := false; END IF; IF WENNegIn = '0' THEN IF (FFNeg_zd = '1' AND not fwft) OR -- NOT full and idt Standard mode (FFNeg_zd = '0' AND fwft) OR (bm_Incnt>0) THEN -- input sequence has begun IF bm = false OR iw = false THEN -- port width = 36 IF (count>=0 ) THEN --(count=0 AND NOT fwft) memA(wrptr) := to_nat(DIn(35 downto 27)); memB(wrptr) := to_nat(DIn(26 downto 18)); memC(wrptr) := to_nat(DIn(17 downto 9)); memD(wrptr) := to_nat(DIn(8 downto 0)); END IF; IF (count=0 AND fwft) THEN -- first word fall through in fwft mode outreg := DIn; --? END IF; ELSIF iw THEN --bus matching IF NOT ow THEN -- x18 WRITE , x36 READ IF bm_Incnt=0 THEN IF (count>=0 ) THEN memA(wrptr) := to_nat(DIn(17 downto 9)); memB(wrptr) := to_nat(DIn(8 downto 0)); ELSIF (count=0 AND fwft) THEN -- first word fall through in fwft mode IF be THEN -- Big Endian outtmp(35 downto 18) := DIn(17 downto 0); ELSE outtmp(17 downto 0) := DIn(17 downto 0); END IF; END IF; ELSIF bm_Incnt=1 THEN IF (count>=0 ) THEN memC(wrptr) := to_nat(DIn(17 downto 9)); memD(wrptr) := to_nat(DIn(8 downto 0)); ELSIF (count=0 AND fwft) THEN -- first word fall through in fwft mode IF be THEN -- Big Endian outtmp(17 downto 0) := DIn(17 downto 0); ELSE outtmp(35 downto 18) := DIn(17 downto 0); END IF; outreg:=outtmp; END IF; END IF; ELSIF ow THEN --x9 WRITE, x36 READ IF bm_Incnt=0 THEN IF (count>=0 ) THEN memA(wrptr) := to_nat(DIn(8 downto 0)); ELSIF (count=0 AND fwft) THEN -- first word fall through in fwft mode IF be THEN -- Big Endian outtmp(35 downto 27) := DIn(8 downto 0); ELSE outtmp(8 downto 0) := DIn(8 downto 0); END IF; END IF; ELSIF bm_Incnt=1 THEN IF (count>=0 ) THEN memB(wrptr) := to_nat(DIn(8 downto 0)); ELSIF (count=0 AND fwft) THEN -- first word fall through in fwft mode IF be THEN -- Big Endian outtmp(26 downto 18) := DIn(8 downto 0); ELSE outtmp(17 downto 9) := DIn(8 downto 0); END IF; END IF; ELSIF bm_Incnt=2 THEN IF (count>=0 ) THEN memC(wrptr) := to_nat(DIn(8 downto 0)); ELSIF (count=0 AND fwft) THEN -- first word fall through in fwft mode IF be THEN -- Big Endian outtmp(17 downto 9) := DIn(8 downto 0); ELSE outtmp(26 downto 18) := DIn(8 downto 0); END IF; END IF; ELSIF bm_Incnt=3 THEN IF (count>=0 ) THEN memD(wrptr) := to_nat(DIn(8 downto 0)); ELSIF (count=0 AND fwft) THEN -- first word fall through in fwft mode IF be THEN -- Big Endian outtmp(8 downto 0) := DIn(8 downto 0); ELSE outtmp(35 downto 27) := DIn(8 downto 0); END IF; outreg:=outtmp; END IF; END IF; END IF; ------ IF (ow AND bm_Incnt=3) OR (NOT ow AND bm_Incnt=1) THEN bm_Incnt:=0; ELSE bm_Incnt:=bm_Incnt+1; END IF; END IF; ELSE --RAM FULL END IF; --- flag ctrl IF fwft AND FFNeg_zd = '0' AND bm_Incnt=0 THEN-- input ready IF wrptr < TotalLoc + 1 THEN wrptr := wrptr + 1; ELSE wrptr := 0; END IF; IF wrptr >= rdptr THEN count := wrptr - rdptr; ELSE count := wrptr + TotalLoc + 2 - rdptr; END IF; IF count > HalfLoc + 1 THEN HFNeg_zd := '0'; END IF; IF count = TotalLoc + 1 THEN IF minskew1RW THEN FFNeg_zd := '1'; ELSE delayed_ff := true; FFNeg_dly := '1'; END IF; END IF; IF pafoff < count + 1 THEN PAFNeg_zd := '0'; ELSIF (spfm AND (pafoff >=count + 1))THEN PAFNeg_zd := '1'; END IF; --PFM low IF (not spfm AND (count > paeoff + 1)) THEN PAENeg_zd := '1'; END IF; ELSIF not fwft AND FFNeg_zd = '1' AND bm_Incnt=0 THEN--not full IF wrptr < TotalLoc THEN wrptr := wrptr + 1; ELSE wrptr := 0; END IF; IF wrptr >= rdptr THEN count := wrptr - rdptr; ELSE count := wrptr + TotalLoc - rdptr; END IF; IF count >= HalfLoc THEN HFNeg_zd := '0'; END IF; IF count = TotalLoc THEN FFNeg_zd := '0'; END IF; IF pafoff < count THEN PAFNeg_zd := '0'; ELSIF (spfm AND (pafoff >=count))THEN PAFNeg_zd := '1'; END IF; --PFM low IF (not spfm AND (count >= paeoff)) THEN PAENeg_zd := '1'; END IF; END IF; ELSE --WE# NOT asserted END IF; IF fwft THEN IF count < TotalLoc + 1 THEN IF minskew1RW THEN FFNeg_zd := '0'; ELSE delayed_ff := true; FFNeg_dly := '0'; END IF; END IF; ELSE IF count < TotalLoc THEN IF minskew1RW THEN FFNeg_zd := '1'; ELSE delayed_ff := true; FFNeg_dly := '1'; END IF; END IF; END IF; ELSE -- access programable flag registers IF programming = parallel THEN IF (WENNegIn='0') AND (RENNeg='1') AND (SENNeg='1') THEN tmp_ser_in :=(OTHERS=>'0'); IF NOT (bm AND iw AND ow) THEN -- port width = 36 IF NOT ip THEN --Non-Interspersed Parity IF fp_Incnt=0 THEN paeoff:=to_nat(DIn(12 downto 0)); ASSERT paeoff'0'); END IF; IF fs_Incnt<13 THEN tmp_ser_in(fs_Incnt):= FWFTIn; fs_Incnt:=fs_Incnt+1; paeoff:= to_nat(tmp_ser_in(12 downto 0)); ELSE tmp_ser_in(fs_Incnt):= FWFTIn; fs_Incnt:=fs_Incnt+1; pafoff:= to_nat(tmp_ser_in(25 downto 13)); END IF; IF fs_Incnt>25 THEN fs_Incnt:=0; ASSERT pafoff tSKEW1 THEN minskew1RW := true; ELSE minskew1RW := false; END IF; IF (tRCLKposedge - tWCLKposedge) > tSKEW2 THEN minskew2WR := true; ELSE minskew2WR := false; END IF; --retransmit-- IF (RTNegIn='0' AND WENNegIn='1') THEN --retransmit setup IF (RENNegIn='0') THEN --zero latency zl_retransmit:= true; ELSE --standard timing sl_retransmit:= true; END IF; IF fwft THEN rdptr:=0; ELSE rdptr:=1; END IF; count :=1; ELSIF RTNegIn='1' THEN IF sl_retransmit THEN sl_retransmit:=false; IF fwft THEN EFNeg_zd:='0'; ELSE EFNeg_zd:='1'; END IF; END IF; IF zl_retransmit THEN zl_retransmit :=false; End IF; END IF; IF LDNegIn = '1' THEN -- read from memory IF delayed_ef THEN EFNeg_zd := EFNeg_dly; delayed_ef := false; END IF; IF (NOT sl_retransmit) AND (RENNegIn='0') AND (count > 0) THEN IF (EFNeg_zd = '0' AND fwft) OR (EFNeg_zd = '1' AND not fwft) OR (bm_Outcnt>0) THEN -- output sequence has begun IF (NOT bm) OR (iw) THEN -- port width = 36 Qreg(35 downto 27) := to_slv(memA(rdptr),9); Qreg(26 downto 18) := to_slv(memB(rdptr),9); Qreg(17 downto 9) := to_slv(memC(rdptr),9); Qreg(8 downto 0) := to_slv(memD(rdptr),9); ELSIF NOT iw THEN --bus matching ------------------******* Qreg:=(OTHERS=>'0'); IF ow = false THEN -- x18 READ IF (bm_Outcnt =0 AND be) OR (bm_Outcnt =1 AND NOT be)THEN Qreg(17 downto 9):= to_slv(memA(rdptr),9); Qreg(8 downto 0) := to_slv(memB(rdptr),9); ELSIF (bm_Outcnt =1 AND be) OR (bm_Outcnt =0 AND NOT be)THEN Qreg(17 downto 9):= to_slv(memC(rdptr),9); Qreg(8 downto 0) := to_slv(memD(rdptr),9); END IF; ELSIF ow = true THEN --x9 READ IF bm_Outcnt =0 THEN IF be THEN -- Big Endian Qreg(8 downto 0) := to_slv(memA(rdptr),9); ELSE Qreg(8 downto 0) := to_slv(memD(rdptr),9); END IF; ELSIF bm_Outcnt =1 THEN IF be THEN -- Big Endian Qreg(8 downto 0):=to_slv(memB(rdptr),9); ELSE Qreg(8 downto 0):=to_slv(memC(rdptr),9); END IF; ELSIF bm_Outcnt =2 THEN IF be THEN -- Big Endian Qreg(8 downto 0):=to_slv(memC(rdptr),9); ELSE Qreg(8 downto 0):=to_slv(memB(rdptr),9); END IF; ELSIF bm_Outcnt =3 THEN IF be THEN -- Big Endian Qreg(8 downto 0) :=to_slv(memD(rdptr),9); ELSE Qreg(8 downto 0):=to_slv(memA(rdptr),9); END IF; END IF; END IF; ------ IF (ow AND bm_Outcnt =3) OR (NOT ow AND bm_Outcnt =1) THEN bm_Outcnt :=0; ELSE bm_Outcnt := bm_Outcnt +1; END IF; -----------------******* END IF; END IF; IF fwft AND EFNeg_zd = '0' AND bm_Outcnt =0 THEN --output ready IF rdptr < TotalLOC + 1 THEN rdptr := rdptr + 1; ELSE rdptr := 0; END IF; IF wrptr >= rdptr THEN count := wrptr - rdptr; ELSE count := wrptr + TotalLoc + 2 - rdptr; END IF; IF count <= HalfLoc + 1 THEN HFNeg_zd := '1'; END IF; ----------------------------- IF count <= paeoff + 1 THEN PAENeg_zd := '0'; END IF; IF spfm THEN -- synchronous prog flag mode IF count >= paeoff THEN PAENeg_zd := '1'; END IF; ELSE IF count < pafoff + 1 THEN PAFNeg_zd := '1'; END IF; END IF; ------------------------------------------------- IF count = 0 THEN EFNeg_zd := '1'; --? ELSE END IF; IF rdptr = 0 AND count = 1 THEN IF fwftcnt < 2 THEN fwftcnt := fwftcnt + 1; ELSE Qreg := outreg; EFNeg_zd := '0'; fwftcnt := 0; rdptr := 1; END IF; END IF; ELSIF not fwft AND EFNeg_zd = '1' AND bm_Outcnt =0 THEN IF rdptr < TotalLOC THEN rdptr := rdptr + 1; ELSE rdptr := 0; END IF; IF wrptr >= rdptr THEN count := wrptr - rdptr; ELSE count := wrptr + TotalLoc - rdptr; END IF; IF count <= HalfLoc THEN HFNeg_zd := '1'; END IF; ----------------------------------------------------------- IF count <= paeoff THEN PAENeg_zd := '0'; END IF; IF spfm THEN -- synchronous prog flag mode IF count > paeoff THEN PAENeg_zd := '1'; END IF; ELSE IF count < pafoff THEN PAFNeg_zd := '1'; END IF; END IF; ---------------------------------------------------------------- IF count = 0 AND minskew1RW THEN EFNeg_zd := '0'; ELSE EFNeg_zd := '1'; END IF; END IF; END IF; IF NOT sl_retransmit THEN IF fwft THEN IF rdptr = 0 AND count = 1 THEN IF fwftcnt < 2 THEN fwftcnt := fwftcnt + 1; ELSE Qreg := outreg; EFNeg_zd := '0'; fwftcnt := 0; rdptr := 1; END IF; END IF; ELSE IF count = 0 THEN IF minskew1RW THEN EFNeg_zd := '0'; ELSE delayed_ef := true; EFNeg_dly := '0'; END IF; ELSE IF minskew1RW THEN EFNeg_zd := '1'; ELSE delayed_ef := true; EFNeg_dly := '1'; END IF; END IF; END IF; ELSE delayed_ef:=false; IF fwft THEN EFNeg_zd:='1'; ELSE EFNeg_zd:='0'; END IF; END IF; ELSE -- access programable flag registers IF (RENNegIn='0') THEN Qreg:=(OTHERS=>'0'); IF (NOT bm) OR (bm AND iw) THEN -- port width = 36 IF NOT ip THEN --Non-Interspersed Parity IF fl_Outcnt=0 THEN Qreg(16 downto 0):= to_slv(paeoff,17); ELSIF fl_Outcnt=1 THEN Qreg(16 downto 0):= to_slv(pafoff,17); END IF; ELSIF ip THEN --Interspersed Parity IF fl_Outcnt=0 THEN tmp_reg:= to_slv(paeoff,17); Qreg(7 downto 0):= tmp_reg(7 downto 0); Qreg(16 downto 9):= tmp_reg(15 downto 8); Qreg(18):=tmp_reg(16); ELSIF fl_Outcnt=1 THEN tmp_reg:= to_slv(pafoff,17); Qreg(7 downto 0):= tmp_reg(7 downto 0); Qreg(16 downto 9):= tmp_reg(15 downto 8); Qreg(18):=tmp_reg(16); END IF; END IF; ELSIF bm AND NOT iw THEN --bus matching ------------------******* IF ow = false THEN -- x18 READ IF NOT ip THEN --Non-Interspersed Parity IF fl_Outcnt=0 THEN Qreg(16 downto 0):= to_slv(paeoff,17); ELSIF fl_Outcnt=1 THEN Qreg(16 downto 0):= to_slv(pafoff,17); END IF; ELSIF ip THEN --Interspersed Parity IF fl_Outcnt=0 THEN tmp_reg:= to_slv(paeoff,17); Qreg(7 downto 0):= tmp_reg(7 downto 0); Qreg(16 downto 9):= tmp_reg(15 downto 8); ELSIF fl_Outcnt=1 THEN tmp_reg:= to_slv(pafoff,17); Qreg(7 downto 0):= tmp_reg(7 downto 0); Qreg(16 downto 9):= tmp_reg(15 downto 8); END IF; END IF; ELSIF ow = true THEN --x9 READ IF fl_Outcnt =0 THEN tmp_reg:= to_slv(paeoff,17); Qreg(7 downto 0) :=tmp_reg(7 downto 0); ELSIF fl_Outcnt =1 THEN Qreg(7 downto 0):=tmp_reg(15 downto 8); ELSIF fl_Outcnt =2 THEN tmp_reg:= to_slv(pafoff,17); Qreg(7 downto 0):=tmp_reg(7 downto 0); ELSIF fl_Outcnt =3 THEN Qreg(7 downto 0):=tmp_reg(15 downto 8); END IF; END IF; ------ IF (ow AND fl_Outcnt =3) OR (NOT ow AND fl_Outcnt =1) THEN fl_Outcnt :=0; ELSE fl_Outcnt := fl_Outcnt +1; END IF; -----------------******* END IF; END IF; ----------**************************** END IF; END IF; IF mreset THEN IF OENegIn = '0' THEN Q_zd <= Qreg; ELSIF OENegIn = '1' THEN Q_zd <= (others => 'Z'); ELSE Q_zd <= (others => 'X'); ASSERT FALSE REPORT "OENegIn has unusable value" SEVERITY error; END IF; END IF; ---------------------------------------------------------------------------- -- Path Delay Section ---------------------------------------------------------------------------- VitalPathDelay01 ( OutSignal => EFNegOut, OutSignalName => "EFNeg", OutTemp => EFNeg_zd, GlitchData => EFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_RCLK_EFNeg, PathCondition => true) ) ); VitalPathDelay01 ( OutSignal => FFNegOut, OutSignalName => "FFNeg", OutTemp => FFNeg_zd, GlitchData => FFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => WCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_FFNeg, PathCondition => true) ) ); VitalPathDelay01 ( OutSignal => HFNegOut, OutSignalName => "HFNeg", OutTemp => HFNeg_zd, GlitchData => HFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => WCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_HFNeg, PathCondition => true), 3 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_HFNeg, PathCondition => true) ) ); VitalPathDelay01 ( OutSignal => PAENegOut, OutSignalName => "PAENeg", OutTemp => PAENeg_zd, GlitchData => PAENeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_RCLK_PAENeg, PathCondition => spfm), 3 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_PAENeg, PathCondition => (not spfm)), 4 => (InputChangeTime => WCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_PAENeg, PathCondition => (not spfm)) ) ); VitalPathDelay01 ( OutSignal => PAFNegOut, OutSignalName => "PAFNeg", OutTemp => PAFNeg_zd, GlitchData => PAFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => WCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_PAFNeg, PathCondition => spfm), 3 => (InputChangeTime => WCLKIn'LAST_EVENT, PathDelay => tpd_RCLK_PAFNeg, PathCondition => (not spfm)), 4 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_RCLK_PAFNeg, PathCondition => ( not spfm)) ) ); END PROCESS Fifo; ------------------------------------------------------------------------ -- Path Delay Processes generated as a function of data width ------------------------------------------------------------------------ DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE DataOut_Delay : PROCESS (Q_zd(i)) VARIABLE Q_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => QOut(i), OutSignalName => "Q", OutTemp => Q_zd(i), Mode => OnEvent, GlitchData => Q_GlitchData(i), Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_MRSNeg_EFNeg), PathCondition => TRUE), 1 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_RCLK_Q0), PathCondition => TRUE), 2 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_MRSNeg_EFNeg), PathCondition => TRUE), 3 => (InputChangeTime => OENegIn'LAST_EVENT, PathDelay => tpd_OENeg_Q0, PathCondition => TRUE) ) ); END PROCESS DataOut_Delay; END GENERATE; END BLOCK; END vhdl_behavioral;