-------------------------------------------------------------------------------- -- File Name: idt72t4098.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com/ -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- 1.0 D.Vukicevic 05 Dec 12 initial version -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FLASH MEMORY -- Technology: CMOS -- Part: IDT72T4098 -- -- Description: 32,768 x 40 High-speed TeraSync DDR/SDR FIFO -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY idt72t4098 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_D18 : VitalDelayType01 := VitalZeroDelay01; tipd_D19 : VitalDelayType01 := VitalZeroDelay01; tipd_D20 : VitalDelayType01 := VitalZeroDelay01; tipd_D21 : VitalDelayType01 := VitalZeroDelay01; tipd_D22 : VitalDelayType01 := VitalZeroDelay01; tipd_D23 : VitalDelayType01 := VitalZeroDelay01; tipd_D24 : VitalDelayType01 := VitalZeroDelay01; tipd_D25 : VitalDelayType01 := VitalZeroDelay01; tipd_D26 : VitalDelayType01 := VitalZeroDelay01; tipd_D27 : VitalDelayType01 := VitalZeroDelay01; tipd_D28 : VitalDelayType01 := VitalZeroDelay01; tipd_D29 : VitalDelayType01 := VitalZeroDelay01; tipd_D30 : VitalDelayType01 := VitalZeroDelay01; tipd_D31 : VitalDelayType01 := VitalZeroDelay01; tipd_D32 : VitalDelayType01 := VitalZeroDelay01; tipd_D33 : VitalDelayType01 := VitalZeroDelay01; tipd_D34 : VitalDelayType01 := VitalZeroDelay01; tipd_D35 : VitalDelayType01 := VitalZeroDelay01; tipd_D36 : VitalDelayType01 := VitalZeroDelay01; tipd_D37 : VitalDelayType01 := VitalZeroDelay01; tipd_D38 : VitalDelayType01 := VitalZeroDelay01; tipd_D39 : VitalDelayType01 := VitalZeroDelay01; tipd_BM : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL1 : VitalDelayType01 := VitalZeroDelay01; tipd_FWFT : VitalDelayType01 := VitalZeroDelay01; tipd_HSTL : VitalDelayType01 := VitalZeroDelay01; tipd_IW : VitalDelayType01 := VitalZeroDelay01; tipd_MARK : VitalDelayType01 := VitalZeroDelay01; tipd_MRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OW : VitalDelayType01 := VitalZeroDelay01; tipd_PRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK : VitalDelayType01 := VitalZeroDelay01; tipd_RCSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RSDRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SCLK : VitalDelayType01 := VitalZeroDelay01; tipd_SENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SRENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SI : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK : VitalDelayType01 := VitalZeroDelay01; tipd_WCSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WSDRNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays -- tA, tASO, tRCSLZ, tRCSHZ tpd_RCLK_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tOLZ, tOHZ, tOE tpd_OENeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tRSF tpd_MRSNeg_EFNeg : VitalDelayType01 := UnitDelay01; -- tWFF tpd_WCLK_FFNeg : VitalDelayType01 := UnitDelay01; -- tREF tpd_RCLK_EFNeg : VitalDelayType01 := UnitDelay01; -- tPAFS tpd_WCLK_PAFNeg : VitalDelayType01 := UnitDelay01; -- tPAES tpd_RCLK_PAENeg : VitalDelayType01 := UnitDelay01; -- tERCLK tpd_RCLK_ERCLK : VitalDelayType01 := UnitDelay01; -- tCLKEN tpd_RCLK_ERENNeg : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths -- tRS tpw_MRSNeg_negedge : VitalDelayType := UnitDelay; -- tCLKL1 tpw_RCLK_SDR_negedge : VitalDelayType := UnitDelay; -- tCLKH1 tpw_RCLK_SDR_posedge : VitalDelayType := UnitDelay; -- tCLKL2 tpw_RCLK_DDR_negedge : VitalDelayType := UnitDelay; -- tCLKH2 tpw_RCLK_DDR_posedge : VitalDelayType := UnitDelay; -- tSCKL tpw_SCLK_negedge : VitalDelayType := UnitDelay; -- tSCKH tpw_SCLK_posedge : VitalDelayType := UnitDelay; -- minimum clock period - 1/max freq -- tCLK1 tperiod_RCLK_SDR_posedge : VitalDelayType := UnitDelay; -- tCLK2 tperiod_RCLK_DDR_posedge : VitalDelayType := UnitDelay; -- tSCLK tperiod_SCLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS tsetup_D0_WCLK : VitalDelayType := UnitDelay; -- tENS tsetup_RENNeg_RCLK : VitalDelayType := UnitDelay; -- tWCSS tsetup_WCSNeg_WCLK : VitalDelayType := UnitDelay; -- tSDS tsetup_SI_SCLK : VitalDelayType := UnitDelay; -- tSENS tsetup_SENNeg_SCLK : VitalDelayType := UnitDelay; -- tRSS tsetup_RENNeg_MRSNeg : VitalDelayType := UnitDelay; -- tHRSS tsetup_HSTL_MRSNeg : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH thold_D0_WCLK : VitalDelayType := UnitDelay; -- tENH thold_RENNeg_RCLK : VitalDelayType := UnitDelay; -- tWCSH thold_WCSNeg_WCLK : VitalDelayType := UnitDelay; -- tSDH thold_SI_SCLK : VitalDelayType := UnitDelay; -- tSENH thold_SENNeg_SCLK : VitalDelayType := UnitDelay; -- trecovery values: release times -- tRSR trecovery_RENNeg_MRSNeg : VitalDelayType := UnitDelay; -- tSKEW1 (skew time /RCLK/WCLK(for EF/FF) tdevice_SKEW1 : VitalDelayType := UnitDelay; -- tSKEW2 (skew time /RCLK/WCLK(for EF/FF - DDR mode)) tdevice_SKEW2 : VitalDelayType := UnitDelay; -- tSKEW2 (skew time /RCLK/WCLK(for PAE/PAF) tdevice_SKEW3 : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN std_ulogic := 'U'; D1 : IN std_ulogic := 'U'; D2 : IN std_ulogic := 'U'; D3 : IN std_ulogic := 'U'; D4 : IN std_ulogic := 'U'; D5 : IN std_ulogic := 'U'; D6 : IN std_ulogic := 'U'; D7 : IN std_ulogic := 'U'; D8 : IN std_ulogic := 'U'; D9 : IN std_ulogic := 'U'; D10 : IN std_ulogic := 'U'; D11 : IN std_ulogic := 'U'; D12 : IN std_ulogic := 'U'; D13 : IN std_ulogic := 'U'; D14 : IN std_ulogic := 'U'; D15 : IN std_ulogic := 'U'; D16 : IN std_ulogic := 'U'; D17 : IN std_ulogic := 'U'; D18 : IN std_ulogic := 'U'; D19 : IN std_ulogic := 'U'; D20 : IN std_ulogic := 'U'; D21 : IN std_ulogic := 'U'; D22 : IN std_ulogic := 'U'; D23 : IN std_ulogic := 'U'; D24 : IN std_ulogic := 'U'; D25 : IN std_ulogic := 'U'; D26 : IN std_ulogic := 'U'; D27 : IN std_ulogic := 'U'; D28 : IN std_ulogic := 'U'; D29 : IN std_ulogic := 'U'; D30 : IN std_ulogic := 'U'; D31 : IN std_ulogic := 'U'; D32 : IN std_ulogic := 'U'; D33 : IN std_ulogic := 'U'; D34 : IN std_ulogic := 'U'; D35 : IN std_ulogic := 'U'; D36 : IN std_ulogic := 'U'; D37 : IN std_ulogic := 'U'; D38 : IN std_ulogic := 'U'; D39 : IN std_ulogic := 'U'; Q0 : OUT std_ulogic := 'U'; Q1 : OUT std_ulogic := 'U'; Q2 : OUT std_ulogic := 'U'; Q3 : OUT std_ulogic := 'U'; Q4 : OUT std_ulogic := 'U'; Q5 : OUT std_ulogic := 'U'; Q6 : OUT std_ulogic := 'U'; Q7 : OUT std_ulogic := 'U'; Q8 : OUT std_ulogic := 'U'; Q9 : OUT std_ulogic := 'U'; Q10 : OUT std_ulogic := 'U'; Q11 : OUT std_ulogic := 'U'; Q12 : OUT std_ulogic := 'U'; Q13 : OUT std_ulogic := 'U'; Q14 : OUT std_ulogic := 'U'; Q15 : OUT std_ulogic := 'U'; Q16 : OUT std_ulogic := 'U'; Q17 : OUT std_ulogic := 'U'; Q18 : OUT std_ulogic := 'U'; Q19 : OUT std_ulogic := 'U'; Q20 : OUT std_ulogic := 'U'; Q21 : OUT std_ulogic := 'U'; Q22 : OUT std_ulogic := 'U'; Q23 : OUT std_ulogic := 'U'; Q24 : OUT std_ulogic := 'U'; Q25 : OUT std_ulogic := 'U'; Q26 : OUT std_ulogic := 'U'; Q27 : OUT std_ulogic := 'U'; Q28 : OUT std_ulogic := 'U'; Q29 : OUT std_ulogic := 'U'; Q30 : OUT std_ulogic := 'U'; Q31 : OUT std_ulogic := 'U'; Q32 : OUT std_ulogic := 'U'; Q33 : OUT std_ulogic := 'U'; Q34 : OUT std_ulogic := 'U'; Q35 : OUT std_ulogic := 'U'; Q36 : OUT std_ulogic := 'U'; Q37 : OUT std_ulogic := 'U'; Q38 : OUT std_ulogic := 'U'; Q39 : OUT std_ulogic := 'U'; BM : IN std_ulogic := 'U'; EFNeg : OUT std_ulogic := 'U'; ERCLK : OUT std_ulogic := 'U'; ERENNeg : OUT std_ulogic := 'U'; FFNeg : OUT std_ulogic := 'U'; FSEL0 : IN std_ulogic := 'U'; FSEL1 : IN std_ulogic := 'U'; FWFT : IN std_ulogic := 'U'; HSTL : IN std_ulogic := 'U'; IW : IN std_ulogic := 'U'; MARK : IN std_ulogic := 'U'; MRSNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; OW : IN std_ulogic := 'U'; PAENeg : OUT std_ulogic := 'U'; PAFNeg : OUT std_ulogic := 'U'; PRSNeg : IN std_ulogic := 'U'; RCLK : IN std_ulogic := 'U'; RCSNeg : IN std_ulogic := 'U'; RENNeg : IN std_ulogic := 'U'; RSDRNeg : IN std_ulogic := 'U'; RTNeg : IN std_ulogic := 'U'; SCLK : IN std_ulogic := 'U'; SENNeg : IN std_ulogic := 'U'; SRENNeg : IN std_ulogic := 'U'; SI : IN std_ulogic := 'U'; SO : OUT std_ulogic := 'U'; WCLK : IN std_ulogic := 'U'; WCSNeg : IN std_ulogic := 'U'; WENNeg : IN std_ulogic := 'U'; WSDRNeg : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of idt72t4098 : ENTITY IS TRUE; END idt72t4098; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of idt72t4098 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : String := "IDT72T4098"; CONSTANT TotalLoc : POSITIVE := 32768; CONSTANT MaxData : POSITIVE := 1023; CONSTANT HiDbit : NATURAL := 39; SIGNAL D0_ipd : std_ulogic := 'U'; SIGNAL D1_ipd : std_ulogic := 'U'; SIGNAL D2_ipd : std_ulogic := 'U'; SIGNAL D3_ipd : std_ulogic := 'U'; SIGNAL D4_ipd : std_ulogic := 'U'; SIGNAL D5_ipd : std_ulogic := 'U'; SIGNAL D6_ipd : std_ulogic := 'U'; SIGNAL D7_ipd : std_ulogic := 'U'; SIGNAL D8_ipd : std_ulogic := 'U'; SIGNAL D9_ipd : std_ulogic := 'U'; SIGNAL D10_ipd : std_ulogic := 'U'; SIGNAL D11_ipd : std_ulogic := 'U'; SIGNAL D12_ipd : std_ulogic := 'U'; SIGNAL D13_ipd : std_ulogic := 'U'; SIGNAL D14_ipd : std_ulogic := 'U'; SIGNAL D15_ipd : std_ulogic := 'U'; SIGNAL D16_ipd : std_ulogic := 'U'; SIGNAL D17_ipd : std_ulogic := 'U'; SIGNAL D18_ipd : std_ulogic := 'U'; SIGNAL D19_ipd : std_ulogic := 'U'; SIGNAL D20_ipd : std_ulogic := 'U'; SIGNAL D21_ipd : std_ulogic := 'U'; SIGNAL D22_ipd : std_ulogic := 'U'; SIGNAL D23_ipd : std_ulogic := 'U'; SIGNAL D24_ipd : std_ulogic := 'U'; SIGNAL D25_ipd : std_ulogic := 'U'; SIGNAL D26_ipd : std_ulogic := 'U'; SIGNAL D27_ipd : std_ulogic := 'U'; SIGNAL D28_ipd : std_ulogic := 'U'; SIGNAL D29_ipd : std_ulogic := 'U'; SIGNAL D30_ipd : std_ulogic := 'U'; SIGNAL D31_ipd : std_ulogic := 'U'; SIGNAL D32_ipd : std_ulogic := 'U'; SIGNAL D33_ipd : std_ulogic := 'U'; SIGNAL D34_ipd : std_ulogic := 'U'; SIGNAL D35_ipd : std_ulogic := 'U'; SIGNAL D36_ipd : std_ulogic := 'U'; SIGNAL D37_ipd : std_ulogic := 'U'; SIGNAL D38_ipd : std_ulogic := 'U'; SIGNAL D39_ipd : std_ulogic := 'U'; SIGNAL BM_ipd : std_ulogic := 'U'; SIGNAL FSEL0_ipd : std_ulogic := 'U'; SIGNAL FSEL1_ipd : std_ulogic := 'U'; SIGNAL FWFT_ipd : std_ulogic := 'U'; SIGNAL HSTL_ipd : std_ulogic := 'U'; SIGNAL IW_ipd : std_ulogic := 'U'; SIGNAL MARK_ipd : std_ulogic := 'U'; SIGNAL MRSNeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL OW_ipd : std_ulogic := 'U'; SIGNAL PRSNeg_ipd : std_ulogic := 'U'; SIGNAL RCLK_ipd : std_ulogic := 'U'; SIGNAL RCSNeg_ipd : std_ulogic := 'U'; SIGNAL RENNeg_ipd : std_ulogic := 'U'; SIGNAL RSDRNeg_ipd : std_ulogic := 'U'; SIGNAL RTNeg_ipd : std_ulogic := 'U'; SIGNAL SCLK_ipd : std_ulogic := 'U'; SIGNAL SENNeg_ipd : std_ulogic := 'U'; SIGNAL SRENNeg_ipd : std_ulogic := 'U'; SIGNAL SI_ipd : std_ulogic := 'U'; SIGNAL WCLK_ipd : std_ulogic := 'U'; SIGNAL WCSNeg_ipd : std_ulogic := 'U'; SIGNAL WENNeg_ipd : std_ulogic := 'U'; SIGNAL WSDRNeg_ipd : std_ulogic := 'U'; -- SKEW stuff ALIAS tSKEW1 : VitalDelayType IS tdevice_SKEW1; ALIAS tSKEW2 : VitalDelayType IS tdevice_SKEW2; ALIAS tSKEW3 : VitalDelayType IS tdevice_SKEW3; SIGNAL OpenIn, OpenOut : std_logic; SHARED VARIABLE FROMOE : BOOLEAN := false; SHARED VARIABLE FROMRCLK : BOOLEAN := false; BEGIN -------------------------------------------------------------------------------- -- Dummy instances for exporting tSKEW vals from SDF file -- using DEVICE construct -------------------------------------------------------------------------------- SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1)); SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2)); SKEW3: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW3, tdevice_SKEW3)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0); w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1); w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2); w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3); w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4); w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5); w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6); w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7); w_9 : VitalWireDelay (D8_ipd, D8, tipd_D8); w_10 : VitalWireDelay (D9_ipd, D9, tipd_D9); w_11 : VitalWireDelay (D10_ipd, D10, tipd_D10); w_12 : VitalWireDelay (D11_ipd, D11, tipd_D11); w_13 : VitalWireDelay (D12_ipd, D12, tipd_D12); w_14 : VitalWireDelay (D13_ipd, D13, tipd_D13); w_15 : VitalWireDelay (D14_ipd, D14, tipd_D14); w_16 : VitalWireDelay (D15_ipd, D15, tipd_D15); w_17 : VitalWireDelay (D16_ipd, D16, tipd_D16); w_18 : VitalWireDelay (D17_ipd, D17, tipd_D17); w_19 : VitalWireDelay (D18_ipd, D18, tipd_D18); w_20 : VitalWireDelay (D19_ipd, D19, tipd_D19); w_21 : VitalWireDelay (D20_ipd, D20, tipd_D20); w_22 : VitalWireDelay (D21_ipd, D21, tipd_D21); w_23 : VitalWireDelay (D22_ipd, D22, tipd_D22); w_24 : VitalWireDelay (D23_ipd, D23, tipd_D23); w_25 : VitalWireDelay (D24_ipd, D24, tipd_D24); w_26 : VitalWireDelay (D25_ipd, D25, tipd_D25); w_27 : VitalWireDelay (D26_ipd, D26, tipd_D26); w_28 : VitalWireDelay (D27_ipd, D27, tipd_D27); w_29 : VitalWireDelay (D28_ipd, D28, tipd_D28); w_30 : VitalWireDelay (D29_ipd, D29, tipd_D29); w_31 : VitalWireDelay (D30_ipd, D30, tipd_D30); w_32 : VitalWireDelay (D31_ipd, D31, tipd_D31); w_33 : VitalWireDelay (D32_ipd, D32, tipd_D32); w_34 : VitalWireDelay (D33_ipd, D33, tipd_D33); w_35 : VitalWireDelay (D34_ipd, D34, tipd_D34); w_36 : VitalWireDelay (D35_ipd, D35, tipd_D35); w_37 : VitalWireDelay (D36_ipd, D36, tipd_D36); w_38 : VitalWireDelay (D37_ipd, D37, tipd_D37); w_39 : VitalWireDelay (D38_ipd, D38, tipd_D38); w_40 : VitalWireDelay (D39_ipd, D39, tipd_D39); w_81 : VitalWireDelay (BM_ipd, BM, tipd_BM); w_82 : VitalWireDelay (FSEL0_ipd, FSEL0, tipd_FSEL0); w_83 : VitalWireDelay (FSEL1_ipd, FSEL1, tipd_FSEL1); w_84 : VitalWireDelay (FWFT_ipd, FWFT, tipd_FWFT); w_85 : VitalWireDelay (HSTL_ipd, HSTL, tipd_HSTL); w_86 : VitalWireDelay (IW_ipd, IW, tipd_IW); w_87 : VitalWireDelay (MARK_ipd, MARK, tipd_MARK); w_88 : VitalWireDelay (MRSNeg_ipd, MRSNeg, tipd_MRSNeg); w_89 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_90 : VitalWireDelay (OW_ipd, OW, tipd_OW); w_91 : VitalWireDelay (PRSNeg_ipd, PRSNeg, tipd_PRSNeg); w_92 : VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK); w_93 : VitalWireDelay (RCSNeg_ipd, RCSNeg, tipd_RCSNeg); w_94 : VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg); w_95 : VitalWireDelay (RSDRNeg_ipd, RSDRNeg, tipd_RSDRNeg); w_96 : VitalWireDelay (RTNeg_ipd, RTNeg, tipd_RTNeg); w_97 : VitalWireDelay (SCLK_ipd, SCLK, tipd_SCLK); w_98 : VitalWireDelay (SENNeg_ipd, SENNeg, tipd_SENNeg); w_99 : VitalWireDelay (SRENNeg_ipd, SRENNeg, tipd_SRENNeg); w_100 : VitalWireDelay (SI_ipd, SI, tipd_SI); w_101 : VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK); w_102 : VitalWireDelay (WCSNeg_ipd, WCSNeg, tipd_WCSNeg); w_103 : VitalWireDelay (WENNeg_ipd, WENNeg, tipd_WENNeg); w_104 : VitalWireDelay (WSDRNeg_ipd, WSDRNeg, tipd_WSDRNeg); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( DIn : IN std_logic_vector(39 DOWNTO 0); BMIn : IN std_ulogic := 'U'; FSEL0In : IN std_ulogic := 'U'; FSEL1In : IN std_ulogic := 'U'; FWFTIn : IN std_ulogic := 'U'; HSTLIn : IN std_ulogic := 'U'; IWIn : IN std_ulogic := 'U'; MARKIn : IN std_ulogic := 'U'; MRSNegIn : IN std_ulogic := 'U'; OENegIn : IN std_ulogic := 'U'; OWIn : IN std_ulogic := 'U'; PRSNegIn : IN std_ulogic := 'U'; RCLKIn : IN std_ulogic := 'U'; RCSNegIn : IN std_ulogic := 'U'; RENNegIn : IN std_ulogic := 'U'; RSDRNegIn : IN std_ulogic := 'U'; RTNegIn : IN std_ulogic := 'U'; SCLKIn : IN std_ulogic := 'U'; SENNegIn : IN std_ulogic := 'U'; SRENNegIn : IN std_ulogic := 'U'; SIIn : IN std_ulogic := 'U'; WCLKIn : IN std_ulogic := 'U'; WCSNegIn : IN std_ulogic := 'U'; WENNegIn : IN std_ulogic := 'U'; WSDRNegIn : IN std_ulogic := 'U'; QOut : OUT std_logic_vector(39 downto 0); EFNegOut : OUT std_ulogic := 'U'; ERCLKOut : OUT std_ulogic := 'U'; ERENNegOut : OUT std_ulogic := 'U'; FFNegOut : OUT std_ulogic := 'U'; PAENegOut : OUT std_ulogic := 'U'; PAFNegOut : OUT std_ulogic := 'U'; SOOut : OUT std_ulogic := 'U' ); PORT MAP ( DIn(0) => D0_ipd, DIn(1) => D1_ipd, DIn(2) => D2_ipd, DIn(3) => D3_ipd, DIn(4) => D4_ipd, DIn(5) => D5_ipd, DIn(6) => D6_ipd, DIn(7) => D7_ipd, DIn(8) => D8_ipd, DIn(9) => D9_ipd, DIn(10) => D10_ipd, DIn(11) => D11_ipd, DIn(12) => D12_ipd, DIn(13) => D13_ipd, DIn(14) => D14_ipd, DIn(15) => D15_ipd, DIn(16) => D16_ipd, DIn(17) => D17_ipd, DIn(18) => D18_ipd, DIn(19) => D19_ipd, DIn(20) => D20_ipd, DIn(21) => D21_ipd, DIn(22) => D22_ipd, DIn(23) => D23_ipd, DIn(24) => D24_ipd, DIn(25) => D25_ipd, DIn(26) => D26_ipd, DIn(27) => D27_ipd, DIn(28) => D28_ipd, DIn(29) => D29_ipd, DIn(30) => D30_ipd, DIn(31) => D31_ipd, DIn(32) => D32_ipd, DIn(33) => D33_ipd, DIn(34) => D34_ipd, DIn(35) => D35_ipd, DIn(36) => D36_ipd, DIn(37) => D37_ipd, DIn(38) => D38_ipd, DIn(39) => D39_ipd, QOut(0) => Q0, QOut(1) => Q1, QOut(2) => Q2, QOut(3) => Q3, QOut(4) => Q4, QOut(5) => Q5, QOut(6) => Q6, QOut(7) => Q7, QOut(8) => Q8, QOut(9) => Q9, QOut(10) => Q10, QOut(11) => Q11, QOut(12) => Q12, QOut(13) => Q13, QOut(14) => Q14, QOut(15) => Q15, QOut(16) => Q16, QOut(17) => Q17, QOut(18) => Q18, QOut(19) => Q19, QOut(20) => Q20, QOut(21) => Q21, QOut(22) => Q22, QOut(23) => Q23, QOut(24) => Q24, QOut(25) => Q25, QOut(26) => Q26, QOut(27) => Q27, QOut(28) => Q28, QOut(29) => Q29, QOut(30) => Q30, QOut(31) => Q31, QOut(32) => Q32, QOut(33) => Q33, QOut(34) => Q34, QOut(35) => Q35, QOut(36) => Q36, QOut(37) => Q37, QOut(38) => Q38, QOut(39) => Q39, BMIn => To_UX01(BM_ipd), FSEL0In => To_UX01(FSEL0_ipd), FSEL1In => To_UX01(FSEL1_ipd), FWFTIn => To_UX01(FWFT_ipd), HSTLIn => To_UX01(HSTL_ipd), IWIn => To_UX01(IW_ipd), MARKIn => To_UX01(MARK_ipd), MRSNegIn => To_UX01(MRSNeg_ipd), OENegIn => To_UX01(OENeg_ipd), OWIn => To_UX01(OW_ipd), PRSNegIn => To_UX01(PRSNeg_ipd), RCLKIn => RCLK_ipd, RCSNegIn => To_UX01(RCSNeg_ipd), RENNegIn => To_UX01(RENNeg_ipd), RSDRNegIn => To_UX01(RSDRNeg_ipd), RTNegIn => To_UX01(RTNeg_ipd), SCLKIn => SCLK_ipd, SENNegIn => SENNeg_ipd, SRENNegIn => SRENNeg_ipd, SIIn => SI_ipd, WCLKIn => WCLK_ipd, WCSNegIn => To_UX01(WCSNeg_ipd), WENNegIn => To_UX01(WENNeg_ipd), WSDRNegIn => To_UX01(WSDRNeg_ipd), EFNegOut => EFNeg, ERCLKOut => ERCLK, ERENNegOut => ERENNeg, FFNegOut => FFNeg, PAENegOut => PAENeg, PAFNegOut => PAFNeg, SOOut => SO ); SIGNAL Q_zd : std_logic_vector(39 downto 0) := (others => 'Z'); SIGNAL mreset : boolean := false; SIGNAL time_flag_for_OE : std_logic := '0'; TYPE mode_type IS (SDR, DDR); TYPE match_type IS (DDR40, DDR20, DDR10, SDR40, SDR20, SDR10); TYPE offset_type IS ARRAY (0 TO 3) OF positive; TYPE last_done_type is (write, read, none); TYPE memory_model_type is (normal, mapped); BEGIN ------------------------------------------------------------------------ -- Behavior Process ------------------------------------------------------------------------ Fifo : PROCESS (DIn, BMIn, WCLKIn, MRSNegIn, PRSNegIn, FWFTIn, OWIn, FSEL0In, FSEL1In, WENNegIn, IWIn, RTNegIn, OENegIn, RENNegIn, SENNegIn, RCLKIn, HSTLIn, MARKIn, RCSNegIn, RSDRNegIn, SCLKIn, SRENNegIn, SIIn, WCSNegIn, WSDRNegIn) CONSTANT offsetps : offset_type := (7, 127, 63, 255); -- Timing Check Variables VARIABLE Tviol_D_WCLK : X01 := '0'; VARIABLE TD_D_WCLK : VitalTimingDataType; VARIABLE Tviol_D_WCLK_DDR : X01 := '0'; VARIABLE TD_D_WCLK_DDR : VitalTimingDataType; VARIABLE Tviol_RENNeg_RCLK : X01 := '0'; VARIABLE TD_RENNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_WCLK : X01 := '0'; VARIABLE TD_WENNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_RCSNeg_RCLK : X01 := '0'; VARIABLE TD_RCSNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_RTNeg_RCLK : X01 := '0'; VARIABLE TD_RTNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_MARK_RCLK : X01 := '0'; VARIABLE TD_MARK_RCLK : VitalTimingDataType; VARIABLE Tviol_WCSNeg_WCLK : X01 := '0'; VARIABLE TD_WCSNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_SI_SCLK : X01 := '0'; VARIABLE TD_SI_SCLK : VitalTimingDataType; VARIABLE Tviol_SENNeg_SCLK : X01 := '0'; VARIABLE TD_SENNeg_SCLK : VitalTimingDataType; VARIABLE Tviol_SRENNeg_SCLK : X01 := '0'; VARIABLE TD_SRENNeg_SCLK : VitalTimingDataType; VARIABLE Tviol_RENNeg_MRSNeg : X01 := '0'; VARIABLE TD_RENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_WENNeg_MRSNeg : X01 := '0'; VARIABLE TD_WENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_SENNeg_MRSNeg : X01 := '0'; VARIABLE TD_SENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_SRENNeg_MRSNeg : X01 := '0'; VARIABLE TD_SRENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FWFT_MRSNeg : X01 := '0'; VARIABLE TD_FWFT_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FSEL1_MRSNeg : X01 := '0'; VARIABLE TD_FSEL1_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FSEL0_MRSNeg : X01 := '0'; VARIABLE TD_FSEL0_MRSNeg : VitalTimingDataType; VARIABLE Tviol_BM_MRSNeg : X01 := '0'; VARIABLE TD_BM_MRSNeg : VitalTimingDataType; VARIABLE Tviol_OW_MRSNeg : X01 := '0'; VARIABLE TD_OW_MRSNeg : VitalTimingDataType; VARIABLE Tviol_IW_MRSNeg : X01 := '0'; VARIABLE TD_IW_MRSNeg : VitalTimingDataType; VARIABLE Tviol_WSDRNeg_MRSNeg : X01 := '0'; VARIABLE TD_WSDRNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RSDRNeg_MRSNeg : X01 := '0'; VARIABLE TD_RSDRNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RTNeg_MRSNeg : X01 := '0'; VARIABLE TD_RTNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_HSTL_MRSNeg : X01 := '0'; VARIABLE TD_HSTL_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_PRSNeg : X01 := '0'; VARIABLE TD_RENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_WENNeg_PRSNeg : X01 := '0'; VARIABLE TD_WENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_SENNeg_PRSNeg : X01 := '0'; VARIABLE TD_SENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_SRENNeg_PRSNeg : X01 := '0'; VARIABLE TD_SRENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_RTNeg_PRSNeg : X01 := '0'; VARIABLE TD_RTNeg_PRSNeg : VitalTimingDataType; VARIABLE Rviol_RENNeg_MRSNeg : X01 := '0'; VARIABLE RD_RENNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_WENNeg_MRSNeg : X01 := '0'; VARIABLE RD_WENNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_FWFT_MRSNeg : X01 := '0'; VARIABLE RD_FWFT_MRSNeg : VitalTimingDataType; VARIABLE Rviol_WSDRNeg_MRSNeg : X01 := '0'; VARIABLE RD_WSDRNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_RSDRNeg_MRSNeg : X01 := '0'; VARIABLE RD_RSDRNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_RENNeg_PRSNeg : X01 := '0'; VARIABLE RD_RENNeg_PRSNeg : VitalTimingDataType; VARIABLE Rviol_WENNeg_PRSNeg : X01 := '0'; VARIABLE RD_WENNeg_PRSNeg : VitalTimingDataType; VARIABLE Pviol_MRSNeg : X01 := '0'; VARIABLE PD_MRSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRSNeg : X01 := '0'; VARIABLE PD_PRSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RCLK1 : X01 := '0'; VARIABLE PD_RCLK1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RCLK2 : X01 := '0'; VARIABLE PD_RCLK2 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WCLK1 : X01 := '0'; VARIABLE PD_WCLK1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WCLK2 : X01 := '0'; VARIABLE PD_WCLK2 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_SCLK : X01 := '0'; VARIABLE PD_SCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE mode_wr : mode_type := SDR; VARIABLE mode_rd : mode_type := SDR; VARIABLE in_mode : match_type := SDR40; VARIABLE out_mode : match_type := SDR40; VARIABLE wrote_in : boolean := false; VARIABLE read_out : boolean := false; -- Memory array declaration TYPE MemStore IS ARRAY (0 to TotalLOC + 1) OF INTEGER RANGE -2 TO MaxData; -- uninitialized memory -2 -- unknown or corrupted memory -1 -- Functionality Results Variables VARIABLE Violation : X01 := '0'; VARIABLE EFNeg_zd : std_ulogic; VARIABLE FFNeg_zd : std_ulogic; VARIABLE PAFNeg_dly : std_ulogic; VARIABLE PAFNeg_zd : std_ulogic; VARIABLE PAENeg_dly : std_ulogic; VARIABLE PAENeg_zd : std_ulogic; VARIABLE ERCLK_zd : std_ulogic; VARIABLE ERENNeg_zd : std_ulogic; VARIABLE Qreg : std_logic_vector(39 downto 0) := (others => '0'); VARIABLE Qreg_tmp: std_logic_vector(39 downto 0):=(others => '0'); VARIABLE rtreg : std_logic_vector(39 downto 0) := (others => '0'); VARIABLE SO_zd : std_ulogic; VARIABLE fwft : boolean := false; VARIABLE bm : boolean := false; VARIABLE iw : boolean := false; VARIABLE ow : boolean := false; VARIABLE memA : MemStore; VARIABLE memB : MemStore; VARIABLE memC : MemStore; VARIABLE memD : MemStore; VARIABLE Data1 : Integer := 0; VARIABLE Data2 : Integer := 0; VARIABLE Data3 : Integer := 0; VARIABLE Data4 : Integer := 0; VARIABLE memory_model : memory_model_type := normal; VARIABLE rdptr : natural RANGE 0 TO TotalLOC + 1 := 0; --read pointer VARIABLE wrptr : natural RANGE 0 TO TotalLOC + 1 := 0;--write pointer VARIABLE rdptr_next : natural RANGE 0 TO TotalLOC + 1 := 0; --read pointer VARIABLE wrptr_next : natural RANGE 0 TO TotalLOC + 1 := 0;--write pointer VARIABLE rtrdptr : natural RANGE 0 TO TotalLOC + 1;--retransmit pt. VARIABLE paeoff : natural RANGE 0 TO TotalLOC; --pae offset VARIABLE pafoff : natural RANGE 0 TO TotalLOC; --paf offset VARIABLE opi : natural RANGE 0 TO 7; --offset preset index VARIABLE count : natural RANGE 0 TO TotalLOC + 1; --memory used VARIABLE fwftcnt : natural RANGE 0 TO 3; -- fwft RCLK counter VARIABLE fwftcnt1 : natural RANGE 0 TO 3; -- fwft output VARIABLE fwftvar : boolean := false; -- fwft flag for outreg VARIABLE opireg : std_logic_vector(1 downto 0); VARIABLE outreg : std_logic_vector(39 downto 0); VARIABLE outtmp : std_logic_vector(39 downto 0); VARIABLE rd_upd_flg : boolean := false; VARIABLE wr_upd_flg : boolean := false; VARIABLE rt_mode : boolean := false; VARIABLE rtrdptr_set : boolean := false; VARIABLE rdptr_set : boolean := false; VARIABLE write_clk_paf : Natural := 0; VARIABLE read_clk_pae : Natural := 0; VARIABLE delayed_pae : boolean := false; VARIABLE delayed_paf : boolean := false; VARIABLE Eflagcnt : natural := 0; VARIABLE PAEflagcnt : natural := 0; VARIABLE PAFflagcnt : natural := 0; VARIABLE Fflagcnt : natural := 0; VARIABLE TotalLoc1: natural := TotalLoc; VARIABLE tRCLKposedge : Time := 0 ns; VARIABLE tWCLKposedge : Time := 0 ns; VARIABLE tRCLKnegedge : Time := 0 ns; VARIABLE tWCLKnegedge : Time := 0 ns; VARIABLE tOEnegedge : Time := 0 ns; VARIABLE minskew1RW : boolean := true; VARIABLE minskew2RW : boolean := true; VARIABLE minskew3RW : boolean := true; VARIABLE minskew1WR : boolean := true; VARIABLE minskew2WR : boolean := true; VARIABLE minskew3WR : boolean := true; VARIABLE last_done : last_done_type := none; VARIABLE flag_FF : std_logic := '0'; VARIABLE flag_EF : std_logic := '0'; VARIABLE flag_PAF : std_logic := '0'; VARIABLE flag_PAE : std_logic := '0'; VARIABLE pass_EF, pass_FF, pass_PAE, pass_PAF : boolean := false; VARIABLE bm_reg : std_logic_vector(2 downto 0); VARIABLE bm_Incnt : natural RANGE 0 TO 7 := 0; VARIABLE bm_Outcnt: natural RANGE 0 TO 7 := 0; VARIABLE fs_Incnt : natural RANGE 0 to 30 := 0; VARIABLE tmp_ser_in : std_logic_vector(29 downto 0) := (OTHERS=>'0'); -- Output Glitch Detection Variables VARIABLE FFNeg_GlitchData : VitalGlitchDataType; VARIABLE PAFNeg_GlitchData : VitalGlitchDataType; VARIABLE EFNeg_GlitchData : VitalGlitchDataType; VARIABLE PAENeg_GlitchData : VitalGlitchDataType; VARIABLE ERCLK_GlitchData : VitalGlitchDataType; VARIABLE ERENNeg_GlitchData : VitalGlitchDataType; VARIABLE SO_GlitchData : VitalGlitchDataType; PROCEDURE master_reset IS BEGIN mreset <= false, true AFTER 30 ns; -- valid reset signal fwftcnt := 0; PAENeg_zd := '0'; PAFNeg_zd := '1'; PAENeg_dly := '0'; PAFNeg_dly := '1'; TotalLoc1 := TotalLoc; rdptr := 0; wrptr := 0; count := 0; last_done := none; rt_mode := false; -- configuration section IF FWFTIn = '1' THEN fwft := true; -- fwft mode EFNeg_zd := '1'; FFNeg_zd := '0'; ELSE fwft := false; --idt standard mode EFNeg_zd := '0'; FFNeg_zd := '1'; END IF; IF BMIn = '0' THEN bm := false; ELSIF BMIn = '1' THEN bm := true; ELSE ASSERT FALSE REPORT "BM has unusable value" SEVERITY Warning; END IF; IF IWIn = '0' THEN iw := false; ELSIF IWIn = '1' THEN iw := true; ELSE ASSERT FALSE REPORT "IW has unusable value" SEVERITY Warning; END IF; IF OWIn = '0' THEN ow := false; ELSIF OWIn = '1' THEN ow := true; ELSE ASSERT FALSE REPORT "OW has unusable value" SEVERITY Warning; END IF; --bus matching byte counter bm_Incnt :=0; bm_Outcnt:=0; IF WSDRNegIn = '0' THEN mode_wr := SDR; ELSIF WSDRNegIn = '1' THEN mode_wr := DDR; ELSE ASSERT FALSE REPORT "WSDRNeg has unusable value" SEVERITY Warning; END IF; IF RSDRNegIn = '0' THEN mode_rd := SDR; ELSIF RSDRNegIn = '1' THEN mode_rd := DDR; ELSE ASSERT FALSE REPORT "RSDRNeg has unusable value" SEVERITY Warning; END IF; IF (mode_wr = DDR OR mode_rd = DDR) AND fwft THEN ASSERT FALSE REPORT "FWFT mode is not acceptable for double data rate!" SEVERITY error; END IF; opireg := (FSEL1In, FSEL0In); opi := To_Nat(opireg); paeoff := offsetps(opi); -- bus-match and rate mode - select input-output combination IF NOT(bm) AND NOT(iw) AND NOT(ow) THEN IF mode_wr = SDR THEN in_mode := SDR40; ELSE in_mode := DDR40; END IF; IF mode_rd = SDR THEN out_mode := SDR40; ELSE out_mode := DDR40; END IF; ELSIF bm AND NOT(iw) AND NOT(ow) THEN IF mode_wr = SDR THEN in_mode := SDR40; ELSE in_mode := DDR40; END IF; IF mode_rd = SDR THEN out_mode := SDR20; ELSE out_mode := DDR20; END IF; ELSIF bm AND NOT(iw) AND ow THEN IF mode_wr = SDR THEN in_mode := SDR40; ELSE in_mode := DDR40; END IF; IF mode_rd = SDR THEN out_mode := SDR10; ELSE out_mode := DDR10; END IF; ELSIF bm AND iw AND NOT(ow) THEN IF mode_wr = SDR THEN in_mode := SDR20; ELSE in_mode := DDR20; END IF; IF mode_rd = SDR THEN out_mode := SDR40; ELSE out_mode := DDR40; END IF; ELSIF bm AND iw AND ow THEN IF mode_wr = SDR THEN in_mode := SDR10; ELSE in_mode := DDR10; END IF; IF mode_rd = SDR THEN out_mode := SDR40; ELSE out_mode := DDR40; END IF; END IF; IF (in_mode=DDR40) OR (in_mode = DDR20 AND out_mode /= SDR40) OR (in_mode = DDR10 AND out_mode /= SDR40) OR (in_mode = SDR40 AND out_mode = DDR40) OR (in_mode = SDR20 AND out_mode = DDR40) OR (in_mode = SDR10 AND out_mode = DDR40) THEN memory_model := mapped; TotalLoc1 := TotalLoc/2; paeoff := (paeoff - 1)/2; ELSE memory_model := normal; TotalLoc1 := TotalLoc; END IF; pafoff := TotalLoc1 - paeoff; outreg := (others => '0'); Qreg := (others => '0'); END master_reset; PROCEDURE partial_reset IS BEGIN mreset <= false, true AFTER 30 ns; -- valid reset signal fwftcnt := 0; PAENeg_zd := '0'; PAFNeg_zd := '1'; PAENeg_dly := '0'; PAFNeg_dly := '1'; rdptr := 0; wrptr := 0; count := 0; last_done := none; rt_mode := false; IF fwft THEN EFNeg_zd := '1'; FFNeg_zd := '0'; ELSE EFNeg_zd := '0'; FFNeg_zd := '1'; END IF; Qreg := (others => '0'); bm_Incnt :=0; bm_Outcnt:=0; END partial_reset; PROCEDURE count_skew IS BEGIN IF (tWCLKposedge - tRCLKposedge) >= tSKEW1 THEN minskew1RW := true; ELSE minskew1RW := false; END IF; IF (tWCLKposedge - tRCLKnegedge) >= tSKEW2 THEN minskew2RW := true; ELSE minskew2RW := false; END IF; IF (tWCLKposedge - tRCLKposedge) >= tSKEW3 THEN minskew3RW := true; ELSE minskew3RW := false; END IF; IF (tRCLKposedge - tWCLKposedge) >= tSKEW1 THEN minskew1WR := true; ELSE minskew1WR := false; END IF; IF (tRCLKposedge - tWCLKnegedge) >= tSKEW2 THEN minskew2WR := true; ELSE minskew2WR := false; END IF; IF (tRCLKposedge - tWCLKposedge) >= tSKEW3 THEN minskew3WR := true; ELSE minskew3WR := false; END IF; END count_skew; PROCEDURE write_input IS BEGIN IF Violation = '0' THEN IF DIn(39 downto 30) /= "ZZZZZZZZZZ" THEN Data4 := to_nat(DIn(39 downto 30)); END IF; IF DIn(29 downto 20) /= "ZZZZZZZZZZ" THEN Data3 := to_nat(DIn(29 downto 20)); END IF; IF DIn(19 downto 10) /= "ZZZZZZZZZZ" THEN Data2 := to_nat(DIn(19 downto 10)); END IF; IF DIn(9 downto 0) /= "ZZZZZZZZZZ" THEN Data1 := to_nat(DIn(9 downto 0)); END IF; ELSE Data4 := -1; Data3 := -1; Data2 := -1; Data1 := -1; END IF; END write_input; PROCEDURE generate_output(pointer : IN Natural) IS BEGIN IF (RCLKIn = '1') THEN time_flag_for_OE <= '1', '0' AFTER tpd_RCLK_Q0(tr01); FROMRCLK := true; FROMOE := false; END IF; IF memA(pointer) >= 0 THEN Qreg_tmp(39 downto 30) := to_slv(memA(pointer),10); ELSE Qreg_tmp(39 downto 30) := (OTHERS => 'X'); END IF; IF memB(pointer) >= 0 THEN Qreg_tmp(29 downto 20) := to_slv(memB(pointer),10); ELSE Qreg_tmp(29 downto 20) := (OTHERS => 'X'); END IF; IF memC(pointer) >= 0 THEN Qreg_tmp(19 downto 10) := to_slv(memC(pointer),10); ELSE Qreg_tmp(19 downto 10) := (OTHERS => 'X'); END IF; IF memD(pointer) >= 0 THEN Qreg_tmp(9 downto 0) := to_slv(memD(pointer),10); ELSE Qreg_tmp(9 downto 0) := (OTHERS => 'X'); END IF; END generate_output; PROCEDURE write_register IS BEGIN IF rising_edge(SCLKIn) THEN IF memory_model = mapped THEN IF fs_Incnt=0 THEN tmp_ser_in := (OTHERS=>'0'); END IF; IF fs_Incnt<14 THEN tmp_ser_in(fs_Incnt):= SIIn; fs_Incnt:=fs_Incnt+1; paeoff:= to_nat(tmp_ser_in(13 downto 0)); ELSE tmp_ser_in(fs_Incnt):= SIIn; fs_Incnt:=fs_Incnt+1; pafoff:= to_nat(tmp_ser_in(27 downto 14)); END IF; IF fs_Incnt>27 THEN fs_Incnt:=0; pafoff:=TotalLoc1-pafoff; END IF; ELSIF memory_model = normal THEN IF fs_Incnt=0 THEN tmp_ser_in := (OTHERS=>'0'); END IF; IF fs_Incnt<15 THEN tmp_ser_in(fs_Incnt):= SIIn; fs_Incnt:=fs_Incnt+1; paeoff:= to_nat(tmp_ser_in(14 downto 0)); ELSE tmp_ser_in(fs_Incnt):= SIIn; fs_Incnt:=fs_Incnt+1; pafoff:= to_nat(tmp_ser_in(29 downto 15)); END IF; IF fs_Incnt>29 THEN fs_Incnt:=0; pafoff:=TotalLoc-pafoff; END IF; END IF; END IF; END write_register; PROCEDURE read_register IS BEGIN IF rising_edge(SCLKIn) THEN IF memory_model = mapped THEN IF fs_Incnt < 28 THEN SO_zd := tmp_ser_in(fs_Incnt); fs_Incnt:=fs_Incnt+1; END IF; IF fs_Incnt >= 28 THEN fs_Incnt:=0; END IF; ELSIF memory_model = normal THEN IF fs_Incnt < 30 THEN SO_zd := tmp_ser_in(fs_Incnt); fs_Incnt:=fs_Incnt+1; END IF; IF fs_Incnt >= 30 THEN fs_Incnt:=0; END IF; END IF; END IF; END read_register; BEGIN ---------------------------------------------------------------------------- -- Timing Check Section ---------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- tDS, tDH VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "D", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_D0_WCLK, SetupLow => tsetup_D0_WCLK, HoldHigh => thold_D0_WCLK, HoldLow => thold_D0_WCLK, CheckEnabled => (WENNegIn='0' AND WCSNegIn='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_D_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_WCLK ); VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "D", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_D0_WCLK, SetupLow => tsetup_D0_WCLK, HoldHigh => thold_D0_WCLK, HoldLow => thold_D0_WCLK, CheckEnabled => (WENNegIn='0' AND WCSNegIn='0' AND mode_wr=DDR), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_D_WCLK_DDR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_WCLK_DDR ); -- tENS, tENH VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => (RCSNegIn='0' AND RENNegIn='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RCLK ); VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => (WCSNegIn='0' AND WENNegIn='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_WCLK ); VitalSetupHoldCheck ( TestSignal => RCSNegIn, TestSignalName => "RCSNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => (RCSNegIn='0' AND RENNegIn='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RCSNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RCSNeg_RCLK ); VitalSetupHoldCheck ( TestSignal => RTNegIn, TestSignalName => "RTNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RTNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_RCLK ); VitalSetupHoldCheck ( TestSignal => MARKIn, TestSignalName => "MARK", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_MARK_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MARK_RCLK ); -- tWCSS, tWCSH VitalSetupHoldCheck ( TestSignal => WCSNegIn, TestSignalName => "WCSNeg", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_WCSNeg_WCLK, SetupLow => tsetup_WCSNeg_WCLK, HoldHigh => thold_WCSNeg_WCLK, HoldLow => thold_WCSNeg_WCLK, CheckEnabled => (WCSNegIn='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WCSNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WCSNeg_WCLK ); -- tSDS, tSDH VitalSetupHoldCheck ( TestSignal => SIIn, TestSignalName => "SI", RefSignal => SCLKIn, RefSignalName => "SCLK", SetupHigh => tsetup_SI_SCLK, SetupLow => tsetup_SI_SCLK, HoldHigh => thold_SI_SCLK, HoldLow => thold_SI_SCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SI_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SI_SCLK ); -- tSENS, tSENH VitalSetupHoldCheck ( TestSignal => SENNegIn, TestSignalName => "SENNeg", RefSignal => SCLKIn, RefSignalName => "SCLK", SetupHigh => tsetup_SENNeg_SCLK, SetupLow => tsetup_SENNeg_SCLK, HoldHigh => thold_SENNeg_SCLK, HoldLow => thold_SENNeg_SCLK, CheckEnabled => (SENNeg = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SENNeg_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_SCLK ); VitalSetupHoldCheck ( TestSignal => SRENNegIn, TestSignalName => "SRENNeg", RefSignal => SCLKIn, RefSignalName => "SCLK", SetupHigh => tsetup_SENNeg_SCLK, SetupLow => tsetup_SENNeg_SCLK, HoldHigh => thold_SENNeg_SCLK, HoldLow => thold_SENNeg_SCLK, CheckEnabled => (SRENNeg = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SRENNeg_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SRENNeg_SCLK ); -- tRSS VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => SENNegIn, TestSignalName => "SENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => SRENNegIn, TestSignalName => "SRENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SRENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SRENNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => FWFTIn, TestSignalName => "FWFT", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_FWFT_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFT_MRSNeg ); VitalSetupHoldCheck ( TestSignal => FSEL1In, TestSignalName => "FSEL1", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_FSEL1_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FSEL1_MRSNeg ); VitalSetupHoldCheck ( TestSignal => FSEL0In, TestSignalName => "FSEL0", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_FSEL0_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FSEL0_MRSNeg ); VitalSetupHoldCheck ( TestSignal => BMIn, TestSignalName => "BM", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_BM_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BM_MRSNeg ); VitalSetupHoldCheck ( TestSignal => OWIn, TestSignalName => "OW", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_OW_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_OW_MRSNeg ); VitalSetupHoldCheck ( TestSignal => IWIn, TestSignalName => "IW", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_IW_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IW_MRSNeg ); VitalSetupHoldCheck ( TestSignal => WSDRNegIn, TestSignalName => "WSDRNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WSDRNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WSDRNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => RSDRNegIn, TestSignalName => "RSDRNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RSDRNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RSDRNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => RTNegIn, TestSignalName => "RTNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RTNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_MRSNeg ); -- tHRSS VitalSetupHoldCheck ( TestSignal => HSTLIn, TestSignalName => "HSTL", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_HSTL_MRSNeg, SetupLow => tsetup_HSTL_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_HSTL_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_HSTL_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_PRSNeg ); VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_PRSNeg ); VitalSetupHoldCheck ( TestSignal => SENNegIn, TestSignalName => "SENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_PRSNeg ); VitalSetupHoldCheck ( TestSignal => SRENNegIn, TestSignalName => "SRENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SRENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SRENNeg_PRSNeg ); VitalSetupHoldCheck ( TestSignal => RTNegIn, TestSignalName => "RTNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RTNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_PRSNeg ); -- tRSR VitalRecoveryRemovalCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_RENNeg_MRSNeg ); VitalRecoveryRemovalCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_WENNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => FWFTIn, TestSignalName => "FWFT", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", HoldHigh => trecovery_RENNeg_MRSNeg, HoldLow => trecovery_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => RD_FWFT_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_FWFT_MRSNeg ); VitalSetupHoldCheck ( TestSignal => WSDRNegIn, TestSignalName => "WSDRNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", HoldHigh => trecovery_RENNeg_MRSNeg, HoldLow => trecovery_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => RD_WSDRNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_WSDRNeg_MRSNeg ); VitalSetupHoldCheck ( TestSignal => RSDRNegIn, TestSignalName => "RSDRNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", HoldHigh => trecovery_RENNeg_MRSNeg, HoldLow => trecovery_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => RD_RSDRNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_RSDRNeg_MRSNeg ); VitalRecoveryRemovalCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_RENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_RENNeg_PRSNeg ); VitalRecoveryRemovalCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => PRSNegIn, RefSignalName => "PRSNeg", Recovery => trecovery_RENNeg_MRSNeg, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_WENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_WENNeg_PRSNeg ); -- tRS VitalPeriodPulseCheck ( TestSignal => MRSNegIn, TestSignalName => "MRSNeg", PulseWidthLow => tpw_MRSNeg_negedge, HeaderMsg => InstancePath & partID, CheckEnabled => TRUE, PeriodData => PD_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MRSNeg ); VitalPeriodPulseCheck ( TestSignal => PRSNegIn, TestSignalName => "PRSNeg", PulseWidthLow => tpw_MRSNeg_negedge, HeaderMsg => InstancePath & partID, CheckEnabled => TRUE, PeriodData => PD_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_PRSNeg ); -- tCLK1, tCLKL1, tCLKH1 VitalPeriodPulseCheck ( TestSignal => RCLKIn, TestSignalName => "RCLK", Period => tperiod_RCLK_SDR_posedge, PulseWidthLow => tpw_RCLK_SDR_negedge, PulseWidthHigh => tpw_RCLK_SDR_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => mode_rd = SDR AND mreset, PeriodData => PD_RCLK1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RCLK1 ); VitalPeriodPulseCheck ( TestSignal => WCLKIn, TestSignalName => "WCLK", Period => tperiod_RCLK_SDR_posedge, PulseWidthLow => tpw_RCLK_SDR_negedge, PulseWidthHigh => tpw_RCLK_SDR_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => mode_wr = SDR AND mreset, PeriodData => PD_WCLK1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WCLK1 ); -- tCLK2, tCLKL2, tCLKH2 VitalPeriodPulseCheck ( TestSignal => RCLKIn, TestSignalName => "RCLK", Period => tperiod_RCLK_DDR_posedge, PulseWidthLow => tpw_RCLK_DDR_negedge, PulseWidthHigh => tpw_RCLK_DDR_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => mode_rd = DDR AND mreset, PeriodData => PD_RCLK2, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RCLK2 ); -- tCLK2, tCLKL2, tCLKH2 VitalPeriodPulseCheck ( TestSignal => WCLKIn, TestSignalName => "WCLK", Period => tperiod_RCLK_DDR_posedge, PulseWidthLow => tpw_RCLK_DDR_negedge, PulseWidthHigh => tpw_RCLK_DDR_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => mode_wr = DDR AND mreset, PeriodData => PD_WCLK2, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WCLK2 ); -- tSCLK, tSCKH, tSCKHL VitalPeriodPulseCheck ( TestSignal => SCLKIn, TestSignalName => "SCLK", Period => tperiod_SCLK_posedge, PulseWidthLow => tpw_SCLK_negedge, PulseWidthHigh => tpw_SCLK_posedge, HeaderMsg => InstancePath & partID, CheckEnabled => true, PeriodData => PD_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCLK ); Violation := Tviol_D_WCLK OR Tviol_D_WCLK_DDR OR Tviol_RENNeg_RCLK OR Tviol_WENNeg_WCLK OR Tviol_RCSNeg_RCLK OR Tviol_RTNeg_RCLK OR Tviol_MARK_RCLK OR Tviol_WCSNeg_WCLK OR Tviol_SI_SCLK OR Tviol_SENNeg_SCLK OR Tviol_SRENNeg_SCLK OR Tviol_RENNeg_MRSNeg OR Tviol_WENNeg_MRSNeg OR Tviol_SENNeg_MRSNeg OR Tviol_SRENNeg_MRSNeg OR Tviol_FWFT_MRSNeg OR Tviol_FSEL1_MRSNeg OR Tviol_FSEL0_MRSNeg OR Tviol_BM_MRSNeg OR Tviol_OW_MRSNeg OR Tviol_IW_MRSNeg OR Tviol_WSDRNeg_MRSNeg OR Tviol_RSDRNeg_MRSNeg OR Tviol_RTNeg_MRSNeg OR Tviol_HSTL_MRSNeg OR Tviol_RENNeg_PRSNeg OR Tviol_WENNeg_PRSNeg OR Tviol_SENNeg_PRSNeg OR Tviol_SRENNeg_PRSNeg OR Tviol_RTNeg_PRSNeg OR Rviol_RENNeg_MRSNeg OR Rviol_WENNeg_MRSNeg OR Rviol_FWFT_MRSNeg OR Rviol_WSDRNeg_MRSNeg OR Rviol_RSDRNeg_MRSNeg OR Rviol_RENNeg_PRSNeg OR Rviol_WENNeg_PRSNeg OR Pviol_MRSNeg OR Pviol_PRSNeg OR Pviol_RCLK1 OR Pviol_WCLK1 OR Pviol_RCLK2 OR Pviol_WCLK2 OR Pviol_SCLK; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; ---------------------------------------------------------------------------- -- Functionality Section ---------------------------------------------------------------------------- IF falling_edge(MRSNegIn) THEN master_reset; ELSIF PRSNegIn'event AND PRSNegIn = '0' AND NOT MRSNegIn = '0' THEN partial_reset; END IF; -- skew counting IF rising_edge(WCLKIn) THEN tWCLKposedge := NOW; count_skew; END IF; IF falling_edge(WCLKIn) THEN tWCLKnegedge := NOW; count_skew; END IF; IF rising_edge(RCLKIn) THEN tRCLKposedge := Now; count_skew; END IF; IF falling_edge(RCLKIn) THEN tRCLKnegedge := NOW; count_skew; END IF; -- write to fifo IF mreset AND WCLKIn'event THEN IF ((FFNeg_zd = '1' AND not fwft) OR (FFNeg_zd = '0' AND fwft)) OR bm_Incnt /= 0 THEN CASE in_mode IS -- different bus-match and rate modes WHEN DDR40 => IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' AND bm_Incnt = 0 THEN write_input; memA(wrptr) := Data4; memB(wrptr) := Data3; memC(wrptr) := Data2; memD(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt :=bm_Incnt + 1; ELSIF bm_Incnt = 1 THEN write_input; memA(wrptr_next + TotalLoc/2) := Data4; memB(wrptr_next + TotalLoc/2) := Data3; memC(wrptr_next + TotalLoc/2) := Data2; memD(wrptr_next + TotalLoc/2) := Data1; last_done := write; bm_Incnt:=0; END IF; WHEN DDR20 => IF out_mode = SDR40 THEN IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' AND bm_Incnt = 0 THEN write_input; memA(wrptr) := Data2; memB(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=1 THEN write_input; memC(wrptr_next) := Data2; memD(wrptr_next) := Data1; last_done := write; bm_Incnt:=0; END IF; ELSE IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' AND bm_Incnt = 0 THEN write_input; memA(wrptr) := Data2; memB(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=1 THEN write_input; memC(wrptr_next) := Data2; memD(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=2 THEN write_input; memA(wrptr_next + TotalLoc/2) :=Data2; memB(wrptr_next + TotalLoc/2) :=Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=3 THEN write_input; memC(wrptr_next + TotalLoc/2) :=Data2; memD(wrptr_next + TotalLoc/2) := Data1; last_done := write; bm_Incnt:=0; END IF; END IF; WHEN DDR10 => IF out_mode = SDR40 THEN IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' AND bm_Incnt = 0 THEN write_input; memA(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=1 THEN write_input; memB(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=2 THEN write_input; memC(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=3 THEN write_input; memD(wrptr_next) := Data1; last_done := write; bm_Incnt:=0; END IF; ELSE IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' AND bm_Incnt = 0 THEN write_input; memA(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=1 THEN write_input; memB(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=2 THEN write_input; memC(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=3 THEN write_input; memD(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=4 THEN write_input; memA(wrptr_next + TotalLoc/2) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=5 THEN write_input; memB(wrptr_next + TotalLoc/2) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=6 THEN write_input; memC(wrptr_next + TotalLoc/2) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt=7 THEN write_input; memD(wrptr_next + TotalLoc/2) := Data1; last_done := write; bm_Incnt:=0; END IF; END IF; WHEN SDR40 => IF out_mode = DDR40 THEN IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' THEN IF bm_Incnt = 0 THEN write_input; memA(wrptr) := Data4; memB(wrptr) := Data3; memC(wrptr) := Data2; memD(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 1 THEN write_input; memA(wrptr_next + TotalLoc/2) :=Data4; memB(wrptr_next + TotalLoc/2) :=Data3; memC(wrptr_next + TotalLoc/2) :=Data2; memD(wrptr_next + TotalLoc/2) :=Data1; last_done := write; bm_Incnt:=0; END IF; END IF; ELSE IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' THEN write_input; memA(wrptr) := Data4; memB(wrptr) := Data3; memC(wrptr) := Data2; memD(wrptr) := Data1; wrote_in := true; last_done := write; bm_Incnt:=0; IF (count=0 AND fwft) THEN outtmp := DIn; END IF; END IF; END IF; WHEN SDR20 => IF out_mode = DDR40 THEN IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' THEN IF bm_Incnt = 0 THEN write_input; memA(wrptr) := Data2; memB(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 1 THEN write_input; memC(wrptr_next) := Data2; memD(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 2 THEN write_input; memA(wrptr_next + TotalLoc/2) :=Data2; memB(wrptr_next + TotalLoc/2) :=Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 3 THEN write_input; memC(wrptr_next + TotalLoc/2) :=Data2; memD(wrptr_next + TotalLoc/2) :=Data1; last_done := write; bm_Incnt:=0; END IF; END IF; ELSE IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' THEN IF bm_Incnt = 0 THEN write_input; memA(wrptr) := Data2; memB(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; IF (count=0 AND fwft) THEN outtmp(39 downto 20) := DIn(19 downto 0); END IF; ELSIF bm_Incnt = 1 THEN write_input; memC(wrptr_next) := Data2; memD(wrptr_next) := Data1; last_done := write; bm_Incnt:=0; IF (count=1 AND fwft) THEN outtmp(19 downto 0) := DIn(19 downto 0); END IF; END IF; END IF; END IF; WHEN SDR10 => IF out_mode = DDR40 THEN IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' THEN IF bm_Incnt = 0 THEN write_input; memA(wrptr) := Data1; wrptr_next := wrptr; wrote_in := true; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 1 THEN write_input; memB(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 2 THEN write_input; memC(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 3 THEN write_input; memD(wrptr_next) := Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 4 THEN write_input; memA(wrptr_next + TotalLoc/2) :=Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 5 THEN write_input; memB(wrptr_next + TotalLoc/2) :=Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 6 THEN write_input; memC(wrptr_next + TotalLoc/2) :=Data1; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 7 THEN write_input; memD(wrptr_next + TotalLoc/2) :=Data1; last_done := write; bm_Incnt:=0; END IF; END IF; ELSE IF rising_edge(WCLKIn) AND WENNegIn = '0' AND WCSNegIn = '0' THEN IF bm_Incnt = 0 THEN write_input; memA(wrptr) := Data1; wrote_in := true; bm_Incnt:=bm_Incnt + 1; wrptr_next := wrptr; IF (count=0 AND fwft) THEN outtmp(39 downto 30) := DIn(9 downto 0); END IF; ELSIF bm_Incnt = 1 THEN write_input; memB(wrptr_next) := Data1; IF (count=1 AND fwft) THEN outtmp(29 downto 20) := DIn(9 downto 0); END IF; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 2 THEN write_input; memC(wrptr_next) := Data1; IF (count=1 AND fwft) THEN outtmp(19 downto 10) := DIn(9 downto 0); END IF; bm_Incnt:=bm_Incnt + 1; ELSIF bm_Incnt = 3 THEN write_input; memD(wrptr_next) := Data1; IF (count=1 AND fwft) THEN outtmp(9 downto 0) := DIn(9 downto 0); END IF; last_done := write; bm_Incnt:=0; END IF; END IF; END IF; WHEN OTHERS => null; END CASE; END IF; --- flag ctrl if just wrote in IF wrote_in THEN wrote_in := false; IF (fwft AND FFNeg_zd = '0') OR (NOT(fwft) AND FFNeg_zd = '1') THEN--not full -- write pointer IF wrptr < TotalLoc1 - 1 THEN IF NOT(rt_mode) THEN wrptr := wrptr + 1; ELSE IF (wrptr /= rtrdptr - 1) THEN wrptr := wrptr + 1; END IF; END IF; ELSE wrptr := 0; END IF; --counter count := count + 1; -- FFNeg sync updating IF count = TotalLoc1 THEN IF fwft THEN FFNeg_zd := '1'; ELSE FFNeg_zd := '0'; END IF; END IF; -- PAFNeg sync updating IF pafoff <= count THEN PAFNeg_dly := '0'; delayed_paf := true; ELSE PAFNeg_dly := '1'; END IF; -- flags for EFNeg and PAENeg updating IF count = 1 OR count = paeoff + 1 THEN wr_upd_flg := true; ELSE wr_upd_flg := false; END IF; END IF; END IF; IF rising_edge(WCLKIn) THEN -- FFNeg updating when reading active IF mode_rd = DDR THEN IF NOT(minskew2RW) AND flag_FF = '1' THEN IF Fflagcnt < 1 THEN Fflagcnt := Fflagcnt + 1; ELSE FFNeg_zd := '1'; Fflagcnt := 0; flag_FF := '0'; END IF; ELSIF minskew2RW AND flag_FF = '1' THEN FFNeg_zd := '1'; Fflagcnt := 0; flag_FF := '0'; END IF; ELSE IF NOT(minskew1RW) AND flag_FF = '1' THEN IF Fflagcnt < 1 THEN Fflagcnt := Fflagcnt + 1; ELSE IF NOT(fwft) THEN FFNeg_zd := '1'; ELSE FFNeg_zd := '0'; END IF; Fflagcnt := 0; flag_FF := '0'; END IF; ELSIF minskew1RW AND flag_FF = '1' THEN IF NOT(fwft) THEN FFNeg_zd := '1'; ELSE FFNeg_zd := '0'; END IF; Fflagcnt := 0; flag_FF := '0'; END IF; END IF; -- PAFNeg updating when write active IF write_clk_paf = 2 AND delayed_paf THEN PAFNeg_zd := PAFNeg_dly; write_clk_paf := 0; delayed_paf := false; ELSIF delayed_paf THEN write_clk_paf := write_clk_paf + 1; END IF; -- PAFNeg updating when read active IF NOT(minskew3RW) AND flag_PAF = '1' THEN IF PAFflagcnt < 1 THEN PAFflagcnt := PAFflagcnt + 1; ELSE PAFNeg_zd := '1'; PAFflagcnt := 0; flag_PAF := '0'; END IF; ELSIF minskew3RW AND flag_PAF = '1' THEN PAFNeg_zd := '1'; PAFflagcnt := 0; flag_PAF := '0'; END IF; -- FFNeg updating when read active IF rd_upd_flg AND count = TotalLoc1 - 1 THEN pass_FF := true; rd_upd_flg := false; END IF; IF last_done = read AND pass_FF THEN flag_FF := '1'; pass_FF := false; END IF; -- PAFNeg updating when read active IF rd_upd_flg AND count = pafoff - 1 THEN pass_PAF := true; rd_upd_flg := false; END IF; IF last_done = read AND pass_PAF THEN flag_PAF := '1'; pass_PAF := false; END IF; END IF; END IF; --- First Word Fall Through IF rising_edge(RCLKIn) AND fwft THEN IF count = 1 AND fwftcnt = 0 AND last_done = write AND EFNeg_zd = '1' THEN fwftcnt := fwftcnt + 1; outreg := outtmp; rdptr := rdptr + 1; count := 0; ELSIF fwftcnt = 1 THEN fwftcnt := fwftcnt + 1; ELSIF fwftcnt = 2 THEN fwftvar := true; EFNeg_zd := '0'; fwftcnt := 0; fwftcnt1 := 0; FROMOE := false; FROMRCLK := true; END IF; IF fwftvar THEN IF out_mode = SDR40 THEN Qreg := outreg; fwftvar := false; ELSIF out_mode = SDR20 THEN IF fwftcnt1 = 0 THEN Qreg(19 downto 0) := outreg(39 downto 20); fwftcnt1 := 1; ELSE Qreg(19 downto 0) := outreg(19 downto 0); fwftcnt1 := 0; fwftvar := false; END IF; ELSIF out_mode = SDR10 THEN IF fwftcnt1 = 0 THEN Qreg(9 downto 0) := outreg(39 downto 30); fwftcnt1 := 1; ELSIF fwftcnt1 = 1 THEN Qreg(9 downto 0) := outreg(29 downto 20); fwftcnt1 := 2; ELSIF fwftcnt1 = 2 THEN Qreg(9 downto 0) := outreg(19 downto 10); fwftcnt1 := 3; ELSE Qreg(9 downto 0) := outreg(9 downto 0); fwftcnt1 := 0; fwftvar := false; END IF; END IF; END IF; END IF; -- empty fifo in fwft mode IF count = 0 AND EFNeg_zd = '0' AND fwft AND RENNeg = '0' AND rising_edge(RCLKIn) AND RCSNeg = '0' THEN EFNeg_zd := '1'; END IF; IF mreset AND RCLKIn'EVENT THEN -- echo read clock IF rising_edge(RCLKIn) THEN ERCLK_zd := '1'; ELSIF falling_edge(RCLKIn) THEN ERCLK_zd := '0'; END IF; -- echo read enable IF ((EFNeg_zd='1' AND NOT(fwft)) OR (EFNeg_zd='0' AND fwft)) AND rising_edge(RCLKIn) AND (RENNegIn='0') AND RCSNegIn='0' THEN ERENNeg_zd := '0'; ELSIF (rising_edge(RCLKIn) AND last_done = read) OR (rising_edge(RCLKIn) AND (RENNegIn = '1')) THEN -- at the end of the reading cycle ERENNeg_zd := '1'; -- or if RENNeg inactive END IF; --retransmit-- IF rising_edge(RCLKIn) AND MARKIn='1' AND NOT(rt_mode) THEN rt_mode := true; rtrdptr_set := false; rdptr_set := false; ELSIF rising_edge(RCLKIn) AND MARKIn = '0' AND rt_mode THEN rt_mode := false; END IF; IF rising_edge(RCLKIn) AND rt_mode THEN IF fwft THEN IF RENNegIn='0' AND RTNegIn = '1' AND count >= 32 THEN --retransmit setup IF rtrdptr_set = false THEN rtrdptr := rdptr; rtrdptr_set := true; rtreg := Qreg; END IF; ELSIF RENNegIn='1' AND RTNegIn = '0' AND rtrdptr_set THEN EFNeg_zd := '1'; --retransmit ELSIF RENNegIn='1' AND RTNegIn = '1' AND EFNeg_zd = '1' AND rtrdptr_set THEN IF rdptr_set = false THEN Qreg := rtreg; EFNeg_zd := '0'; rdptr := rtrdptr; rdptr_set := true; END IF; END IF; ELSE IF RENNegIn='0' AND RTNegIn = '1' AND ((memory_model = mapped AND count >= 16) OR (memory_model = normal AND count >= 32)) THEN --retransmit set IF rtrdptr_set = false THEN IF rdptr > 1 THEN rtrdptr := rdptr-1; ELSE rtrdptr := 0; END IF; rtrdptr_set := true; END IF; ELSIF RENNegIn='1' AND RTNegIn = '0' AND rtrdptr_set THEN EFNeg_zd := '0'; ELSIF RENNegIn='1' AND RTNegIn = '1' AND EFNeg_zd = '0' AND rtrdptr_set THEN IF rdptr_set = false THEN EFNeg_zd := '1'; rdptr := rtrdptr; rdptr_set := true; END IF; END IF; END IF; END IF; -- read from fifo IF ((count > 0) AND ((EFNeg_zd = '1' AND not fwft) OR (EFNeg_zd = '0' AND fwft))) OR bm_Outcnt /= 0 THEN CASE out_mode IS WHEN DDR40 => IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' AND bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(39 downto 30) := Qreg_tmp(39 downto 30); Qreg(29 downto 20) := Qreg_tmp(29 downto 20); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); read_out := true; rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(39 downto 30) := Qreg_tmp(39 downto 30); Qreg(29 downto 20) := Qreg_tmp(29 downto 20); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); last_done := read; bm_Outcnt :=0; END IF; WHEN DDR20 => IF in_mode = DDR40 THEN IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' AND bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(19 downto 10) := Qreg_tmp(39 downto 30); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 2 THEN generate_output(rdptr_next+TotalLoc/2); Qreg(19 downto 10) := Qreg_tmp(39 downto 30); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); read_out := true; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 3 THEN generate_output(rdptr_next+TotalLoc/2); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); last_done := read; bm_Outcnt :=0; END IF; ELSE IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' AND bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(19 downto 10) := Qreg_tmp(39 downto 30); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); read_out := true; rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); last_done := read; bm_Outcnt :=0; END IF; END IF; WHEN DDR10 => IF in_mode = DDR40 THEN IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' AND bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(9 downto 0) := Qreg_tmp(39 downto 30); rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 2 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 3 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 4 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(39 downto 30); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 5 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 6 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); read_out := true; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 7 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); last_done := read; bm_Outcnt :=0; END IF; ELSE IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' AND bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(9 downto 0) := Qreg_tmp(39 downto 30); rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 2 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); read_out := true; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 3 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); last_done := read; bm_Outcnt :=0; END IF; END IF; WHEN SDR40 => IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' THEN IF in_mode = DDR40 THEN IF bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(39 downto 30) := Qreg_tmp(39 downto 30); Qreg(29 downto 20) := Qreg_tmp(29 downto 20); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(39 downto 30) := Qreg_tmp(39 downto 30); Qreg(29 downto 20) := Qreg_tmp(29 downto 20); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); read_out := true; last_done := read; bm_Outcnt :=0; END IF; ELSE generate_output(rdptr); Qreg(39 downto 30) := Qreg_tmp(39 downto 30); Qreg(29 downto 20) := Qreg_tmp(29 downto 20); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); last_done := read; read_out := true; bm_Outcnt :=0; END IF; END IF; WHEN SDR20 => IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' THEN IF in_mode = DDR40 THEN IF bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(19 downto 10) := Qreg_tmp(39 downto 30); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); bm_Outcnt :=bm_Outcnt + 1; rdptr_next := rdptr; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 2 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(19 downto 10) := Qreg_tmp(39 downto 30); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 3 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); read_out := true; last_done := read; bm_Outcnt :=0; END IF; ELSE IF bm_Outcnt = 0 THEN Qreg:=(OTHERS=>'0'); generate_output(rdptr); Qreg(19 downto 10) := Qreg_tmp(39 downto 30); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(19 downto 10) := Qreg_tmp(19 downto 10); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); read_out := true; last_done := read; bm_Outcnt :=0; END IF; END IF; END IF; WHEN SDR10 => IF rising_edge(RCLKIn) AND RENNegIn = '0' AND RCSNegIn = '0' THEN IF in_mode = DDR40 THEN IF bm_Outcnt = 0 THEN generate_output(rdptr); Qreg(9 downto 0) := Qreg_tmp(39 downto 30); rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 2 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 3 THEN generate_output(rdptr_next); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 4 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(39 downto 30); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 5 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(29 downto 20); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 6 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(19 downto 10); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 7 THEN generate_output(rdptr_next + TotalLoc/2); Qreg(9 downto 0) := Qreg_tmp(9 downto 0); read_out := true; last_done := read; bm_Outcnt :=0; END IF; ELSE IF bm_Outcnt = 0 THEN Qreg(9 downto 0) := to_slv(memA(rdptr),10); rdptr_next := rdptr; bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 1 THEN Qreg(9 downto 0) := to_slv(memB(rdptr_next),10); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 2 THEN Qreg(9 downto 0) := to_slv(memC(rdptr_next),10); bm_Outcnt :=bm_Outcnt + 1; ELSIF bm_Outcnt = 3 THEN Qreg(9 downto 0) := to_slv(memD(rdptr_next),10); read_out := true; last_done := read; bm_Outcnt :=0; END IF; END IF; END IF; WHEN OTHERS => null; END CASE; END IF; IF read_out THEN read_out := false; IF (fwft AND EFNeg_zd = '0') OR (not(fwft) AND EFNeg_zd = '1') THEN --not empty -- read pointer IF rdptr < TotalLOC1 - 1 THEN rdptr := rdptr + 1; ELSE rdptr := 0; END IF; -- counter count := count - 1; -- update PAENeg, delayed IF count <= paeoff THEN PAENeg_dly := '0'; delayed_pae := true; ELSE PAENeg_dly := '1'; END IF; -- update EFNeg, for idt standard mode only IF count = 0 AND NOT(fwft) THEN EFNeg_zd := '0'; END IF; -- for updating PAFNeg and FFNeg IF (count = TotalLoc1 -1) OR (count = pafoff - 1) THEN rd_upd_flg := true; ELSE rd_upd_flg := false; END IF; END IF; END IF; IF rising_edge(RCLKIn) THEN --EFNeg updating when reading active IF mode_wr = DDR THEN IF NOT(minskew2WR) AND flag_EF = '1' THEN IF Eflagcnt < 1 THEN Eflagcnt := Eflagcnt + 1; ELSE EFNeg_zd := '1'; Eflagcnt := 0; flag_EF := '0'; END IF; ELSIF minskew2WR AND flag_EF = '1' THEN EFNeg_zd := '1'; Eflagcnt := 0; flag_EF := '0'; END IF; ELSE IF NOT(minskew1WR) AND flag_EF = '1' THEN IF NOT(fwft) THEN IF Eflagcnt < 1 THEN Eflagcnt := Eflagcnt + 1; ELSE EFNeg_zd := '1'; Eflagcnt := 0; flag_EF := '0'; END IF; ELSE IF Eflagcnt < 2 THEN Eflagcnt := Eflagcnt + 1; ELSE EFNeg_zd := '0'; Eflagcnt := 0; flag_EF := '0'; END IF; END IF; ELSIF minskew1WR AND flag_EF = '1' THEN IF NOT(fwft) THEN EFNeg_zd := '1'; Eflagcnt := 0; flag_EF := '0'; ELSE IF Eflagcnt < 1 THEN Eflagcnt := Eflagcnt + 1; ELSE EFNeg_zd := '0'; Eflagcnt := 0; flag_EF := '0'; END IF; END IF; END IF; END IF; --PAENeg updating when writing - delayed IF read_clk_pae = 2 AND delayed_pae THEN PAENeg_zd := PAENeg_dly; read_clk_pae := 0; delayed_pae := false; ELSIF delayed_pae THEN read_clk_pae := read_clk_pae + 1; END IF; --PAENeg updating when write active IF NOT(minskew3WR) AND flag_PAE = '1' THEN IF PAEflagcnt < 1 THEN PAEflagcnt := PAEflagcnt + 1; ELSE PAENeg_zd := '1'; PAEflagcnt := 0; flag_PAE := '0'; END IF; ELSIF minskew3WR AND flag_PAE = '1' THEN PAENeg_zd := '1'; PAEflagcnt := 0; flag_PAE := '0'; END IF; --EFNeg updating when reading active IF wr_upd_flg AND count = 1 THEN pass_EF := true; wr_upd_flg := false; END IF; IF last_done = write AND pass_EF THEN flag_EF := '1'; pass_EF := false; END IF; --PAENeg updating when write active IF wr_upd_flg AND count = paeoff + 1 THEN pass_PAE := true; wr_upd_flg := false; END IF; IF last_done = write AND pass_PAE THEN flag_PAE := '1'; pass_PAE := false; END IF; END IF; END IF; IF rising_edge(SENNegIn) OR rising_edge(SRENNegIn) THEN fs_Incnt := 0; END IF; -- write to offset registers and read from them IF SENNegIn='0' AND mreset THEN write_register; ELSIF SRENNegIn='0' AND mreset THEN read_register; END IF; -- path delay resolving IF falling_edge(OENeg) THEN tOEnegedge := Now; FROMOE := false; IF time_flag_for_OE = '1' THEN IF (tpd_RCLK_Q0(tr01) - (tOEnegedge - tRCLKposedge)) >= tpd_OENeg_Q0(tr01) THEN FROMOE := false; FROMRCLK := true; ELSE FROMOE := true; FROMRCLK := false; END IF; ELSE FROMOE := true; FROMRCLK := false; END IF; END IF; -- OENeg IF mreset THEN IF OENegIn = '0' AND RCSNeg = '0' THEN Q_zd <= Qreg; ELSIF OENegIn = '1' OR RCSNeg = '1' THEN Q_zd <= (others => 'Z'); END IF; END IF; ---------------------------------------------------------------------------- -- Path Delay Section ---------------------------------------------------------------------------- VitalPathDelay01 ( OutSignal => ERCLKOut, OutSignalName => "ERCLK", OutTemp => ERCLK_zd, Mode => VitalTransport, Paths => ( 0 => (InputChangeTime => RCLK'LAST_EVENT, PathDelay => tpd_RCLK_ERCLK, PathCondition => TRUE) ), GlitchData => ERCLK_GlitchData ); VitalPathDelay01Z ( OutSignal => SOOut, OutSignalName => "SO", OutTemp => SO_zd, Paths => ( 0 => (InputChangeTime => SCLK'LAST_EVENT, PathDelay => tpd_RCLK_Q0, PathCondition => TRUE) ), GlitchData => SO_GlitchData ); VitalPathDelay01 ( OutSignal => ERENNegOut, OutSignalName => "ERENNeg", OutTemp => ERENNeg_zd, Paths => ( 0 => (InputChangeTime => RCLK'LAST_EVENT, PathDelay => tpd_RCLK_ERENNeg, PathCondition => TRUE) ), GlitchData => ERENNeg_GlitchData ); VitalPathDelay01 ( OutSignal => EFNegOut, OutSignalName => "EFNeg", OutTemp => EFNeg_zd, GlitchData => EFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_RCLK_EFNeg, PathCondition => true) ) ); VitalPathDelay01 ( OutSignal => FFNegOut, OutSignalName => "FFNeg", OutTemp => FFNeg_zd, GlitchData => FFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => WCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_FFNeg, PathCondition => true) ) ); VitalPathDelay01 ( OutSignal => PAENegOut, OutSignalName => "PAENeg", OutTemp => PAENeg_zd, GlitchData => PAENeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => tpd_RCLK_PAENeg, PathCondition => true) ) ); VitalPathDelay01 ( OutSignal => PAFNegOut, OutSignalName => "PAFNeg", OutTemp => PAFNeg_zd, GlitchData => PAFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => tpd_MRSNeg_EFNeg, PathCondition => true), 2 => (InputChangeTime => WCLKIn'LAST_EVENT, PathDelay => tpd_WCLK_PAFNeg, PathCondition => true) ) ); END PROCESS Fifo; ------------------------------------------------------------------------ -- Path Delay Processes generated as a function of data width ------------------------------------------------------------------------ DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE DataOut_Delay : PROCESS (Q_zd(i)) VARIABLE Q_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => QOut(i), OutSignalName => "Q", OutTemp => Q_zd(i), Mode => OnEvent, GlitchData => Q_GlitchData(i), Paths => ( 0 => (InputChangeTime => MRSNegIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_MRSNeg_EFNeg), PathCondition => TRUE), 1 => (InputChangeTime => RCLKIn'LAST_EVENT, PathDelay => (tpd_RCLK_Q0), PathCondition => FROMRCLK), 2 => (InputChangeTime => PRSNegIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_MRSNeg_EFNeg), PathCondition => TRUE), 3 => (InputChangeTime => OENegIn'LAST_EVENT, PathDelay => tpd_OENeg_Q0, PathCondition => FROMOE) ) ); END PROCESS DataOut_Delay; END GENERATE; END BLOCK; END vhdl_behavioral;