-------------------------------------------------------------------------------- -- File Name: idt72t36135m.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 A.Anic 05 Dec 12 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FIFO -- Technology: CMOS -- Part: idt72t36135m -- Description: 18Mb (524,288 x 36) High-Speed FIFO -------------------------------------------------------------------------------- -- Known Bugs: -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.vital_primitives.ALL; USE ieee.vital_timing.ALL; USE ieee.std_logic_1164.ALL; LIBRARY fmf; USE fmf.gen_utils.ALL; USE fmf.conversions.to_nat; USE fmf.conversions.to_slv; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY idt72t36135m IS GENERIC ( -- tipd delays: interconnect path delays tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_D18 : VitalDelayType01 := VitalZeroDelay01; tipd_D19 : VitalDelayType01 := VitalZeroDelay01; tipd_D20 : VitalDelayType01 := VitalZeroDelay01; tipd_D21 : VitalDelayType01 := VitalZeroDelay01; tipd_D22 : VitalDelayType01 := VitalZeroDelay01; tipd_D23 : VitalDelayType01 := VitalZeroDelay01; tipd_D24 : VitalDelayType01 := VitalZeroDelay01; tipd_D25 : VitalDelayType01 := VitalZeroDelay01; tipd_D26 : VitalDelayType01 := VitalZeroDelay01; tipd_D27 : VitalDelayType01 := VitalZeroDelay01; tipd_D28 : VitalDelayType01 := VitalZeroDelay01; tipd_D29 : VitalDelayType01 := VitalZeroDelay01; tipd_D30 : VitalDelayType01 := VitalZeroDelay01; tipd_D31 : VitalDelayType01 := VitalZeroDelay01; tipd_D32 : VitalDelayType01 := VitalZeroDelay01; tipd_D33 : VitalDelayType01 := VitalZeroDelay01; tipd_D34 : VitalDelayType01 := VitalZeroDelay01; tipd_D35 : VitalDelayType01 := VitalZeroDelay01; tipd_ASYRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ASYWNeg : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL1 : VitalDelayType01 := VitalZeroDelay01; tipd_FWFT : VitalDelayType01 := VitalZeroDelay01; tipd_MARK : VitalDelayType01 := VitalZeroDelay01; tipd_LDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_MRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_PFM : VitalDelayType01 := VitalZeroDelay01; tipd_PRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SCLK : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK : VitalDelayType01 := VitalZeroDelay01; tipd_WENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WCSNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: -- tA tpd_RCLK_Q0_SYN_EQ_1 : VitalDelayType01Z := UnitDelay01Z; tpd_RCLK_Q0_ASYN_EQ_1 : VitalDelayType01Z := UnitDelay01Z; -- tOLZ,tOHZ,tOE tpd_OENeg_Q0_SYN_EQ_1 : VitalDelayType01Z := UnitDelay01Z; tpd_OENeg_Q0_ASYN_EQ_1 : VitalDelayType01Z := UnitDelay01Z; -- tRSF tpd_MRSNeg_EF1Neg : VitalDelayType01 := UnitDelay01; tpd_MRSNeg_FF1Neg : VitalDelayType01 := UnitDelay01; tpd_MRSNeg_PAE1Neg : VitalDelayType01 := UnitDelay01; tpd_MRSNeg_PAF1Neg : VitalDelayType01 := UnitDelay01; tpd_MRSNeg_Q0 : VitalDelayType01Z := UnitDelay01Z; tpd_PRSNeg_EF1Neg : VitalDelayType01 := UnitDelay01; tpd_PRSNeg_FF1Neg : VitalDelayType01 := UnitDelay01; tpd_PRSNeg_PAE1Neg : VitalDelayType01 := UnitDelay01; tpd_PRSNeg_PAF1Neg : VitalDelayType01 := UnitDelay01; tpd_PRSNeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tWFF,tREF,tPAFS,tPAES,tPAFA,tPAEA,tHF tpd_WCLK_FF1Neg_SYN_EQ_1 : VitalDelayType01 := UnitDelay01; tpd_WCLK_FF1Neg_ASYN_EQ_1 : VitalDelayType01 := UnitDelay01; tpd_RCLK_FF1Neg : VitalDelayType01 := UnitDelay01; tpd_RCLK_EF1Neg_SYN_EQ_1 : VitalDelayType01 := UnitDelay01; tpd_RCLK_EF1Neg_ASYN_EQ_1 : VitalDelayType01 := UnitDelay01; tpd_WCLK_EF1Neg : VitalDelayType01 := UnitDelay01; tpd_RCLK_EF1Neg : VitalDelayType01 := UnitDelay01; tpd_WCLK_PAF1Neg_ASYN_EQ_1 : VitalDelayType01 := UnitDelay01; tpd_WCLK_PAF1Neg_SYN_EQ_1 : VitalDelayType01 := UnitDelay01; tpd_RCLK_PAF1Neg : VitalDelayType01 := UnitDelay01; tpd_RCLK_PAE1Neg_ASYN_EQ_1 : VitalDelayType01 := UnitDelay01; tpd_RCLK_PAE1Neg_SYN_EQ_1 : VitalDelayType01 := UnitDelay01; tpd_WCLK_PAE1Neg : VitalDelayType01 := UnitDelay01; -- tsetup values: setup times -- tDS tsetup_D0_WCLK : VitalDelayType := UnitDelay; tsetup_FWFT_SCLK : VitalDelayType := UnitDelay; -- tENS,tLDS,tWCSS tsetup_WENNeg_WCLK : VitalDelayType := UnitDelay; tsetup_LDNeg_WCLK : VitalDelayType := UnitDelay; tsetup_WCSNeg_WCLK : VitalDelayType := UnitDelay; tsetup_LDNeg_RCLK : VitalDelayType := UnitDelay; tsetup_RENNeg_RCLK : VitalDelayType := UnitDelay; tsetup_WENNeg_RCLK : VitalDelayType := UnitDelay; tsetup_RTNeg_RCLK : VitalDelayType := UnitDelay; tsetup_RCSNeg_RCLK : VitalDelayType := UnitDelay; tsetup_MARK_RCLK : VitalDelayType := UnitDelay; tsetup_LDNeg_SCLK : VitalDelayType := UnitDelay; tsetup_SENNeg_SCLK : VitalDelayType := UnitDelay; -- tRSS tsetup_RENNeg_MRSNeg : VitalDelayType := UnitDelay; tsetup_WENNeg_MRSNeg : VitalDelayType := UnitDelay; tsetup_FWFT_MRSNeg : VitalDelayType := UnitDelay; tsetup_LDNeg_MRSNeg : VitalDelayType := UnitDelay; tsetup_FSEL0_MRSNeg : VitalDelayType := UnitDelay; tsetup_FSEL1_MRSNeg : VitalDelayType := UnitDelay; tsetup_PFM_MRSNeg : VitalDelayType := UnitDelay; tsetup_RTNeg_MRSNeg : VitalDelayType := UnitDelay; tsetup_SENNeg_MRSNeg : VitalDelayType := UnitDelay; tsetup_RENNeg_PRSNeg : VitalDelayType := UnitDelay; tsetup_WENNeg_PRSNeg : VitalDelayType := UnitDelay; tsetup_RTNeg_PRSNeg : VitalDelayType := UnitDelay; tsetup_SENNeg_PRSNeg : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH thold_D0_WCLK : VitalDelayType := UnitDelay; thold_FWFT_SCLK : VitalDelayType := UnitDelay; -- tENH,tLDH,tWCSH thold_WENNeg_WCLK : VitalDelayType := UnitDelay; thold_LDNeg_WCLK : VitalDelayType := UnitDelay; thold_WCSNeg_WCLK : VitalDelayType := UnitDelay; thold_LDNeg_RCLK : VitalDelayType := UnitDelay; thold_RENNeg_RCLK : VitalDelayType := UnitDelay; thold_RTNeg_RCLK : VitalDelayType := UnitDelay; thold_RCSNeg_RCLK : VitalDelayType := UnitDelay; thold_MARK_RCLK : VitalDelayType := UnitDelay; thold_LDNeg_SCLK : VitalDelayType := UnitDelay; thold_SENNeg_SCLK : VitalDelayType := UnitDelay; -- tRSR thold_RENNeg_MRSNeg : VitalDelayType := UnitDelay; thold_WENNeg_MRSNeg : VitalDelayType := UnitDelay; thold_FWFT_MRSNeg : VitalDelayType := UnitDelay; thold_LDNeg_MRSNeg : VitalDelayType := UnitDelay; thold_RENNeg_PRSNeg : VitalDelayType := UnitDelay; thold_WENNeg_PRSNeg : VitalDelayType := UnitDelay; -- tpw values: pulse widths -- tCLKL, tCLKH tpw_WCLK_SYN_EQ_1_negedge : VitalDelayType := UnitDelay; tpw_WCLK_ASYN_EQ_1_negedge : VitalDelayType := UnitDelay; tpw_WCLK_SYN_EQ_1_posedge : VitalDelayType := UnitDelay; tpw_WCLK_ASYN_EQ_1_posedge : VitalDelayType := UnitDelay; tpw_RCLK_SYN_EQ_1_negedge : VitalDelayType := UnitDelay; tpw_RCLK_ASYN_EQ_1_negedge : VitalDelayType := UnitDelay; tpw_RCLK_SYN_EQ_1_posedge : VitalDelayType := UnitDelay; tpw_RCLK_ASYN_EQ_1_posedge : VitalDelayType := UnitDelay; tpw_SCLK_posedge : VitalDelayType := UnitDelay; tpw_SCLK_negedge : VitalDelayType := UnitDelay; -- tPW tpw_MRSNeg_negedge : VitalDelayType := UnitDelay; tpw_PRSNeg_negedge : VitalDelayType := UnitDelay; -- tperiod values -- tCLK tperiod_WCLK_SYN_EQ_1_posedge : VitalDelayType := UnitDelay; tperiod_WCLK_ASYN_EQ_1_posedge : VitalDelayType := UnitDelay; tperiod_RCLK_SYN_EQ_1_posedge : VitalDelayType := UnitDelay; tperiod_RCLK_ASYN_EQ_1_posedge : VitalDelayType := UnitDelay; tperiod_SCLK_posedge : VitalDelayType := UnitDelay; -- tSKEW1 (skew time) tdevice_SKEW1 : VitalDelayType := UnitDelay; -- tSKEW2 (skew time) tdevice_SKEW2 : VitalDelayType := UnitDelay; -- tRPE (skew time) tdevice_RPE : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; TimingModel : STRING := DefaultTimingModel); PORT ( D0 : IN std_ulogic := 'U'; -- D1 : IN std_ulogic := 'U'; -- D2 : IN std_ulogic := 'U'; -- D3 : IN std_ulogic := 'U'; -- D4 : IN std_ulogic := 'U'; -- Data Input Bus D5 : IN std_ulogic := 'U'; -- D6 : IN std_ulogic := 'U'; -- D7 : IN std_ulogic := 'U'; -- D8 : IN std_ulogic := 'U'; -- D9 : IN std_ulogic := 'U'; -- D10 : IN std_ulogic := 'U'; -- D11 : IN std_ulogic := 'U'; -- D12 : IN std_ulogic := 'U'; -- D13 : IN std_ulogic := 'U'; -- D14 : IN std_ulogic := 'U'; -- Data Input Bus D15 : IN std_ulogic := 'U'; -- D16 : IN std_ulogic := 'U'; -- D17 : IN std_ulogic := 'U'; -- D18 : IN std_ulogic := 'U'; -- D19 : IN std_ulogic := 'U'; -- D20 : IN std_ulogic := 'U'; -- D21 : IN std_ulogic := 'U'; -- D22 : IN std_ulogic := 'U'; -- D23 : IN std_ulogic := 'U'; -- D24 : IN std_ulogic := 'U'; -- Data Input Bus D25 : IN std_ulogic := 'U'; -- D26 : IN std_ulogic := 'U'; -- D27 : IN std_ulogic := 'U'; -- D28 : IN std_ulogic := 'U'; -- D29 : IN std_ulogic := 'U'; -- D30 : IN std_ulogic := 'U'; -- D31 : IN std_ulogic := 'U'; -- D32 : IN std_ulogic := 'U'; -- D33 : IN std_ulogic := 'U'; -- D34 : IN std_ulogic := 'U'; -- Data Input Bus D35 : IN std_ulogic := 'U'; -- ASYRNeg : IN std_ulogic := 'U'; -- Asynchronous Read Port ASYWNeg : IN std_ulogic := 'U'; -- Asynchronous Write Port FSEL0 : IN std_ulogic := 'U'; -- Flag Select Bit 0 FSEL1 : IN std_ulogic := 'U'; -- Flag Select Bit 1 FWFT : IN std_ulogic := 'U'; -- First Word FallThrough LDNeg : IN std_ulogic := 'U'; -- Load MARK : IN std_ulogic := 'U'; -- Mark for Retransmit OENeg : IN std_ulogic := 'U'; -- Output Enable MRSNeg : IN std_ulogic := 'U'; -- Master Reset PFM : IN std_ulogic := 'U'; -- Programmable Flag Mode PRSNeg : IN std_ulogic := 'U'; -- Partial Reset RCLK : IN std_ulogic := 'U'; -- Read Clock RENNeg : IN std_ulogic := 'U'; -- Read Enable RCSNeg : IN std_ulogic := 'U'; -- Read Chip Select RTNeg : IN std_ulogic := 'U'; -- Retrasmint SENNeg : IN std_ulogic := 'U'; -- Serial Enable SCLK : IN std_ulogic := 'U'; -- Serial Clock WCLK : IN std_ulogic := 'U'; -- Write Clock WENNeg : IN std_ulogic := 'U'; -- Write Enable WCSNeg : IN std_ulogic := 'U'; -- Write Chip Select EF1Neg : OUT std_ulogic := 'U'; -- Empty Flag1 EF2Neg : OUT std_ulogic := 'U'; -- Empty Flag2 FF1Neg : OUT std_ulogic := 'U'; -- Full Flag1 FF2Neg : OUT std_ulogic := 'U'; -- Full Flag2 PAE1Neg : OUT std_ulogic := 'U'; -- Programmable Almost Empty Flag1 PAE2Neg : OUT std_ulogic := 'U'; -- Programmable Almost Empty Flag2 PAF1Neg : OUT std_ulogic := 'U'; -- Programmable Almost Full Flag1 PAF2Neg : OUT std_ulogic := 'U'; -- Programmable Almost Full Flag2 Q0 : OUT std_logic := 'Z'; -- Q1 : OUT std_logic := 'Z'; -- Q2 : OUT std_logic := 'Z'; -- Q3 : OUT std_logic := 'Z'; -- Q4 : OUT std_logic := 'Z'; -- Data Output Bus Q5 : OUT std_logic := 'Z'; -- Q6 : OUT std_logic := 'Z'; -- Q7 : OUT std_logic := 'Z'; -- Q8 : OUT std_logic := 'Z'; -- Q9 : OUT std_logic := 'Z'; -- Q10 : OUT std_logic := 'Z'; -- Q11 : OUT std_logic := 'Z'; -- Q12 : OUT std_logic := 'Z'; -- Q13 : OUT std_logic := 'Z'; -- Q14 : OUT std_logic := 'Z'; -- Data Output Bus Q15 : OUT std_logic := 'Z'; -- Q16 : OUT std_logic := 'Z'; -- Q17 : OUT std_logic := 'Z'; -- Q18 : OUT std_logic := 'Z'; -- Q19 : OUT std_logic := 'Z'; -- Q20 : OUT std_logic := 'Z'; -- Q21 : OUT std_logic := 'Z'; -- Q22 : OUT std_logic := 'Z'; -- Q23 : OUT std_logic := 'Z'; -- Q24 : OUT std_logic := 'Z'; -- Data Output Bus Q25 : OUT std_logic := 'Z'; -- Q26 : OUT std_logic := 'Z'; -- Q27 : OUT std_logic := 'Z'; -- Q28 : OUT std_logic := 'Z'; -- Q29 : OUT std_logic := 'Z'; -- Q30 : OUT std_logic := 'Z'; -- Q31 : OUT std_logic := 'Z'; -- Q32 : OUT std_logic := 'Z'; -- Q33 : OUT std_logic := 'Z'; -- Q34 : OUT std_logic := 'Z'; -- Data Output Bus Q35 : OUT std_logic := 'Z'); -- ATTRIBUTE vital_level0 OF idt72t36135m : ENTITY IS True; END idt72t36135m; ----------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ----------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF idt72t36135m IS ATTRIBUTE vital_level0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : String := "idt72t36135m"; -- delayed inputs SIGNAL D0_ipd : std_ulogic := 'U'; SIGNAL D1_ipd : std_ulogic := 'U'; SIGNAL D2_ipd : std_ulogic := 'U'; SIGNAL D3_ipd : std_ulogic := 'U'; SIGNAL D4_ipd : std_ulogic := 'U'; SIGNAL D5_ipd : std_ulogic := 'U'; SIGNAL D6_ipd : std_ulogic := 'U'; SIGNAL D7_ipd : std_ulogic := 'U'; SIGNAL D8_ipd : std_ulogic := 'U'; SIGNAL D9_ipd : std_ulogic := 'U'; SIGNAL D10_ipd : std_ulogic := 'U'; SIGNAL D11_ipd : std_ulogic := 'U'; SIGNAL D12_ipd : std_ulogic := 'U'; SIGNAL D13_ipd : std_ulogic := 'U'; SIGNAL D14_ipd : std_ulogic := 'U'; SIGNAL D15_ipd : std_ulogic := 'U'; SIGNAL D16_ipd : std_ulogic := 'U'; SIGNAL D17_ipd : std_ulogic := 'U'; SIGNAL D18_ipd : std_ulogic := 'U'; SIGNAL D19_ipd : std_ulogic := 'U'; SIGNAL D20_ipd : std_ulogic := 'U'; SIGNAL D21_ipd : std_ulogic := 'U'; SIGNAL D22_ipd : std_ulogic := 'U'; SIGNAL D23_ipd : std_ulogic := 'U'; SIGNAL D24_ipd : std_ulogic := 'U'; SIGNAL D25_ipd : std_ulogic := 'U'; SIGNAL D26_ipd : std_ulogic := 'U'; SIGNAL D27_ipd : std_ulogic := 'U'; SIGNAL D28_ipd : std_ulogic := 'U'; SIGNAL D29_ipd : std_ulogic := 'U'; SIGNAL D30_ipd : std_ulogic := 'U'; SIGNAL D31_ipd : std_ulogic := 'U'; SIGNAL D32_ipd : std_ulogic := 'U'; SIGNAL D33_ipd : std_ulogic := 'U'; SIGNAL D34_ipd : std_ulogic := 'U'; SIGNAL D35_ipd : std_ulogic := 'U'; SIGNAL ASYRNeg_ipd : std_ulogic := 'U'; SIGNAL ASYWNeg_ipd : std_ulogic := 'U'; SIGNAL FSEL0_ipd : std_ulogic := 'U'; SIGNAL FSEL1_ipd : std_ulogic := 'U'; SIGNAL FWFT_ipd : std_ulogic := 'U'; SIGNAL LDNeg_ipd : std_ulogic := 'U'; SIGNAL MARK_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL MRSNeg_ipd : std_ulogic := 'U'; SIGNAL PFM_ipd : std_ulogic := 'U'; SIGNAL PRSNeg_ipd : std_ulogic := 'U'; SIGNAL RCLK_ipd : std_ulogic := 'U'; SIGNAL RENNeg_ipd : std_ulogic := 'U'; SIGNAL RCSNeg_ipd : std_ulogic := 'U'; SIGNAL RTNeg_ipd : std_ulogic := 'U'; SIGNAL SENNeg_ipd : std_ulogic := 'U'; SIGNAL SCLK_ipd : std_ulogic := 'U'; SIGNAL WCLK_ipd : std_ulogic := 'U'; SIGNAL WENNeg_ipd : std_ulogic := 'U'; SIGNAL WCSNeg_ipd : std_ulogic := 'U'; -- FIFO memory definations CONSTANT TotalLoc : positive := 524287; CONSTANT DataWidth : positive := 36; CONSTANT MaxData : positive := 262143; -- SKEW stuff (see also generics list) ALIAS tSKEW1 : VitalDelayType IS tdevice_SKEW1; ALIAS tSKEW2 : VitalDelayType IS tdevice_SKEW2; ALIAS tRPE : VitalDelayType IS tdevice_RPE; SIGNAL BufIn, BufOut : std_logic; SIGNAL Const0 : std_logic := '0'; SIGNAL Const1 : std_logic := '1'; TYPE SyncAsync IS (Synchronous, Asynchronous); SHARED VARIABLE FromOE : BOOLEAN; SHARED VARIABLE FromRCLK : BOOLEAN; SHARED VARIABLE ProgFlagMode : SyncAsync; SIGNAL EFNeg_zd : std_logic_vector(1 TO 2); SIGNAL FFNeg_zd : std_logic_vector(1 TO 2); SIGNAL QOut_zd : std_logic_vector(35 DOWNTO 0); SIGNAL PAENeg_zd : std_logic_vector(1 TO 2); SIGNAL PAFNeg_zd : std_logic_vector(1 TO 2); BEGIN -------------------------------------------------------------- -- Dummy instances for exporting tSKEW vals from SDF file -- using DEVICE construct -------------------------------------------------------------- SKEW1: VitalBuf (BufOut, BufIn, (tdevice_SKEW2, tdevice_SKEW2)); SKEW2: VitalBuf (BufOut, BufIn, (tdevice_SKEW2, tdevice_SKEW2)); RPE: VitalBuf (BufOut, BufIn, (tdevice_RPE, tdevice_RPE)); ------------------------------------------------------------------- -- Wire Delays ------------------------------------------------------------------- WireDelay: BLOCK BEGIN w_1: VitalWireDelay (D0_ipd , D0 , tipd_D0 ); w_2: VitalWireDelay (D1_ipd , D1 , tipd_D1 ); w_3: VitalWireDelay (D2_ipd , D2 , tipd_D2 ); w_4: VitalWireDelay (D3_ipd , D3 , tipd_D3 ); w_5: VitalWireDelay (D4_ipd , D4 , tipd_D4 ); w_6: VitalWireDelay (D5_ipd , D5 , tipd_D5 ); w_7: VitalWireDelay (D6_ipd , D6 , tipd_D6 ); w_8: VitalWireDelay (D7_ipd , D7 , tipd_D7 ); w_9: VitalWireDelay (D8_ipd , D8 , tipd_D8 ); w_10: VitalWireDelay (D9_ipd , D9 , tipd_D9 ); w_11: VitalWireDelay (D10_ipd , D10 , tipd_D10 ); w_12: VitalWireDelay (D11_ipd , D11 , tipd_D11 ); w_13: VitalWireDelay (D12_ipd , D12 , tipd_D12 ); w_14: VitalWireDelay (D13_ipd , D13 , tipd_D13 ); w_15: VitalWireDelay (D14_ipd , D14 , tipd_D14 ); w_16: VitalWireDelay (D15_ipd , D15 , tipd_D15 ); w_17: VitalWireDelay (D16_ipd , D16 , tipd_D16 ); w_18: VitalWireDelay (D17_ipd , D17 , tipd_D17 ); w_19: VitalWireDelay (D18_ipd , D18 , tipd_D18 ); w_20: VitalWireDelay (D19_ipd , D19 , tipd_D19 ); w_21: VitalWireDelay (D20_ipd , D20 , tipd_D20 ); w_22: VitalWireDelay (D21_ipd , D21 , tipd_D21 ); w_23: VitalWireDelay (D22_ipd , D22 , tipd_D22 ); w_24: VitalWireDelay (D23_ipd , D23 , tipd_D23 ); w_25: VitalWireDelay (D24_ipd , D24 , tipd_D24 ); w_26: VitalWireDelay (D25_ipd , D25 , tipd_D25 ); w_27: VitalWireDelay (D26_ipd , D26 , tipd_D26 ); w_28: VitalWireDelay (D27_ipd , D27 , tipd_D27 ); w_29: VitalWireDelay (D28_ipd , D28 , tipd_D28 ); w_30: VitalWireDelay (D29_ipd , D29 , tipd_D29 ); w_31: VitalWireDelay (D30_ipd , D30 , tipd_D30 ); w_32: VitalWireDelay (D31_ipd , D31 , tipd_D31 ); w_33: VitalWireDelay (D32_ipd , D32 , tipd_D32 ); w_34: VitalWireDelay (D33_ipd , D33 , tipd_D33 ); w_35: VitalWireDelay (D34_ipd , D34 , tipd_D34 ); w_36: VitalWireDelay (D35_ipd , D35 , tipd_D35 ); w_37: VitalWireDelay (ASYRNeg_ipd , ASYRNeg , tipd_ASYRNeg ); w_38: VitalWireDelay (ASYWNeg_ipd , ASYWNeg , tipd_ASYWNeg ); w_39: VitalWireDelay (FSEL0_ipd , FSEL0 , tipd_FSEL0 ); w_40: VitalWireDelay (FSEL1_ipd , FSEL1 , tipd_FSEL1 ); w_41: VitalWireDelay (FWFT_ipd , FWFT , tipd_FWFT ); w_42: VitalWireDelay (LDNeg_ipd , LDNeg , tipd_LDNeg ); w_43: VitalWireDelay (MARK_ipd , MARK , tipd_MARK ); w_44: VitalWireDelay (OENeg_ipd , OENeg , tipd_OENeg ); w_45: VitalWireDelay (MRSNeg_ipd , MRSNeg , tipd_MRSNeg ); w_46: VitalWireDelay (PRSNeg_ipd , PRSNeg , tipd_PRSNeg ); w_47: VitalWireDelay (PFM_ipd , PFM , tipd_PFM ); w_48: VitalWireDelay (RCLK_ipd , RCLK , tipd_RCLK ); w_49: VitalWireDelay (RENNeg_ipd , RENNeg , tipd_RENNeg ); w_50: VitalWireDelay (RCSNeg_ipd , RCSNeg , tipd_RCSNeg ); w_51: VitalWireDelay (RTNeg_ipd , RTNeg , tipd_RTNeg ); w_52: VitalWireDelay (SENNeg_ipd , SENNeg , tipd_SENNeg ); w_53: VitalWireDelay (SCLK_ipd , SCLK , tipd_SCLK ); w_54: VitalWireDelay (WCLK_ipd , WCLK , tipd_WCLK ); w_55: VitalWireDelay (WENNeg_ipd , WENNeg , tipd_WENNeg ); w_56: VitalWireDelay (WCSNeg_ipd , WCSNeg , tipd_WCSNeg ); END BLOCK WireDelay; ------------------------------------------------------------------- -- Main behavior Block ------------------------------------------------------------------- Main: BLOCK PORT ( DIn : IN std_logic_vector( 35 DOWNTO 0):= (OTHERS=>'U'); ASYRNeg : IN std_ulogic := 'U'; ASYWNeg : IN std_ulogic := 'U'; FSEL0 : IN std_ulogic := 'U'; FSEL1 : IN std_ulogic := 'U'; FWFT : IN std_ulogic := 'U'; LDNeg : IN std_ulogic := 'U'; MARK : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; MRSNeg : IN std_ulogic := 'U'; PRSNeg : IN std_ulogic := 'U'; PFM : IN std_ulogic := 'U'; RCLK : IN std_ulogic := 'U'; RENNeg : IN std_ulogic := 'U'; RCSNeg : IN std_ulogic := 'U'; RTNeg : IN std_ulogic := 'U'; SENNeg : IN std_ulogic := 'U'; SCLK : IN std_ulogic := 'U'; WCLK : IN std_ulogic := 'U'; WENNeg : IN std_ulogic := 'U'; WCSNeg : IN std_ulogic := 'U'; QOut : OUT std_logic_vector( 35 DOWNTO 0) := (OTHERS=>'Z'); EFNeg : OUT std_logic_vector(1 TO 2) := (OTHERS => 'U'); FFNeg : OUT std_logic_vector(1 TO 2) := (OTHERS => 'U'); PAENeg : OUT std_logic_vector(1 TO 2) := (OTHERS => 'U'); PAFNeg : OUT std_logic_vector(1 TO 2) := (OTHERS => 'U') ); PORT MAP ( DIn(0) => D0_ipd, DIn(1) => D1_ipd, DIn(2) => D2_ipd, DIn(3) => D3_ipd, DIn(4) => D4_ipd, DIn(5) => D5_ipd, DIn(6) => D6_ipd, DIn(7) => D7_ipd, DIn(8) => D8_ipd, DIn(9) => D9_ipd, DIn(10) => D10_ipd, DIn(11) => D11_ipd, DIn(12) => D12_ipd, DIn(13) => D13_ipd, DIn(14) => D14_ipd, DIn(15) => D15_ipd, DIn(16) => D16_ipd, DIn(17) => D17_ipd, DIn(18) => D18_ipd, DIn(19) => D19_ipd, DIn(20) => D20_ipd, DIn(21) => D21_ipd, DIn(22) => D22_ipd, DIn(23) => D23_ipd, DIn(24) => D24_ipd, DIn(25) => D25_ipd, DIn(26) => D26_ipd, DIn(27) => D27_ipd, DIn(28) => D28_ipd, DIn(29) => D29_ipd, DIn(30) => D30_ipd, DIn(31) => D31_ipd, DIn(32) => D32_ipd, DIn(33) => D33_ipd, DIn(34) => D34_ipd, DIn(35) => D35_ipd, ASYRNeg => ASYRNeg_ipd, ASYWNeg => ASYWNeg_ipd, FSEL0 => FSEL0_ipd, FSEL1 => FSEL1_ipd, FWFT => FWFT_ipd, LDNeg => LDNeg_ipd, MARK => MARK_ipd, OENeg => OENeg_ipd, MRSNeg => MRSNeg_ipd, PRSNeg => PRSNeg_ipd, PFM => PFM_ipd, RCLK => RCLK_ipd, RENNeg => RENNeg_ipd, RCSNeg => RCSNeg_ipd, RTNeg => RTNeg_ipd, SENNeg => SENNeg_ipd, SCLK => SCLK_ipd, WCLK => WCLK_ipd, WENNeg => WENNeg_ipd, WCSNeg => WCSNeg_ipd, QOut(0) => Q0, QOut(1) => Q1, QOut(2) => Q2, QOut(3) => Q3, QOut(4) => Q4, QOut(5) => Q5, QOut(6) => Q6, QOut(7) => Q7, QOut(8) => Q8, QOut(9) => Q9, QOut(10) => Q10, QOut(11) => Q11, QOut(12) => Q12, QOut(13) => Q13, QOut(14) => Q14, QOut(15) => Q15, QOut(16) => Q16, QOut(17) => Q17, QOut(18) => Q18, QOut(19) => Q19, QOut(20) => Q20, QOut(21) => Q21, QOut(22) => Q22, QOut(23) => Q23, QOut(24) => Q24, QOut(25) => Q25, QOut(26) => Q26, QOut(27) => Q27, QOut(28) => Q28, QOut(29) => Q29, QOut(30) => Q30, QOut(31) => Q31, QOut(32) => Q32, QOut(33) => Q33, QOut(34) => Q34, QOut(35) => Q35, EFNeg(1) => EF1Neg, EFNeg(2) => EF2Neg, FFNeg(1) => FF1Neg, FFNeg(2) => FF2Neg, PAENeg(1) => PAE1Neg, PAENeg(2) => PAE2Neg, PAFNeg(1) => PAF1Neg, PAFNeg(2) => PAF2Neg ); SIGNAL flagRCLKskew1 : std_ulogic := '0'; SIGNAL flagRCLKskew2 : std_ulogic := '0'; SIGNAL flagWCLKskew1 : std_ulogic := '0'; SIGNAL flagWCLKskew2 : std_ulogic := '0'; SIGNAL flagRCS : std_ulogic := '0'; SIGNAL flagRCSNeg : std_ulogic := '0'; SIGNAL FlagForOE : std_ulogic := '0'; SIGNAL FlagForDelay : std_ulogic := '0'; SIGNAL flagRPE : std_ulogic := '0'; SIGNAL FlagAbd : std_ulogic := '0'; SIGNAL CopyFFNeg : std_ulogic := 'U'; SIGNAL CopyEFNeg : std_ulogic := 'U'; SIGNAL CopyHF : std_ulogic := 'U'; SIGNAL CopyPAF : std_ulogic := 'U'; SIGNAL CopyPAE : std_ulogic := 'U'; BEGIN CHECK: PROCESS (DIn,WCLK,RCLK,SCLK,WENNeg,RENNeg,SENNeg,RTNeg,LDNeg,FWFT, FSEL0,FSEL1,MRSNeg,PRSNeg,PFM,RCSNeg,WCSNeg,MARK, OENeg,CopyEFNeg) -- Pulse Width and Period Check Variables VARIABLE Pviol_WCLK_SYN : X01 := '0'; VARIABLE PD_WCLK_SYN : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WCLK_ASYN : X01 := '0'; VARIABLE PD_WCLK_ASYN : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RCLK_SYN : X01 := '0'; VARIABLE PD_RCLK_SYN : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RCLK_ASYN : X01 := '0'; VARIABLE PD_RCLK_ASYN : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_SCLK : X01 := '0'; VARIABLE PD_SCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MRSNeg : X01 := '0'; VARIABLE PD_MRSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRSNeg : X01 := '0'; VARIABLE PD_PRSNeg : VitalPeriodDataType := VitalPeriodDataInit; -- Setup/Hold Check Variables VARIABLE Tviol_DIn_WCLK : X01 := '0'; VARIABLE TD_DIn_WCLK : VitalTimingDataType; VARIABLE Tviol_FWFT_SCLK : X01 := '0'; VARIABLE TD_FWFT_SCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_WCLK : X01 := '0'; VARIABLE TD_WENNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_RCLK : X01 := '0'; VARIABLE TD_WENNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_RENNeg_RCLK : X01 := '0'; VARIABLE TD_RENNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_RENNeg_RCLK_RT : X01 := '0'; VARIABLE TD_RENNeg_RCLK_RT : VitalTimingDataType; VARIABLE Tviol_SENNeg_SCLK : X01 := '0'; VARIABLE TD_SENNeg_SCLK : VitalTimingDataType; VARIABLE Tviol_RTNeg_RCLK : X01 := '0'; VARIABLE TD_RTNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_LDNeg_RCLK : X01 := '0'; VARIABLE TD_LDNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_MARK_RCLK : X01 := '0'; VARIABLE TD_MARK_RCLK : VitalTimingDataType; VARIABLE Tviol_LDNeg_WCLK : X01 := '0'; VARIABLE TD_LDNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_LDNeg_SCLK : X01 := '0'; VARIABLE TD_LDNeg_SCLK : VitalTimingDataType; VARIABLE Tviol_WCSNeg_WCLK : X01 := '0'; VARIABLE TD_WCSNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_RCSNeg_RCLK : X01 := '0'; VARIABLE TD_RCSNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_RENNeg_MRSNeg : X01 := '0'; VARIABLE TD_RENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_WENNeg_MRSNeg : X01 := '0'; VARIABLE TD_WENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FWFT_MRSNeg : X01 := '0'; VARIABLE TD_FWFT_MRSNeg : VitalTimingDataType; VARIABLE Tviol_LDNeg_MRSNeg : X01 := '0'; VARIABLE TD_LDNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FSEL0_MRSNeg : X01 := '0'; VARIABLE TD_FSEL0_MRSNeg : VitalTimingDataType; VARIABLE Tviol_FSEL1_MRSNeg : X01 := '0'; VARIABLE TD_FSEL1_MRSNeg : VitalTimingDataType; VARIABLE Tviol_PFM_MRSNeg : X01 := '0'; VARIABLE TD_PFM_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RTNeg_MRSNeg : X01 := '0'; VARIABLE TD_RTNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_SENNeg_MRSNeg : X01 := '0'; VARIABLE TD_SENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_PRSNeg : X01 := '0'; VARIABLE TD_RENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_WENNeg_PRSNeg : X01 := '0'; VARIABLE TD_WENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_RTNeg_PRSNeg : X01 := '0'; VARIABLE TD_RTNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_SENNeg_PRSNeg : X01 := '0'; VARIABLE TD_SENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_MRSNeg_hold : X01 := '0'; VARIABLE TD_RENNeg_MRSNeg_hold : VitalTimingDataType; VARIABLE Tviol_WENNeg_MRSNeg_hold : X01 := '0'; VARIABLE TD_WENNeg_MRSNeg_hold : VitalTimingDataType; VARIABLE Tviol_FWFT_MRSNeg_hold : X01 := '0'; VARIABLE TD_FWFT_MRSNeg_hold : VitalTimingDataType; VARIABLE Tviol_LDNeg_MRSNeg_hold : X01 := '0'; VARIABLE TD_LDNeg_MRSNeg_hold : VitalTimingDataType; VARIABLE Tviol_RENNeg_PRSNeg_hold : X01 := '0'; VARIABLE TD_RENNeg_PRSNeg_hold : VitalTimingDataType; VARIABLE Tviol_WENNeg_PRSNeg_hold : X01 := '0'; VARIABLE TD_WENNeg_PRSNeg_hold : VitalTimingDataType; -- Violation variable VARIABLE Violation : X01 := '0'; -- Memory array declaration TYPE MemStore IS ARRAY (0 to TotalLoc) OF INTEGER RANGE -1 TO MaxData; TYPE yesno IS (yes, no); TYPE ProgramModeType IS (Serial, Parallel); TYPE ModeType IS (IDTStandard, FWFTMode); TYPE OffsetType IS (EOffset, FOffset); TYPE ByteOffsetType IS (LSBEmptyOffset, MSBEmptyOffset, LSBFullOffset, MSBFullOffset); TYPE RetransmitStatus IS (marked,initiated, hold, done); VARIABLE reset : yesno:= no; VARIABLE EnWrite : yesno:= no; VARIABLE PaLdEmptyOk : yesno:= no; VARIABLE PaLdEmptyEnd: yesno:= no; VARIABLE SerLdEnd : yesno:= no; VARIABLE SerLdOk : yesno:= no; VARIABLE ResetEF : yesno:= no; VARIABLE SetOR : yesno:= no; VARIABLE ResetFF : yesno:= no; VARIABLE SetPAF : yesno:= no; VARIABLE SetPAFabd : yesno:= no; VARIABLE SetPAF_1 : yesno:= no; VARIABLE ResetPAFabd : yesno:= no; VARIABLE ResetPAF : yesno:= no; VARIABLE ResetPAF_1 : yesno:= no; VARIABLE ResetOR : yesno:= no; VARIABLE SetIR : yesno:= no; VARIABLE ResetPAE : yesno:= no; VARIABLE ResetPAEabd : yesno:= no; VARIABLE ResetPAE_1 : yesno:= no; VARIABLE SetPAE_1 : yesno:= no; VARIABLE SetPAE : yesno:= no; VARIABLE SetPAEabd : yesno:= no; VARIABLE ResPAE_Ret : yesno:= no; VARIABLE SetPAE_Ret : yesno:= no; VARIABLE PaLdFullOk : yesno:= no; VARIABLE PaLdFullEnd : yesno:= no; VARIABLE FirstWord : yesno:= no; VARIABLE EnFirstWord : yesno:= no; VARIABLE EnReadOffs : yesno:= yes; VARIABLE CondAbd : yesno:= no; VARIABLE ProgramMode : ProgramModeType; VARIABLE ReadOperation : SyncAsync; VARIABLE WriteOperation : SyncAsync; VARIABLE Mode : ModeType; VARIABLE Retransmit : RetransmitStatus := done; VARIABLE ByteOffset : ByteOffsetType; VARIABLE ReadByteOffset : ByteOffsetType; VARIABLE FullOffset : INTEGER; VARIABLE EmptyOffset : INTEGER; VARIABLE ValueForPAE : INTEGER; VARIABLE ValueForPAF : INTEGER; VARIABLE WrPointer : INTEGER := 0; VARIABLE RdPointer : INTEGER := 0; VARIABLE OldRdPointer : INTEGER := 0; VARIABLE RefPointer : INTEGER := 0; VARIABLE CntRCLKforResEF : INTEGER; VARIABLE MarkedPointer : INTEGER; VARIABLE CntWCLKforResFF : INTEGER; VARIABLE CntRCLKforSetOR : INTEGER; VARIABLE CntRCLKforFirstWord : INTEGER; VARIABLE CntWCLKforSetPAF : INTEGER; VARIABLE CntWCLKforSetPAF_1 : INTEGER; VARIABLE CntWCLKforResPAF : INTEGER; VARIABLE CntWCLKforResPAF_1 : INTEGER; VARIABLE CntWCLKforSetIR : INTEGER; VARIABLE CntRCLKforSetPAE : INTEGER; VARIABLE CntRCLKforSetPAE_1 : INTEGER; VARIABLE CntRCLKforResPAE : INTEGER; VARIABLE CntRCLKforResPAE_1 : INTEGER; VARIABLE CountForSerial : INTEGER := 0; VARIABLE TmpMemLocRead_H : std_logic_vector(17 DOWNTO 0); VARIABLE TmpMemLocRead_L : std_logic_vector(17 DOWNTO 0); VARIABLE TmpMemLocRead : std_logic_vector(35 DOWNTO 0) := (OTHERS => '0'); VARIABLE TmpOffset : std_logic_vector(37 DOWNTO 0); VARIABLE TmpEmptyOffset : std_logic_vector(18 DOWNTO 0); VARIABLE TmpFullOffset : std_logic_vector(18 DOWNTO 0); VARIABLE TmpMemLocOE : std_logic_vector(35 DOWNTO 0) := (OTHERS => '0'); VARIABLE TmpOffsetRead : std_logic_vector(18 DOWNTO 0); VARIABLE MemDataHigh : MemStore; VARIABLE MemDataLow : MemStore; VARIABLE time_OE : TIME := 0 ns; VARIABLE time_RCLK : TIME := 0 ns; VARIABLE TimeForFlag : TIME := 0 ns; VARIABLE TimeForFlag_1 : TIME := 0 ns; -- Output Glitch Detection Variables PROCEDURE SetFlagForOE IS BEGIN IF OENeg = '1' THEN FlagForOE <= '1','0' AFTER TimeForFlag; END IF; END SetFlagForOE; PROCEDURE Pointer IS BEGIN IF Retransmit = done THEN RefPointer := RdPointer; ELSE RefPointer := MarkedPointer; END IF; END Pointer; PROCEDURE SetFlags (ValueForPAE : IN INTEGER; ValueForPAF : IN INTEGER) IS BEGIN IF (WrPointer > RdPointer AND WrPointer - RdPointer >= ValueForPAE+1) OR (WrPointer < RdPointer AND TotalLoc - RdPointer + WrPointer >= ValueForPAE) OR (WrPointer = RdPointer AND Mode = FWFTMode AND CopyFFNeg = '1') OR (WrPointer = RdPointer AND Mode = IDTStandard AND CopyFFNeg = '0') THEN ResetPAEabd := yes; CntRCLKforResPAE := 2; ELSE SetPAEabd := yes; CntRCLKforSetPAE := 2; END IF; Pointer; IF (WrPointer > RefPointer AND WrPointer - RefPointer >= ValueForPAF+1) OR (WrPointer < RefPointer AND TotalLoc - RefPointer + WrPointer >= ValueForPAF)OR (WrPointer = RefPointer AND Mode = FWFTMode AND CopyFFNeg = '1') OR (WrPointer = RefPointer AND Mode = IDTStandard AND CopyFFNeg = '0')THEN SetPAFabd := yes; CntWCLKforSetPAF := 2; ELSE ResetPAFabd := yes; CntWCLKforResPAF := 2; END IF; END SetFlags; PROCEDURE SetFlagsRt (ValueForPAE : IN INTEGER; ValueForPAF : IN INTEGER) IS BEGIN IF (WrPointer > RdPointer AND WrPointer - RdPointer >= ValueForPAE+1) OR (WrPointer < RdPointer AND TotalLoc - RdPointer + WrPointer >= ValueForPAE) OR (WrPointer = RdPointer AND Mode = FWFTMode AND CopyFFNeg = '1') OR (WrPointer = RdPointer AND Mode = IDTStandard AND CopyFFNeg = '0') THEN ResetPAE := yes; CntRCLKforResPAE := 1; ELSE SetPAE := yes; CntRCLKforSetPAE := 1; END IF; Pointer; IF (WrPointer > RefPointer AND WrPointer - RefPointer >= ValueForPAF+1) OR (WrPointer < RefPointer AND TotalLoc - RefPointer + WrPointer >= ValueForPAF) OR (WrPointer = RefPointer AND Mode = FWFTMode AND CopyFFNeg = '1') OR (WrPointer = RefPointer AND Mode = IDTStandard AND CopyFFNeg = '0') THEN SetPAF := yes; CntWCLKforSetPAF := 1; ELSE ResetPAF := yes; CntWCLKforResPAF := 1; END IF; END SetFlagsRt; PROCEDURE SetFlagsWrite (ValueForPAE_Wr : IN INTEGER; ValueForPAF_Wr : IN INTEGER) IS BEGIN IF WrPointer >= RdPointer THEN IF (WrPointer > RdPointer AND WrPointer - RdPointer = ValueForPAE_Wr+1) OR (WrPointer = RdPointer AND TotalLoc = ValueForPAE_Wr) THEN IF ProgFlagMode = Asynchronous THEN PAENeg_zd <= (OTHERS => '1'); CopyPAE <= '1'; ELSE ResetPAE := yes; CntRCLKforResPAE := 1; END IF; END IF; ELSE IF TotalLoc - RdPointer + WrPointer = ValueForPAE_Wr THEN IF ProgFlagMode = Asynchronous THEN PAENeg_zd <= (OTHERS => '1'); CopyPAE <= '1'; ELSE ResetPAE_1 := yes; CntRCLKforResPAE_1 := 1; END IF; END IF; END IF; Pointer; IF WrPointer >= RefPointer THEN IF (WrPointer > RefPointer AND WrPointer - RefPointer = ValueForPAF_Wr+1) OR (WrPointer = RefPointer AND WrPointer - RefPointer = ValueForPAF_Wr) THEN IF ProgFlagMode = Asynchronous THEN PAFNeg_zd <= (OTHERS => '0'); CopyPAF <= '0'; ELSE SetPAF := yes; CntWCLKforSetPAF := 2; END IF; END IF; ELSE IF TotalLoc - RefPointer + WrPointer = ValueForPAF_Wr THEN IF ProgFlagMode = Asynchronous THEN PAFNeg_zd <= (OTHERS => '0'); CopyPAF <= '0'; ELSE SetPAF_1 := yes; CntWCLKforSetPAF_1 := 2; END IF; END IF; END IF; END SetFlagsWrite; PROCEDURE SetFlagsRead (ValueForPAE_Rd : IN INTEGER; ValueForPAF_Rd : IN INTEGER) IS BEGIN IF WrPointer >= RdPointer THEN IF WrPointer - RdPointer = ValueForPAE_Rd THEN IF ProgFlagMode = Asynchronous THEN PAENeg_zd <= (OTHERS => '0'); CopyPAE <= '0'; ELSE SetPAE := yes; CntRCLKforSetPAE := 2; END IF; END IF; ELSE IF TotalLoc - RdPointer + WrPointer = ValueForPAE_Rd-1 THEN IF ProgFlagMode = Asynchronous THEN PAENeg_zd <= (OTHERS => '0'); CopyPAE <= '0'; ELSE SetPAE_1 := yes; CntRCLKforSetPAE_1 := 2; END IF; END IF; END IF; Pointer; IF WrPointer >= RefPointer THEN IF (WrPointer > RefPointer AND WrPointer - RefPointer = ValueForPAF_Rd) OR (WrPointer = RefPointer AND TotalLoc = ValueForPAF_Rd)THEN IF ProgFlagMode = Asynchronous THEN PAFNeg_zd <= (OTHERS => '1'); CopyPAF <= '1'; ELSE ResetPAF := yes; CntWCLKforResPAF := 1; END IF; END IF; ELSE IF TotalLoc - RefPointer + WrPointer = ValueForPAF_Rd-1 THEN IF ProgFlagMode = Asynchronous THEN PAFNeg_zd <= (OTHERS => '1'); CopyPAF <= '1'; ELSE ResetPAF_1 := yes; CntWCLKforResPAF_1 := 1; END IF; END IF; END IF; END SetFlagsRead; PROCEDURE CountCLK (Counter : INOUT INTEGER; Condition : INOUT yesno; SIGNAL CopyFlag : OUT std_ulogic; SIGNAL Flag: OUT std_logic_vector(1 TO 2); SIGNAL SkewFlag : IN std_ulogic; SIGNAL Value : IN std_ulogic; abd : IN yesno := no) IS BEGIN IF Counter = 0 THEN Flag <= (OTHERS => Value); CopyFlag <= Value; Condition := no; IF abd = yes THEN FlagAbd <= '1', '0' AFTER 1 ns; END IF; ELSE IF SkewFlag = '0' THEN Counter := Counter-1; END IF; END IF; END CountCLK; PROCEDURE ParallelLoad IS BEGIN IF ByteOffset = LSBEmptyOffset THEN IF Violation = '0' THEN TmpEmptyOffset := B"111" & DIn(15 DOWNTO 0); ELSE PaLdEmptyOk := no; END IF; ByteOffset := MSBEmptyOffset; ELSIF ByteOffset = MSBEmptyOffset THEN IF Violation = '0' THEN TmpEmptyOffset := TmpEmptyOffset AND (DIn(2 DOWNTO 0) & X"FFFF"); ELSE PaLdEmptyOk := no; END IF; PaLdEmptyEnd := yes; ByteOffset := LSBFullOffset; ELSIF ByteOffset = LSBFullOffset THEN IF Violation = '0' THEN TmpFullOffset := B"111" & DIn(15 DOWNTO 0); ELSE PaLdFullOk := no; END IF; ByteOffset := MSBFullOffset; ELSE IF Violation = '0' THEN TmpFullOffset := TmpFullOffset AND (DIn(2 DOWNTO 0) & X"FFFF"); ELSE PaLdFullOk := no; END IF; ByteOffset := LSBEmptyOffset; PaLdFullEnd := yes; END IF; END ParallelLoad; PROCEDURE SerialLoad IS BEGIN IF Violation = '0' THEN TmpOffset (CountForSerial) := FWFT ; ELSE SerLdOk := no; END IF; CountForSerial := CountForSerial + 1; IF CountForSerial = 38 THEN SerLdEnd := yes; CountForSerial := 0; END IF; END SerialLoad; PROCEDURE ParallelRead IS BEGIN TmpMemLocOE := TmpMemLocRead; SetFlagForOE; IF ReadByteOffset = LSBEmptyOffset AND EnReadOffs = yes THEN TmpOffsetRead := to_slv(EmptyOffset,19); TmpMemLocRead (15 DOWNTO 0) := TmpOffsetRead (15 DOWNTO 0); ReadByteOffset := MSBEmptyOffset; EnReadOffs := no; ELSIF ReadByteOffset = MSBEmptyOffset AND EnReadOffs = yes THEN TmpOffsetRead := to_slv(EmptyOffset,19); TmpMemLocRead (2 DOWNTO 0) := TmpOffsetRead (18 DOWNTO 16); ReadByteOffset := LSBFullOffset; EnReadOffs := no; ELSIF ReadByteOffset = LSBFullOffset AND EnReadOffs = yes THEN TmpOffsetRead := to_slv(FullOffset,19); TmpMemLocRead (15 DOWNTO 0) := TmpOffsetRead (15 DOWNTO 0); ReadByteOffset := MSBFullOffset; EnReadOffs := no; ELSIF ReadByteOffset = MSBFullOffset AND EnReadOffs = yes THEN TmpOffsetRead := to_slv(FullOffset,19); TmpMemLocRead (2 DOWNTO 0) := TmpOffsetRead (18 DOWNTO 16); ReadByteOffset := LSBEmptyOffset; EnReadOffs := no; END IF; END ParallelRead; BEGIN -------------------------------- -- Timing Check Section -------------------------------- IF (TimingChecksON) THEN -- WCLK pulse ( low&high ) width and period check - Syn VitalPeriodPulseCheck ( TestSignal => WCLK, TestSignalName => "WCLK", Period => tperiod_WCLK_SYN_EQ_1_posedge, PulseWidthHigh => tpw_WCLK_SYN_EQ_1_posedge, PulseWidthLow => tpw_WCLK_SYN_EQ_1_negedge, CheckEnabled => ASYWNeg='1', HeaderMsg => InstancePath & partID, PeriodData => PD_WCLK_SYN, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WCLK_SYN); -- WCLK pulse ( low&high ) width and period check - Asyn VitalPeriodPulseCheck ( TestSignal => WCLK, TestSignalName => "WCLK", Period => tperiod_WCLK_ASYN_EQ_1_posedge, PulseWidthHigh => tpw_WCLK_ASYN_EQ_1_posedge, PulseWidthLow => tpw_WCLK_ASYN_EQ_1_negedge, CheckEnabled => ASYWNeg='0', HeaderMsg => InstancePath & partID, PeriodData => PD_WCLK_ASYN, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WCLK_ASYN); -- RCLK pulse ( low&high ) width and period check - Syn VitalPeriodPulseCheck ( TestSignal => RCLK, TestSignalName => "RCLK", Period => tperiod_RCLK_SYN_EQ_1_posedge, PulseWidthHigh => tpw_RCLK_SYN_EQ_1_posedge, PulseWidthLow => tpw_RCLK_SYN_EQ_1_negedge, CheckEnabled => ASYRNeg='1', HeaderMsg => InstancePath & partID, PeriodData => PD_RCLK_SYN, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RCLK_SYN); -- RCLK pulse ( low&high ) width and period check - Asyn VitalPeriodPulseCheck ( TestSignal => RCLK, TestSignalName => "RCLK", Period => tperiod_RCLK_ASYN_EQ_1_posedge, PulseWidthHigh => tpw_RCLK_ASYN_EQ_1_posedge, PulseWidthLow => tpw_RCLK_ASYN_EQ_1_negedge, CheckEnabled => ASYRNeg='0', HeaderMsg => InstancePath & partID, PeriodData => PD_RCLK_ASYN, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RCLK_ASYN); -- SCLK pulse ( low&high ) width and period check VitalPeriodPulseCheck ( TestSignal => SCLK, TestSignalName => "SCLK", Period => tperiod_SCLK_posedge, PulseWidthHigh => tpw_SCLK_posedge, PulseWidthLow => tpw_SCLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_SCLK); -- MRSNeg pulse low width check VitalPeriodPulseCheck ( TestSignal => MRSNeg, TestSignalName => "MRSNeg", PulseWidthLow => tpw_MRSNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MRSNeg); -- PRSNeg pulse low width check VitalPeriodPulseCheck ( TestSignal => PRSNeg, TestSignalName => "PRSNeg", PulseWidthLow => tpw_PRSNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_PRSNeg); -- DIn/WCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "DIn", RefSignal => WCLK, RefSignalName => "WCLK", SetupHigh => tsetup_D0_WCLK, SetupLow => tsetup_D0_WCLK, HoldHigh => thold_D0_WCLK, HoldLow => thold_D0_WCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_DIn_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DIn_WCLK); -- FWFT/SCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => FWFT, TestSignalName => "FWFT", RefSignal => SCLK, RefSignalName => "SCLK", SetupHigh => tsetup_FWFT_SCLK, SetupLow => tsetup_FWFT_SCLK, HoldHigh => thold_FWFT_SCLK, HoldLow => thold_FWFT_SCLK, CheckEnabled => SENNeg='0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FWFT_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFT_SCLK); -- WENNeg/WCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_WENNeg_WCLK, HoldLow => thold_WENNeg_WCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_WCLK); -- RENNeg/RCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RCLK); -- RENNeg/RCLK setup time check VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, CheckEnabled => RTNeg='0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_RCLK_RT, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RCLK_RT); -- WENNeg/RCLK setup time check VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupHigh => tsetup_WENNeg_RCLK, CheckEnabled => RTNeg='0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_RCLK); -- MARK/RCLK setup time check VitalSetupHoldCheck ( TestSignal => MARK, TestSignalName => "MARK", RefSignal => RCLK, RefSignalName => "RCLK", SetupHigh => tsetup_MARK_RCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_MARK_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MARK_RCLK); -- SENNeg/SCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => SENNeg, TestSignalName => "SENNeg", RefSignal => SCLK, RefSignalName => "SCLK", SetupLow => tsetup_SENNeg_SCLK, HoldLow => thold_SENNeg_SCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_SCLK); -- RTNeg/RCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => RTNeg, TestSignalName => "RTNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RTNeg_RCLK, HoldLow => thold_RTNeg_RCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_RCLK); -- LDNeg/RCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_LDNeg_RCLK, HoldLow => thold_LDNeg_RCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_RCLK); -- LDNeg/WCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_LDNeg_WCLK, HoldLow => thold_LDNeg_WCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_WCLK); -- LDNeg/SCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => SCLK, RefSignalName => "SCLK", SetupLow => tsetup_LDNeg_SCLK, HoldLow => thold_LDNeg_SCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_SCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_SCLK); -- WCSNeg/WCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => WCSNeg, TestSignalName => "WCSNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_WCSNeg_WCLK, HoldLow => thold_WCSNeg_WCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WCSNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WCSNeg_WCLK); -- RCSNeg/RCLK setup/hold time check VitalSetupHoldCheck ( TestSignal => RCSNeg, TestSignalName => "RCSNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RCSNeg_RCLK, HoldLow => thold_RCSNeg_RCLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RCSNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RCSNeg_RCLK); -- RENNeg/MRSNeg setup time check VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_MRSNeg); -- WENNeg/MRSNeg setup time check VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_WENNeg_MRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_MRSNeg); -- FWFT/MRSNeg setup time check VitalSetupHoldCheck ( TestSignal => FWFT, TestSignalName => "FWFT", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupLow => tsetup_FWFT_MRSNeg, SetupHigh => tsetup_FWFT_MRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_FWFT_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFT_MRSNeg); -- LDNeg/MRSNeg setup time check VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupLow => tsetup_LDNeg_MRSNeg, SetupHigh => tsetup_LDNeg_MRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_MRSNeg); -- FSEL0/MRSNeg setup time check VitalSetupHoldCheck ( TestSignal => FSEL0, TestSignalName => "FSEL0", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_FSEL0_MRSNeg, SetupLow => tsetup_FSEL0_MRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_FSEL0_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FSEL0_MRSNeg); -- FSEL1/MRSNeg setup time check VitalSetupHoldCheck ( TestSignal => FSEL1, TestSignalName => "FSEL1", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_FSEL1_MRSNeg, SetupLow => tsetup_FSEL1_MRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_FSEL1_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FSEL1_MRSNeg); -- PFM/MRSNeg setup time check VitalSetupHoldCheck ( TestSignal => PFM, TestSignalName => "PFM", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_PFM_MRSNeg, SetupLow => tsetup_PFM_MRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_PFM_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_PFM_MRSNeg); -- RTNeg/MRSNeg setup time check VitalSetupHoldCheck ( TestSignal => RTNeg, TestSignalName => "RTNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_RTNeg_MRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_MRSNeg); -- SENNeg/MRSNeg setup time check VitalSetupHoldCheck ( TestSignal => SENNeg, TestSignalName => "SENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_SENNeg_MRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_MRSNeg); -- RENNeg/PRSNeg setup time check VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_PRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_PRSNeg); -- WENNeg/PRSNeg setup time check VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_WENNeg_PRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_PRSNeg); -- RTNeg/PRSNeg setup time check VitalSetupHoldCheck ( TestSignal => RTNeg, TestSignalName => "RTNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_RTNeg_PRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_PRSNeg); -- SENNeg/PRSNeg setup time check VitalSetupHoldCheck ( TestSignal => SENNeg, TestSignalName => "SENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_SENNeg_PRSNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_PRSNeg); -- RENNeg/MRSNeg hold time check VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", HoldHigh => thold_RENNeg_MRSNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_MRSNeg_hold, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_MRSNeg_hold); -- WENNeg/MRSNeg hold time check VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", HoldHigh => thold_WENNeg_MRSNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_MRSNeg_hold, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_MRSNeg_hold); -- FWFT/MRSNeg hold time check VitalSetupHoldCheck ( TestSignal => FWFT, TestSignalName => "FWFT", RefSignal => MRSNeg, RefSignalName => "MRSNeg", HoldLow => thold_FWFT_MRSNeg, HoldHigh => thold_FWFT_MRSNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FWFT_MRSNeg_hold, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFT_MRSNeg_hold); -- LDNeg/MRSNeg hold time check VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", HoldLow => thold_LDNeg_MRSNeg, HoldHigh => thold_LDNeg_MRSNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_MRSNeg_hold, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_MRSNeg_hold); -- RENNeg/PRSNeg hold time check VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", HoldHigh => thold_RENNeg_PRSNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_PRSNeg_hold, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_PRSNeg_hold); -- WENNeg/PRSNeg hold time check VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", HoldHigh => thold_WENNeg_PRSNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_PRSNeg_hold, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_PRSNeg_hold); END IF; --------------------------------------- -- Functional Section --------------------------------------- Violation := Pviol_WCLK_SYN OR Pviol_WCLK_ASYN OR Pviol_RCLK_SYN OR Pviol_RCLK_ASYN OR Pviol_SCLK OR Pviol_MRSNeg OR Pviol_PRSNeg OR Tviol_DIn_WCLK OR Tviol_FWFT_SCLK OR Tviol_WENNeg_WCLK OR Tviol_RENNeg_RCLK OR Tviol_RENNeg_RCLK_RT OR Tviol_SENNeg_SCLK OR Tviol_RTNeg_RCLK OR Tviol_LDNeg_RCLK OR Tviol_LDNeg_WCLK OR Tviol_RENNeg_MRSNeg OR Tviol_WENNeg_MRSNeg OR Tviol_FWFT_MRSNeg OR Tviol_LDNeg_MRSNeg OR Tviol_FSEL0_MRSNeg OR Tviol_FSEL1_MRSNeg OR Tviol_LDNeg_SCLK OR Tviol_PFM_MRSNeg OR Tviol_MARK_RCLK OR Tviol_RTNeg_MRSNeg OR Tviol_SENNeg_MRSNeg OR Tviol_RENNeg_PRSNeg OR Tviol_WENNeg_PRSNeg OR Tviol_RTNeg_PRSNeg OR Tviol_SENNeg_PRSNeg OR Tviol_RENNeg_MRSNeg_hold OR Tviol_WENNeg_MRSNeg_hold OR Tviol_FWFT_MRSNeg_hold OR Tviol_LDNeg_MRSNeg_hold OR Tviol_RENNeg_PRSNeg_hold OR Tviol_WENNeg_PRSNeg_hold; ASSERT Violation = '0' REPORT InstancePath & partID & " : signal values may be" & " incorrect due to timing violation(s)" SEVERITY Warning; --------------------------------------- --------------------------------------- -- Functional Section --------------------------------------- --------------------------------------- ----------------------- ----------------------- -- RESET ----------------------- ----------------------- IF falling_edge(MRSNeg) THEN Reset := yes; Enwrite := yes; PAFNeg_zd <= (OTHERS => '1'); CopyPAF <= '1'; PAENeg_zd <= (OTHERS => '0'); CopyPAE <= '0'; FlagForDelay <= '0'; FlagForOE <= '0'; FlagRCS <= '0'; flagRCSNeg <= '0'; WrPointer := 0; RdPointer := 0; PaLdEmptyOk := yes; PaLdFullOk := yes; SerLdOk := yes; EnReadOffs := yes; ByteOffset := LSBEmptyOffset; ReadByteOffset := LSBEmptyOffset; TmpMemLocOE := (OTHERS => '0'); TmpMemLocRead := (OTHERS => '0'); Retransmit := done; CountForSerial := 0; ResetOR := no; ResetEF := no; SetOR := no; ResetFF := no; SetPAF := no; SetPAFabd := no; SetPAF_1 := no; ResetPAF := no; ResetPAFabd := no; ResetPAF_1 := no; SetIR := no; ResetPAE := no; ResetPAEabd := no; ResetPAE_1 := no; SetPAE_1 := no; SetPAE := no; SetPAEabd := no; PaLdEmptyEnd:= no; PaLdFullEnd := no; FirstWord := no; EnFirstWord := no; IF LDNeg = '1' THEN ProgramMode := Serial; IF FSEL1 = '0' AND FSEL0 = '0' THEN FullOffset := 1023; EmptyOffset := 1023; ELSIF FSEL1 = '1' AND FSEL0 = '0' THEN FullOffset := 31; EmptyOffset := 31; ELSIF FSEL1 = '0' AND FSEL0 = '1' THEN FullOffset := 15; EmptyOffset := 15; ELSIF FSEL1 = '1' AND FSEL0 = '1' THEN FullOffset := 7; EmptyOffset := 7; END IF; ELSIF LDNeg = '0' THEN ProgramMode := Parallel; IF FSEL1 = '0' AND FSEL0 = '0' THEN FullOffset := 127; EmptyOffset := 127; ELSIF FSEL1 = '1' AND FSEL0 = '0' THEN FullOffset := 511; EmptyOffset := 511; ELSIF FSEL1 = '0' AND FSEL0 = '1' THEN FullOffset := 255; EmptyOffset := 255; ELSIF FSEL1 = '1' AND FSEL0 = '1' THEN FullOffset := 63; EmptyOffset := 63; END IF; END IF; ValueForPAE := EmptyOffset; ValueForPAF := TotalLoc - FullOffset; IF PFM = '0' then ProgFlagMode := Asynchronous; ELSIF PFM = '1' then ProgFlagMode := Synchronous; END IF; IF FWFT = '0' then Mode := IDTStandard; EFNeg_zd <= (OTHERS => '0'); FFNeg_zd <= (OTHERS => '1'); CopyEFNeg <= '0'; CopyFFNeg <= '1'; ELSIF FWFT = '1' then Mode := FWFTMode; EFNeg_zd <= (OTHERS => '1'); FFNeg_zd <= (OTHERS => '0'); CopyEFNeg <= '1'; CopyFFNeg <= '0'; END IF; IF ASYRNeg = '0' then IF FWFT = '1' then ASSERT FALSE REPORT "FIFO must operate in IDT Standard mode " SEVERITY Warning; Mode := IDTStandard; END IF; ReadOperation := Asynchronous; TimeForFlag := tpd_RCLK_Q0_ASYN_EQ_1(tr01); TimeForFlag_1 := tpd_OENeg_Q0_ASYN_EQ_1(tr01); ELSIF ASYRNeg = '1' then ReadOperation := Synchronous; TimeForFlag := tpd_RCLK_Q0_SYN_EQ_1(tr01); TimeForFlag_1 := tpd_OENeg_Q0_SYN_EQ_1(tr01); END IF; IF ASYWNeg = '0' then WriteOperation := Asynchronous; ELSIF ASYWNeg = '1' then WriteOperation := Synchronous; END IF; IF OENeg = '0' then QOut_zd <= (OTHERS => '0'); ELSIF OENeg = '1' then QOut_zd <= (OTHERS => 'Z'); END IF; ELSIF rising_edge(MRSNeg) THEN Reset := no; END IF; ----------------------- ----------------------- -- PRESET ----------------------- ----------------------- IF falling_edge(PRSNeg) THEN Reset := yes; PAFNeg_zd <= (OTHERS => '1'); CopyPAF <= '1'; PAENeg_zd <= (OTHERS => '0'); CopyPAE <= '0'; FlagForDelay <= '0'; FlagRCS <= '0'; flagRCSNeg <= '0'; WrPointer := 0; RdPointer := 0; PaLdEmptyOk := yes; PaLdFullOk := yes; SerLdOk := yes; EnReadOffs := yes; ByteOffset := LSBEmptyOffset; ReadByteOffset := LSBEmptyOffset; TmpMemLocOE := (OTHERS => '0'); TmpMemLocRead := (OTHERS => '0'); Retransmit := done; CountForSerial := 0; ResetOR := no; ResetEF := no; SetOR := no; ResetFF := no; SetPAF := no; SetPAFabd := no; SetPAF_1 := no; ResetPAF := no; ResetPAFabd := no; ResetPAF_1 := no; SetIR := no; ResetPAE := no; ResetPAEabd := no; ResetPAE_1 := no; SetPAE_1 := no; SetPAE := no; SetPAEabd := no; PaLdEmptyEnd:= no; PaLdFullEnd := no; FirstWord := no; EnFirstWord := no; IF Mode = IDTStandard then EFNeg_zd <= (OTHERS => '0'); FFNeg_zd <= (OTHERS => '1'); CopyEFNeg <= '0'; CopyFFNeg <= '1'; ELSE EFNeg_zd <= (OTHERS => '1'); FFNeg_zd <= (OTHERS => '0'); CopyEFNeg <= '1'; CopyFFNeg <= '0'; END IF; IF OENeg = '0' then QOut_zd <= (OTHERS => '0'); ELSIF OENeg = '1' then QOut_zd <= (OTHERS => 'Z'); END IF; ELSIF rising_edge(PRSNeg) THEN Reset := no; END IF; ----------------------- ----------------------- -- SKEW ----------------------- ----------------------- IF reset = no THEN IF rising_edge (RCLK) THEN flagRCLKskew2 <= '1','0' after tSKEW2; flagRCLKskew1 <= '1','0' after tSKEW1; flagRCS <= '0'; flagRCSNeg <= '0'; END IF; IF rising_edge (WCLK) THEN flagWCLKskew2 <= '1','0' after tSKEW2; flagWCLKskew1 <= '1','0' after tSKEW1; END IF; IF rising_edge (CopyEFNeg) THEN flagRPE <= '1','0' after tRPE; END IF; IF falling_edge (RCSNeg) THEN flagRCS <= '1'; END IF; IF rising_edge (RCSNeg) THEN flagRCSNeg <= '1'; END IF; END IF; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- WRITE -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- IF Reset = no THEN IF rising_edge(WCLK) THEN IF Mode = IDTStandard THEN IF (WENNeg = '0' AND CopyFFNeg = '1' AND Enwrite = yes AND LDNeg = '1' AND WCSNeg = '0') THEN IF Violation = '0' THEN MemDataLow(WrPointer) := to_nat(DIn(17 downto 0)); MemDataHigh(WrPointer) := to_nat(DIn(35 downto 18)); ELSE MemDataLow(WrPointer) := -1; MemDataHigh(WrPointer) := -1; END IF; IF WrPointer = TotalLoc THEN WrPointer := 0; ELSE WrPointer := WrPointer + 1; END IF; IF ReadOperation = Synchronous THEN IF CopyEFNeg = '0' THEN IF ResetEF = no THEN ResetEF := yes; CntRCLKforResEF := 1; END IF; END IF; ELSE EFNeg_zd <= (OTHERS => '1'); CopyEFNeg <= '1'; END IF; Pointer; IF WrPointer = RefPointer THEN FFNeg_zd <= (OTHERS => '0'); CopyFFNeg <= '0'; END IF; SetFlagsWrite( ValueForPAE_Wr => ValueForPAE, ValueForPAF_Wr => ValueForPAF); END IF; ELSE IF (WENNeg = '0' AND CopyFFNeg = '0' AND Enwrite = yes AND LDNeg = '1' AND WCSNeg = '0') THEN IF Violation = '0' THEN MemDataLow(WrPointer) := to_nat(DIn(17 downto 0)); MemDataHigh(WrPointer) := to_nat(DIn(35 downto 18)); ELSE MemDataLow(WrPointer) := -1; MemDataHigh(WrPointer) := -1; END IF; IF WrPointer = TotalLoc THEN WrPointer := 0; ELSE WrPointer := WrPointer + 1; END IF; Pointer; IF WrPointer = RefPointer THEN FFNeg_zd <= (OTHERS => '1'); CopyFFNeg <= '1'; END IF; IF CopyEFNeg = '1' THEN IF EnFirstWord = no THEN EnFirstWord := yes; CntRCLKforFirstWord := 2; END IF; END IF; SetFlagsWrite( ValueForPAE_Wr => ValueForPAE, ValueForPAF_Wr => ValueForPAF); END IF; END IF; --Counting Write Cycles IF SetPAF = yes THEN CountCLK (Counter => CntWCLKforSetPAF, Condition => SetPAF, CopyFlag => CopyPAF, Flag => PAFNeg_zd, SkewFlag => Const0, Value => Const0); END IF; IF SetPAFabd = yes THEN CountCLK (Counter => CntWCLKforSetPAF, Condition => SetPAF, CopyFlag => CopyPAF, Flag => PAFNeg_zd, SkewFlag => Const0, Value => Const0, abd => yes); END IF; IF SetPAF_1 = yes THEN CountCLK (Counter => CntWCLKforSetPAF_1, Condition => SetPAF_1, CopyFlag => CopyPAF, Flag => PAFNeg_zd, SkewFlag => Const0, Value => Const0); END IF; IF ResetPAF = yes THEN CountCLK (Counter => CntWCLKforResPAF, Condition => ResetPAF, CopyFlag => CopyPAF, Flag => PAFNeg_zd, SkewFlag => FlagRCLKskew2, Value => Const1); END IF; IF ResetPAFabd = yes THEN CountCLK (Counter => CntWCLKforResPAF, Condition => ResetPAFabd, CopyFlag => CopyPAF, Flag => PAFNeg_zd, SkewFlag => Const0, Value => Const1, abd => yes); END IF; IF ResetPAF_1 = yes THEN CountCLK (Counter => CntWCLKforResPAF_1, Condition => ResetPAF_1, CopyFlag => CopyPAF, Flag => PAFNeg_zd, SkewFlag => FlagRCLKskew2, Value => Const1); END IF; IF ResetFF = yes THEN CountCLK (Counter => CntWCLKforResFF, Condition => ResetFF, CopyFlag => CopyFFNeg, Flag => FFNeg_zd, SkewFlag => FlagRCLKskew1, Value => Const1); END IF; IF SetIR = yes THEN CountCLK (Counter => CntWCLKforSetIR, Condition => SetIR, CopyFlag => CopyFFNeg, Flag => FFNeg_zd, SkewFlag => FlagRCLKskew1, Value => Const0); END IF; --Parallel Loading Offset Registers IF ProgramMode = Parallel AND Enwrite = yes THEN IF (WENNeg = '0' AND RENNeg = '1' AND SENNeg = '1' AND LDNeg = '0') THEN ParallelLoad; IF PaLdEmptyEnd = yes THEN PaLdEmptyEnd := no; IF PaLdEmptyOk = yes THEN EmptyOffset := to_nat (TmpEmptyOffset); ValueForPAE := EmptyOffset; SetFlags( ValueForPAE => ValueForPAE, ValueForPAF => ValueForPAF); END IF; PaLdEmptyOk := yes; END IF; IF PaLdFullEnd = yes THEN PaLdFullEnd := no; IF PaLdFullOk = yes THEN FullOffset := to_nat (TmpFullOffset); ValueForPAF := TotalLoc - FullOffset; SetFlags( ValueForPAE => ValueForPAE, ValueForPAF => ValueForPAF); END IF; PaLdFullOk := yes; END IF; END IF; END IF; END IF; END IF; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- READ -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- IF Reset = no THEN IF (rising_edge(RCLK) AND ReadOperation = Synchronous) OR (rising_edge(RCLK) AND ReadOperation = Asynchronous AND flagRPE = '0') THEN IF Mode = IDTStandard THEN IF MARK = '1' THEN IF Retransmit = done AND (abs(WrPointer - RdPointer) >= 128) AND OENeg = '0' AND RCSNeg = '0' THEN MarkedPointer := OldRdPointer; Retransmit := marked; ELSIF (Retransmit = marked OR Retransmit = hold) AND RENNeg = '1' AND WENNeg = '1' AND RTNeg = '0' THEN Retransmit := initiated; EFNeg_zd <= (OTHERS => '0'); CopyEFNeg <= '0'; RdPointer := MarkedPointer; ELSIF Retransmit = initiated THEN FirstWord := yes; Retransmit := hold; EFNeg_zd <= (OTHERS => '1'); CopyEFNeg <= '1'; SetFlagsRt (ValueForPAE => ValueForPAE, ValueForPAF => ValueForPAF); END IF; END IF; IF (RENNeg = '0' AND CopyEFNeg = '1' AND LDNeg = '1' AND RCSNeg = '0') THEN TmpMemLocOE := TmpMemLocRead; SetFlagForOE; IF MemDataLow(RdPointer) = -1 THEN TmpMemLocRead := (OTHERS=> 'X' ); ELSE TmpMemLocRead_L := to_slv(MemDataLow(RdPointer),18); TmpMemLocRead_H := to_slv(MemDataHigh(RdPointer),18); TmpMemLocRead := TmpMemLocRead_H & TmpMemLocRead_L; END IF; OldRdPointer := RdPointer; IF RdPointer = TotalLoc THEN RdPointer := 0; ELSE RdPointer := RdPointer + 1; END IF; IF CopyFFNeg = '0' THEN IF ReadOperation = Synchronous THEN IF ResetFF = no THEN ResetFF := yes; CntWCLKforResFF := 1; END IF; ELSE FFNeg_zd <= (OTHERS => '1'); CopyFFNeg <= '1'; END IF; END IF; IF WrPointer = RdPointer THEN EFNeg_zd <= (OTHERS => '0'); CopyEFNeg <= '0'; END IF; SetFlagsRead( ValueForPAE_Rd => ValueForPAE, ValueForPAF_Rd => ValueForPAF); END IF; ELSE IF MARK = '1' THEN IF Retransmit = done AND (abs(WrPointer - RdPointer) >= 128) AND OENeg = '0' AND RCSNeg = '0' THEN MarkedPointer := OldRdPointer; Retransmit := marked; ELSIF (Retransmit = marked OR Retransmit = hold) AND RENNeg = '1' AND WENNeg = '1' AND RTNeg = '0' THEN Retransmit := initiated; EFNeg_zd <= (OTHERS => '1'); CopyEFNeg <= '1'; RdPointer := MarkedPointer; ELSIF Retransmit = initiated THEN Retransmit := hold; FirstWord := yes; EFNeg_zd <= (OTHERS => '0'); CopyEFNeg <= '0'; END IF; END IF; IF (RENNeg = '0' AND ResetOR = yes AND LDNeg = '1' AND RTNeg = '1') THEN ResetOR := no; EFNeg_zd <= (OTHERS=> '1'); CopyEFNeg <= '1'; ELSE IF ((RENNeg = '0' AND CopyEFNeg = '0') OR FirstWord = yes) AND LDNeg = '1' AND RCSNeg = '0' THEN TmpMemLocOE := TmpMemLocRead; SetFlagForOE; IF MemDataLow(RdPointer) = -1 THEN TmpMemLocRead := (OTHERS=> 'X' ); ELSE TmpMemLocRead_L := to_slv(MemDataLow(RdPointer),18); TmpMemLocRead_H := to_slv(MemDataHigh(RdPointer),18); TmpMemLocRead := TmpMemLocRead_H & TmpMemLocRead_L; END IF; OldRdPointer := RdPointer; IF RdPointer = TotalLoc THEN RdPointer := 0; ELSE RdPointer := RdPointer + 1; END IF; IF CopyFFNeg = '1' THEN IF ReadOperation = Synchronous THEN IF SetIR = no THEN SetIR := yes; CntWCLKforSetIR := 1; END IF; ELSE FFNeg_zd <= (OTHERS => '0'); CopyFFNeg <= '0'; END IF; END IF; IF WrPointer = RdPointer THEN ResetOR := yes; END IF; IF (FirstWord = no) THEN SetFlagsRead( ValueForPAE_Rd => ValueForPAE, ValueForPAF_Rd => ValueForPAF); END IF; FirstWord := no; END IF; END IF; END IF; --Reading Offset Registers IF (WENNeg = '1' AND RENNeg = '0' AND SENNeg = '1' AND LDNeg = '0') THEN ParallelRead; END IF; --Disable Reading Offset Registers IF (RENNeg = '1') THEN EnReadOffs := yes; END IF; --Counting Read Cycles IF ResetEF = yes THEN CountCLK (Counter => CntRCLKforResEF, Condition => ResetEF, CopyFlag => CopyEFNeg, Flag => EFNeg_zd, SkewFlag => FlagWCLKskew1, Value => Const1); END IF; IF EnFirstWord = yes THEN IF CntRCLKforFirstWord = 0 THEN EnFirstWord := no; TmpMemLocOE := TmpMemLocRead; SetFlagForOE; IF MemDataLow(RdPointer) = -1 THEN TmpMemLocRead := (OTHERS=> 'X' ); ELSE TmpMemLocRead_L := to_slv(MemDataLow(RdPointer),18); TmpMemLocRead_H := to_slv(MemDataHigh(RdPointer),18); TmpMemLocRead := TmpMemLocRead_H & TmpMemLocRead_L; END IF; OldRdPointer := RdPointer; IF RdPointer = TotalLoc THEN RdPointer := 0; ELSE RdPointer := RdPointer + 1; END IF; EFNeg_zd <= (OTHERS=> '0' ); CopyEFNeg <= '0'; ELSE IF FlagWCLKskew1 = '0' THEN CntRCLKforFirstWord := CntRCLKforFirstWord-1; END IF; END IF; END IF; IF ResetPAE = yes THEN CountCLK (Counter => CntRCLKforResPAE, Condition => ResetPAE, CopyFlag => CopyPAE, Flag => PAENeg_zd, SkewFlag => FlagWCLKskew2, Value => Const1); END IF; IF ResetPAEabd = yes THEN CountCLK (Counter => CntRCLKforResPAE, Condition => ResetPAEabd, CopyFlag => CopyPAE, Flag => PAENeg_zd, SkewFlag => Const0, Value => Const1, abd => yes); END IF; IF ResetPAE_1 = yes THEN CountCLK (Counter => CntRCLKforResPAE_1, Condition => ResetPAE_1, CopyFlag => CopyPAE, Flag => PAENeg_zd, SkewFlag => FlagWCLKskew2, Value => Const1); END IF; IF SetPAE = yes THEN CountCLK (Counter => CntRCLKforSetPAE, Condition => SetPAE, CopyFlag => CopyPAE, Flag => PAENeg_zd, SkewFlag => Const0, Value => Const0); END IF; IF SetPAEabd = yes THEN CountCLK (Counter => CntRCLKforSetPAE, Condition => SetPAE, CopyFlag => CopyPAE, Flag => PAENeg_zd, SkewFlag => Const0, Value => Const0, abd => yes); END IF; IF SetPAE_1 = yes THEN CountCLK (Counter => CntRCLKforSetPAE_1, Condition => SetPAE_1, CopyFlag => CopyPAE, Flag => PAENeg_zd, SkewFlag => Const0, Value => Const0); END IF; END IF; END IF; ----------------------------------------------- ----------------------------------------------- -- Serial Loading Offset Registers ----------------------------------------------- ----------------------------------------------- IF Reset = no THEN IF rising_edge(SCLK) AND Enwrite = yes THEN IF ProgramMode = Serial THEN IF (WENNeg = '1' AND RENNeg = '1' AND SENNeg = '0' AND LDNeg = '0') THEN IF SerLdEnd = no THEN SerialLoad; END IF; IF SerLdEnd = yes THEN SerLdEnd := no; IF SerLdOk = yes THEN TmpEmptyOffset := TmpOffset(18 downto 0); EmptyOffset := to_nat (TmpEmptyOffset); TmpFullOffset := TmpOffset(37 downto 19); FullOffset := to_nat (TmpFullOffset); ValueForPAE := EmptyOffset; ValueForPAF := TotalLoc - FullOffset; SetFlags( ValueForPAE => ValueForPAE, ValueForPAF => ValueForPAF); END IF; END IF; END IF; END IF; END IF; END IF; ------------------------------ ------------------------------ -- Deasert Retransmit Mode ------------------------------ ------------------------------ IF Reset = no THEN IF falling_edge (RCLK) AND MARK = '0' AND (Retransmit = marked OR Retransmit = hold OR Retransmit = initiated) THEN Retransmit := done; SetFlagsRt (ValueForPAE => ValueForPAE, ValueForPAF => ValueForPAF); END IF; END IF; -------------------------- -------------------------- -- Output Data Control -------------------------- -------------------------- FromOE := false; FromRCLK := true; IF falling_edge (OENeg) THEN time_OE := OENeg'last_event + TimeForFlag_1; END IF; IF rising_edge (RCLK) THEN time_RCLK := RCLK'last_event + TimeForFlag; END IF; IF rising_edge (RCLK) AND OENeg = '0' AND (RCSNeg = '0' OR LDNeg = '0') THEN QOut_zd <= TmpMemLocRead; ELSIF rising_edge (RCLK) AND RCSNeg = '1' AND LDNeg = '1' THEN QOut_zd <= (OTHERS=> 'Z' ); END IF; IF rising_edge (OENeg) THEN TmpMemLocOE := TmpMemLocRead; QOut_zd <= (OTHERS=> 'Z'); FromRCLK := false; FromOE := true; ELSIF falling_edge (OENeg) AND RCSNeg = '0' AND (flagRCS = '0' OR flagRCSNeg = '1') THEN IF FlagForOE = '1' THEN QOut_zd <= TmpMemLocOE, TmpMemLocRead AFTER 0.5 ns; IF time_OE >= time_RCLK THEN FromOE := true; FromRCLK := false; ELSE FlagForDelay <= '1','0' after 1 ns; END IF; ELSE QOut_zd <= TmpMemLocRead; FromOE := true; FromRCLK := false; END IF; END IF; END PROCESS; --------------------------------------------------------------------- -- Path delay section -- --------------------------------------------------------------------- FlagPathDelay_Gen: FOR i IN 1 TO 2 GENERATE PROCESS (EFNeg_zd(i)) VARIABLE EFNeg_GlitchData : VitalGlitchDataArrayType(1 TO 2); BEGIN VitalPathDelay01 (OutSignal => EFNeg(i), OutSignalName => "EFNeg", OutTemp => EFNeg_zd(i), GlitchData => EFNeg_GlitchData(i), Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_EF1Neg, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_EF1Neg, PathCondition => true), 2 => (InputChangeTime => WCLK'last_event, PathDelay => tpd_WCLK_EF1Neg, PathCondition => ASYRNeg = '0' AND CopyEFNeg='1'), 3 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_EF1Neg_ASYN_EQ_1, PathCondition => ASYRNeg = '0' AND CopyEFNeg='0'), 4 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_EF1Neg_SYN_EQ_1, PathCondition => ASYRNeg = '1'))); END PROCESS; PROCESS (FFNeg_zd(i)) VARIABLE FFNeg_GlitchData : VitalGlitchDataArrayType(1 TO 2); BEGIN VitalPathDelay01 (OutSignal => FFNeg(i), OutSignalName => "FFNeg", OutTemp => FFNeg_zd(i), GlitchData => FFNeg_GlitchData(i), Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_FF1Neg, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_FF1Neg, PathCondition => true), 2 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_FF1Neg, PathCondition => ASYWNeg = '0' AND CopyFFNeg='1'), 3 => (InputChangeTime => WCLK'last_event, PathDelay => tpd_WCLK_FF1Neg_ASYN_EQ_1, PathCondition => ASYWNeg = '0' AND CopyFFNeg='0'), 4 => (InputChangeTime => WCLK'last_event, PathDelay => tpd_WCLK_FF1Neg_SYN_EQ_1, PathCondition => ASYWNeg = '1' ))); END PROCESS; PROCESS (PAENeg_zd(i)) VARIABLE PAENeg_GlitchData : VitalGlitchDataArrayType(1 TO 2); BEGIN VitalPathDelay01 (OutSignal => PAENeg(i), OutSignalName => "PAENeg", OutTemp => PAENeg_zd(i), GlitchData => PAENeg_GlitchData(i), Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_PAE1Neg, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_PAE1Neg, PathCondition => true), 2 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_PAE1Neg_ASYN_EQ_1, PathCondition => ProgFlagMode = Asynchronous AND CopyPAE='0' AND FlagAbd = '0'), 3 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_PAE1Neg_SYN_EQ_1, PathCondition => ProgFlagMode = Synchronous OR FlagAbd = '1'), 4 => (InputChangeTime => WCLK'last_event, PathDelay => tpd_WCLK_PAE1Neg, PathCondition => ProgFlagMode = Asynchronous AND CopyPAE='1'))); END PROCESS; PROCESS (PAFNeg_zd(i)) VARIABLE PAFNeg_GlitchData : VitalGlitchDataArrayType(1 TO 2); BEGIN VitalPathDelay01 (OutSignal => PAFNeg(i), OutSignalName => "PAFNeg", OutTemp => PAFNeg_zd(i), GlitchData => PAFNeg_GlitchData(i), Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_PAF1Neg, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_PAF1Neg, PathCondition => true), 2 => (InputChangeTime => WCLK'last_event, PathDelay => tpd_WCLK_PAF1Neg_ASYN_EQ_1, PathCondition => ProgFlagMode = Asynchronous AND CopyPAF='0' AND FlagAbd = '0'), 3 => (InputChangeTime => WCLK'last_event, PathDelay => tpd_WCLK_PAF1Neg_SYN_EQ_1, PathCondition => ProgFlagMode = Synchronous OR FlagAbd = '1'), 4 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_PAF1Neg, PathCondition => ProgFlagMode = Asynchronous AND CopyPAF='1'))); END PROCESS; END GENERATE FlagPathDelay_Gen; QOutPathDelay_Gen: FOR i IN DataWidth-1 DOWNTO 0 GENERATE PROCESS (QOut_zd(i)) VARIABLE QOut_GlitchData : VitalGlitchDataArrayType(DataWidth-1 Downto 0); BEGIN VitalPathDelay01Z (OutSignal => QOut(i), OutSignalName => "QOut", OutTemp => QOut_zd(i), GlitchData => QOut_GlitchData(i), Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_Q0, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_Q0, PathCondition => true), 2 => (InputChangeTime => OENeg'last_event, PathDelay => tpd_OENeg_Q0_SYN_EQ_1, PathCondition => (FromOE OR FlagForDelay = '1')AND ASYRNeg = '1'), 3 => (InputChangeTime => OENeg'last_event, PathDelay => tpd_OENeg_Q0_ASYN_EQ_1, PathCondition => (FromOE OR FlagForDelay = '1')AND ASYRNeg = '0'), 4 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_Q0_SYN_EQ_1, PathCondition => FromRCLK AND ASYRNeg = '1'), 5 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_Q0_ASYN_EQ_1, PathCondition => FromRCLK AND ASYRNeg = '0' ))); END PROCESS; END GENERATE QOutPathDelay_Gen; END BLOCK Main; END vhdl_behavioral;