-------------------------------------------------------------------------------- -- File name : idt723651.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998 Integrated Device Technology; http://www.idt.com/ -- Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT -- and supported by Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no -- warranty with respect to the information contained herein. IDT DISCLAIMS -- AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE -- ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN -- NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN -- CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, -- CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR -- APPLICATION OF THE VHDL model. Further, IDT reserves the right to make -- changes without notice to any product herein to improve reliability, -- function, or design. IDT does not convey any license under patent rights -- or any other intellectual property rights, including those of third parties. -- IDT is not obligated to provide maintenance or support for the licensed VHDL -- model. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V1.0 A. Poliakov 98 APR 30 initial release -- V1.1 Ilya Shenfinkel 99 MAR 15 corrected FIFO1_Read_Data process -- V1.2 | R. Munden | 02 MAY 19 | licensing changed to GPL ------------------------------------------------------------------------------- -- -- PART DESCRIPTION : -- -- Library: FIFO -- Technology: CMOS -- Part: IDT723651 -- -- Descripton: SyncFIFO 2048x36 -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.vital_primitives.ALL; USE ieee.vital_timing.ALL; LIBRARY fmf; USE fmf.ff_package.ALL; USE fmf.gen_utils.ALL; USE fmf.conversions.to_nat; USE fmf.conversions.to_slv; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -- -------------------------------------------------------------------------------- ENTITY IDT723651 IS GENERIC ( ---------------------------------------------------------------------------- -- VITAL generics ---------------------------------------------------------------------------- -- tipd delays: interconnect path delays -- (there must be one generic for each input pin) tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; tipd_A13 : VitalDelayType01 := VitalZeroDelay01; tipd_A14 : VitalDelayType01 := VitalZeroDelay01; tipd_A15 : VitalDelayType01 := VitalZeroDelay01; tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_A18 : VitalDelayType01 := VitalZeroDelay01; tipd_A19 : VitalDelayType01 := VitalZeroDelay01; tipd_A20 : VitalDelayType01 := VitalZeroDelay01; tipd_A21 : VitalDelayType01 := VitalZeroDelay01; tipd_A22 : VitalDelayType01 := VitalZeroDelay01; tipd_A23 : VitalDelayType01 := VitalZeroDelay01; tipd_A24 : VitalDelayType01 := VitalZeroDelay01; tipd_A25 : VitalDelayType01 := VitalZeroDelay01; tipd_A26 : VitalDelayType01 := VitalZeroDelay01; tipd_A27 : VitalDelayType01 := VitalZeroDelay01; tipd_A28 : VitalDelayType01 := VitalZeroDelay01; tipd_A29 : VitalDelayType01 := VitalZeroDelay01; tipd_A30 : VitalDelayType01 := VitalZeroDelay01; tipd_A31 : VitalDelayType01 := VitalZeroDelay01; tipd_A32 : VitalDelayType01 := VitalZeroDelay01; tipd_A33 : VitalDelayType01 := VitalZeroDelay01; tipd_A34 : VitalDelayType01 := VitalZeroDelay01; tipd_A35 : VitalDelayType01 := VitalZeroDelay01; tipd_B0 : VitalDelayType01 := VitalZeroDelay01; tipd_B1 : VitalDelayType01 := VitalZeroDelay01; tipd_B2 : VitalDelayType01 := VitalZeroDelay01; tipd_B3 : VitalDelayType01 := VitalZeroDelay01; tipd_B4 : VitalDelayType01 := VitalZeroDelay01; tipd_B5 : VitalDelayType01 := VitalZeroDelay01; tipd_B6 : VitalDelayType01 := VitalZeroDelay01; tipd_B7 : VitalDelayType01 := VitalZeroDelay01; tipd_B8 : VitalDelayType01 := VitalZeroDelay01; tipd_B9 : VitalDelayType01 := VitalZeroDelay01; tipd_B10 : VitalDelayType01 := VitalZeroDelay01; tipd_B11 : VitalDelayType01 := VitalZeroDelay01; tipd_B12 : VitalDelayType01 := VitalZeroDelay01; tipd_B13 : VitalDelayType01 := VitalZeroDelay01; tipd_B14 : VitalDelayType01 := VitalZeroDelay01; tipd_B15 : VitalDelayType01 := VitalZeroDelay01; tipd_B16 : VitalDelayType01 := VitalZeroDelay01; tipd_B17 : VitalDelayType01 := VitalZeroDelay01; tipd_B18 : VitalDelayType01 := VitalZeroDelay01; tipd_B19 : VitalDelayType01 := VitalZeroDelay01; tipd_B20 : VitalDelayType01 := VitalZeroDelay01; tipd_B21 : VitalDelayType01 := VitalZeroDelay01; tipd_B22 : VitalDelayType01 := VitalZeroDelay01; tipd_B23 : VitalDelayType01 := VitalZeroDelay01; tipd_B24 : VitalDelayType01 := VitalZeroDelay01; tipd_B25 : VitalDelayType01 := VitalZeroDelay01; tipd_B26 : VitalDelayType01 := VitalZeroDelay01; tipd_B27 : VitalDelayType01 := VitalZeroDelay01; tipd_B28 : VitalDelayType01 := VitalZeroDelay01; tipd_B29 : VitalDelayType01 := VitalZeroDelay01; tipd_B30 : VitalDelayType01 := VitalZeroDelay01; tipd_B31 : VitalDelayType01 := VitalZeroDelay01; tipd_B32 : VitalDelayType01 := VitalZeroDelay01; tipd_B33 : VitalDelayType01 := VitalZeroDelay01; tipd_B34 : VitalDelayType01 := VitalZeroDelay01; tipd_B35 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKA : VitalDelayType01 := VitalZeroDelay01; tipd_CLKB : VitalDelayType01 := VitalZeroDelay01; tipd_CSANeg : VitalDelayType01 := VitalZeroDelay01; tipd_CSBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ENA : VitalDelayType01 := VitalZeroDelay01; tipd_ENB : VitalDelayType01 := VitalZeroDelay01; tipd_FS0SD : VitalDelayType01 := VitalZeroDelay01; tipd_FS1SEN : VitalDelayType01 := VitalZeroDelay01; tipd_MBA : VitalDelayType01 := VitalZeroDelay01; tipd_MBB : VitalDelayType01 := VitalZeroDelay01; tipd_RSTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RTM : VitalDelayType01 := VitalZeroDelay01; tipd_RFM : VitalDelayType01 := VitalZeroDelay01; tipd_WRA : VitalDelayType01 := VitalZeroDelay01; tipd_WRB : VitalDelayType01 := VitalZeroDelay01; ------------------------------------------------------------ -- tpd delays: propagation delays -- tA tpd_CLKB_B0 : VitalDelayType01 := UnitDelay01; -- tPIR tpd_CLKA_IR : VitalDelayType01 := UnitDelay01; -- tPOR tpd_CLKB_ORB : VitalDelayType01 := UnitDelay01; -- tPAE tpd_CLKB_AENeg : VitalDelayType01 := UnitDelay01; -- tPAF tpd_CLKA_AFNeg : VitalDelayType01 := UnitDelay01; -- tPMF tpd_CLKA_MBF1Neg : VitalDelayType01 := UnitDelay01; -- tPMR tpd_CLKA_B0 : VitalDelayType01 := UnitDelay01; -- tMDV tpd_MBB_B0 : VitalDelayType01 := UnitDelay01; -- tRSF tpd_RSTNeg_AENeg : VitalDelayType01 := UnitDelay01; -- tEN/tDIS tpd_CSANeg_A0 : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths -- tCLK tperiod_CLKA_posedge : VitalDelayType := UnitDelay; -- tCLKH -- tCLKL tpw_CLKA_posedge : VitalDelayType := UnitDelay; tpw_CLKA_negedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS tsetup_A0_CLKA : VitalDelayType := UnitDelay; -- tENS1 tsetup_ENA_CLKA : VitalDelayType := UnitDelay; -- tENS2 tsetup_CSANeg_CLKA : VitalDelayType := UnitDelay; -- tRMS tsetup_RTM_CLKB : VitalDelayType := UnitDelay; -- tRSTS tsetup_RSTNeg_CLKA : VitalDelayType := UnitDelay; -- tFSS tsetup_FS0SD_RSTNeg : VitalDelayType := UnitDelay; -- tSDS tsetup_FS0SD_CLKA : VitalDelayType := UnitDelay; -- tSENS tsetup_FS1SEN_CLKA : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH thold_A0_CLKA : VitalDelayType := UnitDelay; -- tENH1 thold_ENA_CLKA : VitalDelayType := UnitDelay; -- tENH2 thold_CSANeg_CLKA : VitalDelayType := UnitDelay; -- tRMH thold_RTM_CLKB : VitalDelayType := UnitDelay; -- tRSTH thold_RSTNeg_CLKA : VitalDelayType := UnitDelay; -- tFSH thold_FS0SD_RSTNeg : VitalDelayType := UnitDelay; -- tSDH thold_FS0SD_CLKA : VitalDelayType := UnitDelay; -- tSENH thold_FS1SEN_CLKA : VitalDelayType := UnitDelay; -- tskew values: skew times tdevice_SKEW1 : VitalDelayType := UnitDelay; -- Skew Time, between posedge CLKA and posedge CLKB for ORB and IR; -- tdevice_SKEW2 : VitalDelayType := UnitDelay; -- Skew Time, between posedge CLKA and posedge CLKB for AFNeg and AENeg; -- -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; TimingModel : STRING := DefaultTimingModel ); PORT ( A0 : INOUT std_logic; ----------------------------- A1 : INOUT std_logic; -- A2 : INOUT std_logic; -- A3 : INOUT std_logic; -- A4 : INOUT std_logic; -- A5 : INOUT std_logic; -- A6 : INOUT std_logic; -- A7 : INOUT std_logic; -- A8 : INOUT std_logic; -- A9 : INOUT std_logic; -- A10 : INOUT std_logic; -- A11 : INOUT std_logic; -- A12 : INOUT std_logic; -- A13 : INOUT std_logic; -- A14 : INOUT std_logic; -- A15 : INOUT std_logic; -- A16 : INOUT std_logic; -- A17 : INOUT std_logic; -- A18 : INOUT std_logic; -- 36 pin bidirectional Port-A data bus A19 : INOUT std_logic; -- A20 : INOUT std_logic; -- A21 : INOUT std_logic; -- A22 : INOUT std_logic; -- A23 : INOUT std_logic; -- A24 : INOUT std_logic; -- A25 : INOUT std_logic; -- A26 : INOUT std_logic; -- A27 : INOUT std_logic; -- A28 : INOUT std_logic; -- A29 : INOUT std_logic; -- A30 : INOUT std_logic; -- A31 : INOUT std_logic; -- A32 : INOUT std_logic; -- A33 : INOUT std_logic; -- A34 : INOUT std_logic; -- A35 : INOUT std_logic; -------------------------------------- AENeg : OUT std_logic := 'U'; -- Almost-Empty Flag for Port-B AFNeg : OUT std_logic := 'U'; -- Almost-Full Flag for Port-A B0 : INOUT std_logic; ----------------------------- B1 : INOUT std_logic; -- B2 : INOUT std_logic; -- B3 : INOUT std_logic; -- B4 : INOUT std_logic; -- B5 : INOUT std_logic; -- B6 : INOUT std_logic; -- B7 : INOUT std_logic; -- B8 : INOUT std_logic; -- B9 : INOUT std_logic; -- B10 : INOUT std_logic; -- B11 : INOUT std_logic; -- B12 : INOUT std_logic; -- B13 : INOUT std_logic; -- B14 : INOUT std_logic; -- B15 : INOUT std_logic; -- B16 : INOUT std_logic; -- B17 : INOUT std_logic; -- B18 : INOUT std_logic; -- 36 pin bidirectional Port-B data bus B19 : INOUT std_logic; -- B20 : INOUT std_logic; -- B21 : INOUT std_logic; -- B22 : INOUT std_logic; -- B23 : INOUT std_logic; -- B24 : INOUT std_logic; -- B25 : INOUT std_logic; -- B26 : INOUT std_logic; -- B27 : INOUT std_logic; -- B28 : INOUT std_logic; -- B29 : INOUT std_logic; -- B30 : INOUT std_logic; -- B31 : INOUT std_logic; -- B32 : INOUT std_logic; -- B33 : INOUT std_logic; -- B34 : INOUT std_logic; -- B35 : INOUT std_logic; -------------------------------------- CLKA : IN std_logic := 'X'; -- Port-A clock CLKB : IN std_logic := 'X'; -- Port-B clock CSANeg : IN std_logic := 'X'; -- Port-A Chip Select CSBNeg : IN std_logic := 'X'; -- Port-B Chip Select ORB : OUT std_logic := 'U'; -- Port-B Empty / Output Ready Flag ENA : IN std_logic := 'X'; -- Port-A Enable ENB : IN std_logic := 'X'; -- Port-B Enable IR : OUT std_logic := 'U'; -- Port-A Full / Input Ready Flag FS0SD : IN std_logic := 'X'; -- Flag Offset Select 0 / Serial Data FS1SEN : IN std_logic := 'X'; -- Flag Offset Select 1 / Serial Enable MBA : IN std_logic := 'X'; -- Port-A Mailbox Select MBB : IN std_logic := 'X'; -- Port-B Mailbox Select MBF1Neg : OUT std_logic := 'U'; -- Mail1 Register Flag MBF2Neg : OUT std_logic := 'U'; -- Mail2 Register Flag RSTNeg : IN std_logic := 'X'; -- Reset RFM : IN std_logic := 'X'; -- Read From Mark RTM : IN std_logic := 'X'; -- Retransmit Mode WRA : IN std_logic := 'X'; -- Port-A Write/Read Select WRB : IN std_logic := 'X' -- Port-B Write/Read Select ); ATTRIBUTE vital_level0 OF IDT723651 : ENTITY IS True; END IDT723651; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -- -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF IDT723651 IS ATTRIBUTE vital_level0 OF vhdl_behavioral : ARCHITECTURE IS True; -- CONSTANTS which define IDT723631 / IDT723641 / IDT723651 type CONSTANT FIFOPOWER : POSITIVE := 11; -- 9/10/11- CONSTANT FIFOSize : POSITIVE := 2** FIFOPOWER; -- 512/1024/2048 CONSTANT OffsetSize : POSITIVE := FIFOPOWER ; -- 9/10/11- CONSTANT partID : String := "IDT723651"; -- delayed inputs and bidirectional ports -- (func. sec. must use these signals instead of actual inputs/inoutputs) SIGNAL A0_ipd : std_ulogic := 'X'; SIGNAL A1_ipd : std_ulogic := 'X'; SIGNAL A2_ipd : std_ulogic := 'X'; SIGNAL A3_ipd : std_ulogic := 'X'; SIGNAL A4_ipd : std_ulogic := 'X'; SIGNAL A5_ipd : std_ulogic := 'X'; SIGNAL A6_ipd : std_ulogic := 'X'; SIGNAL A7_ipd : std_ulogic := 'X'; SIGNAL A8_ipd : std_ulogic := 'X'; SIGNAL A9_ipd : std_ulogic := 'X'; SIGNAL A10_ipd : std_ulogic := 'X'; SIGNAL A11_ipd : std_ulogic := 'X'; SIGNAL A12_ipd : std_ulogic := 'X'; SIGNAL A13_ipd : std_ulogic := 'X'; SIGNAL A14_ipd : std_ulogic := 'X'; SIGNAL A15_ipd : std_ulogic := 'X'; SIGNAL A16_ipd : std_ulogic := 'X'; SIGNAL A17_ipd : std_ulogic := 'X'; SIGNAL A18_ipd : std_ulogic := 'X'; SIGNAL A19_ipd : std_ulogic := 'X'; SIGNAL A20_ipd : std_ulogic := 'X'; SIGNAL A21_ipd : std_ulogic := 'X'; SIGNAL A22_ipd : std_ulogic := 'X'; SIGNAL A23_ipd : std_ulogic := 'X'; SIGNAL A24_ipd : std_ulogic := 'X'; SIGNAL A25_ipd : std_ulogic := 'X'; SIGNAL A26_ipd : std_ulogic := 'X'; SIGNAL A27_ipd : std_ulogic := 'X'; SIGNAL A28_ipd : std_ulogic := 'X'; SIGNAL A29_ipd : std_ulogic := 'X'; SIGNAL A30_ipd : std_ulogic := 'X'; SIGNAL A31_ipd : std_ulogic := 'X'; SIGNAL A32_ipd : std_ulogic := 'X'; SIGNAL A33_ipd : std_ulogic := 'X'; SIGNAL A34_ipd : std_ulogic := 'X'; SIGNAL A35_ipd : std_ulogic := 'X'; SIGNAL B0_ipd : std_ulogic := 'X'; SIGNAL B1_ipd : std_ulogic := 'X'; SIGNAL B2_ipd : std_ulogic := 'X'; SIGNAL B3_ipd : std_ulogic := 'X'; SIGNAL B4_ipd : std_ulogic := 'X'; SIGNAL B5_ipd : std_ulogic := 'X'; SIGNAL B6_ipd : std_ulogic := 'X'; SIGNAL B7_ipd : std_ulogic := 'X'; SIGNAL B8_ipd : std_ulogic := 'X'; SIGNAL B9_ipd : std_ulogic := 'X'; SIGNAL B10_ipd : std_ulogic := 'X'; SIGNAL B11_ipd : std_ulogic := 'X'; SIGNAL B12_ipd : std_ulogic := 'X'; SIGNAL B13_ipd : std_ulogic := 'X'; SIGNAL B14_ipd : std_ulogic := 'X'; SIGNAL B15_ipd : std_ulogic := 'X'; SIGNAL B16_ipd : std_ulogic := 'X'; SIGNAL B17_ipd : std_ulogic := 'X'; SIGNAL B18_ipd : std_ulogic := 'X'; SIGNAL B19_ipd : std_ulogic := 'X'; SIGNAL B20_ipd : std_ulogic := 'X'; SIGNAL B21_ipd : std_ulogic := 'X'; SIGNAL B22_ipd : std_ulogic := 'X'; SIGNAL B23_ipd : std_ulogic := 'X'; SIGNAL B24_ipd : std_ulogic := 'X'; SIGNAL B25_ipd : std_ulogic := 'X'; SIGNAL B26_ipd : std_ulogic := 'X'; SIGNAL B27_ipd : std_ulogic := 'X'; SIGNAL B28_ipd : std_ulogic := 'X'; SIGNAL B29_ipd : std_ulogic := 'X'; SIGNAL B30_ipd : std_ulogic := 'X'; SIGNAL B31_ipd : std_ulogic := 'X'; SIGNAL B32_ipd : std_ulogic := 'X'; SIGNAL B33_ipd : std_ulogic := 'X'; SIGNAL B34_ipd : std_ulogic := 'X'; SIGNAL B35_ipd : std_ulogic := 'X'; SIGNAL CLKA_ipd : std_ulogic := 'X'; SIGNAL CLKB_ipd : std_ulogic := 'X'; SIGNAL CSANeg_ipd : std_ulogic := 'X'; SIGNAL CSBNeg_ipd : std_ulogic := 'X'; SIGNAL ENA_ipd : std_ulogic := 'X'; SIGNAL ENB_ipd : std_ulogic := 'X'; SIGNAL FS0SD_ipd : std_ulogic := 'X'; SIGNAL FS1SEN_ipd : std_ulogic := 'X'; SIGNAL MBA_ipd : std_ulogic := 'X'; SIGNAL MBB_ipd : std_ulogic := 'X'; SIGNAL RSTNeg_ipd : std_ulogic := 'X'; SIGNAL RFM_ipd : std_logic := 'X'; SIGNAL RTM_ipd : std_logic := 'X'; SIGNAL WRA_ipd : std_ulogic := 'X'; SIGNAL WRB_ipd : std_ulogic := 'X'; SIGNAL OpenIn, OpenOut : std_logic; -- Additional signals ALIAS tA : VitalDelayType01 IS tpd_CLKB_B0; ALIAS tPIR : VitalDelayType01 IS tpd_CLKA_IR; ALIAS tPOR : VitalDelayType01 IS tpd_CLKB_ORB; ALIAS tPAE : VitalDelayType01 IS tpd_CLKB_AENeg; ALIAS tPAF : VitalDelayType01 IS tpd_CLKA_AFNeg; ALIAS tPMF : VitalDelayType01 IS tpd_CLKA_MBF1Neg; ALIAS tPMR : VitalDelayType01 IS tpd_CLKA_B0; ALIAS tMDV : VitalDelayType01 IS tpd_MBB_B0; ALIAS tRSF : VitalDelayType01 IS tpd_RSTNeg_AENeg; ALIAS tEN_DIS : VitalDelayType01Z IS tpd_CSANeg_A0; ALIAS tCLK : VitalDelayType IS tperiod_CLKA_posedge; ALIAS tCLKH : VitalDelayType IS tpw_CLKA_posedge; ALIAS tCLKL : VitalDelayType IS tpw_CLKA_negedge; ALIAS tDS : VitalDelayType IS tsetup_A0_CLKA; ALIAS tENS1 : VitalDelayType IS tsetup_ENA_CLKA; ALIAS tENS2 : VitalDelayType IS tsetup_CSANeg_CLKA; ALIAS tRMS : VitalDelayType IS tsetup_RTM_CLKB; ALIAS tRSTS : VitalDelayType IS tsetup_RSTNeg_CLKA; ALIAS tFSS : VitalDelayType IS tsetup_FS0SD_RSTNeg; ALIAS tSDS : VitalDelayType IS tsetup_FS0SD_CLKA; ALIAS tSENS : VitalDelayType IS tsetup_FS1SEN_CLKA; ALIAS tDH : VitalDelayType IS thold_A0_CLKA; ALIAS tENH1 : VitalDelayType IS thold_ENA_CLKA; ALIAS tENH2 : VitalDelayType IS thold_CSANeg_CLKA; ALIAS tRMH : VitalDelayType IS thold_RTM_CLKB; ALIAS tRSTH : VitalDelayType IS thold_RSTNeg_CLKA; ALIAS tFSH : VitalDelayType IS thold_FS0SD_RSTNeg; ALIAS tSDH : VitalDelayType IS thold_FS0SD_CLKA; ALIAS tSENH : VitalDelayType IS thold_FS1SEN_CLKA; BEGIN -------------------------------------------------------------------------------- -- Skew Delays -------------------------------------------------------------------------------- -- Artificient VITAL primitives wich allows pass complex non-constaint -- SKEW time into the model SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1)); SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2)); -------------------------------------------------------------------------------- -- Wire Delays -- -------------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (A0_ipd, A0, tipd_A0 ); w_2: VitalWireDelay (A1_ipd, A1, tipd_A1 ); w_3: VitalWireDelay (A2_ipd, A2, tipd_A2 ); w_4: VitalWireDelay (A3_ipd, A3, tipd_A3 ); w_5: VitalWireDelay (A4_ipd, A4, tipd_A4 ); w_6: VitalWireDelay (A5_ipd, A5, tipd_A5 ); w_7: VitalWireDelay (A6_ipd, A6, tipd_A6 ); w_8: VitalWireDelay (A7_ipd, A7, tipd_A7 ); w_9: VitalWireDelay (A8_ipd, A8, tipd_A8 ); w_10: VitalWireDelay (A9_ipd, A9, tipd_A9 ); w_11: VitalWireDelay (A10_ipd, A10, tipd_A10 ); w_12: VitalWireDelay (A11_ipd, A11, tipd_A11 ); w_13: VitalWireDelay (A12_ipd, A12, tipd_A12 ); w_14: VitalWireDelay (A13_ipd, A13, tipd_A13 ); w_15: VitalWireDelay (A14_ipd, A14, tipd_A14 ); w_16: VitalWireDelay (A15_ipd, A15, tipd_A15 ); w_17: VitalWireDelay (A16_ipd, A16, tipd_A16 ); w_18: VitalWireDelay (A17_ipd, A17, tipd_A17 ); w_19: VitalWireDelay (A18_ipd, A18, tipd_A18 ); w_20: VitalWireDelay (A19_ipd, A19, tipd_A19 ); w_21: VitalWireDelay (A20_ipd, A20, tipd_A20 ); w_22: VitalWireDelay (A21_ipd, A21, tipd_A21 ); w_23: VitalWireDelay (A22_ipd, A22, tipd_A22 ); w_24: VitalWireDelay (A23_ipd, A23, tipd_A23 ); w_25: VitalWireDelay (A24_ipd, A24, tipd_A24 ); w_26: VitalWireDelay (A25_ipd, A25, tipd_A25 ); w_27: VitalWireDelay (A26_ipd, A26, tipd_A26 ); w_28: VitalWireDelay (A27_ipd, A27, tipd_A27 ); w_29: VitalWireDelay (A28_ipd, A28, tipd_A28 ); w_30: VitalWireDelay (A29_ipd, A29, tipd_A29 ); w_31: VitalWireDelay (A30_ipd, A30, tipd_A30 ); w_32: VitalWireDelay (A31_ipd, A31, tipd_A31 ); w_33: VitalWireDelay (A32_ipd, A32, tipd_A32 ); w_34: VitalWireDelay (A33_ipd, A33, tipd_A33 ); w_35: VitalWireDelay (A34_ipd, A34, tipd_A34 ); w_36: VitalWireDelay (A35_ipd, A35, tipd_A35 ); w_37: VitalWireDelay (B0_ipd, B0, tipd_B0 ); w_38: VitalWireDelay (B1_ipd, B1, tipd_B1 ); w_39: VitalWireDelay (B2_ipd, B2, tipd_B2 ); w_40: VitalWireDelay (B3_ipd, B3, tipd_B3 ); w_41: VitalWireDelay (B4_ipd, B4, tipd_B4 ); w_42: VitalWireDelay (B5_ipd, B5, tipd_B5 ); w_43: VitalWireDelay (B6_ipd, B6, tipd_B6 ); w_44: VitalWireDelay (B7_ipd, B7, tipd_B7 ); w_45: VitalWireDelay (B8_ipd, B8, tipd_B8 ); w_46: VitalWireDelay (B9_ipd, B9, tipd_B9 ); w_47: VitalWireDelay (B10_ipd, B10, tipd_B10 ); w_48: VitalWireDelay (B11_ipd, B11, tipd_B11 ); w_49: VitalWireDelay (B12_ipd, B12, tipd_B12 ); w_50: VitalWireDelay (B13_ipd, B13, tipd_B13 ); w_51: VitalWireDelay (B14_ipd, B14, tipd_B14 ); w_52: VitalWireDelay (B15_ipd, B15, tipd_B15 ); w_53: VitalWireDelay (B16_ipd, B16, tipd_B16 ); w_54: VitalWireDelay (B17_ipd, B17, tipd_B17 ); w_55: VitalWireDelay (B18_ipd, B18, tipd_B18 ); w_56: VitalWireDelay (B19_ipd, B19, tipd_B19 ); w_57: VitalWireDelay (B20_ipd, B20, tipd_B20 ); w_58: VitalWireDelay (B21_ipd, B21, tipd_B21 ); w_59: VitalWireDelay (B22_ipd, B22, tipd_B22 ); w_60: VitalWireDelay (B23_ipd, B23, tipd_B23 ); w_61: VitalWireDelay (B24_ipd, B24, tipd_B24 ); w_62: VitalWireDelay (B25_ipd, B25, tipd_B25 ); w_63: VitalWireDelay (B26_ipd, B26, tipd_B26 ); w_64: VitalWireDelay (B27_ipd, B27, tipd_B27 ); w_65: VitalWireDelay (B28_ipd, B28, tipd_B28 ); w_66: VitalWireDelay (B29_ipd, B29, tipd_B29 ); w_67: VitalWireDelay (B30_ipd, B30, tipd_B30 ); w_68: VitalWireDelay (B31_ipd, B31, tipd_B31 ); w_69: VitalWireDelay (B32_ipd, B32, tipd_B32 ); w_70: VitalWireDelay (B33_ipd, B33, tipd_B33 ); w_71: VitalWireDelay (B34_ipd, B34, tipd_B34 ); w_72: VitalWireDelay (B35_ipd, B35, tipd_B35 ); w_75: VitalWireDelay (CLKA_ipd, CLKA, tipd_CLKA ); w_76: VitalWireDelay (CLKB_ipd, CLKB, tipd_CLKB ); w_77: VitalWireDelay (CSANeg_ipd, CSANeg, tipd_CSANeg ); w_78: VitalWireDelay (CSBNeg_ipd, CSBNeg, tipd_CSBNeg ); w_79: VitalWireDelay (ENA_ipd, ENA, tipd_ENA ); w_80: VitalWireDelay (ENB_ipd, ENB, tipd_ENB ); w_81: VitalWireDelay (FS0SD_ipd, FS0SD, tipd_FS0SD ); w_82: VitalWireDelay (FS1SEN_ipd, FS1SEN, tipd_FS1SEN ); w_83: VitalWireDelay (MBA_ipd, MBA, tipd_MBA ); w_84: VitalWireDelay (MBB_ipd, MBB, tipd_MBB ); w_85: VitalWireDelay (RFM_ipd, RFM , tipd_RFM ); w_86: VitalWireDelay (RTM_ipd, RTM , tipd_RTM ); w_87: VitalWireDelay (RSTNeg_ipd, RSTNeg, tipd_RSTNeg ); w_91: VitalWireDelay (WRA_ipd, WRA, tipd_WRA ); w_92: VitalWireDelay (WRB_ipd, WRB, tipd_WRB ); END BLOCK; -------------------------------------------------------------------------------- -- Main Behavior Block -- -------------------------------------------------------------------------------- VITALBehavior: BLOCK PORT ( A_ipd : IN std_logic_vector(35 downto 0) := (OTHERS => 'X'); A : OUT std_logic_vector(35 downto 0) := (OTHERS => 'U'); AENeg : OUT std_logic := 'U'; AFNeg : OUT std_logic := 'U'; B_ipd : IN std_logic_vector(35 downto 0) := (OTHERS => 'X'); B : OUT std_logic_vector(35 downto 0) := (OTHERS => 'U'); CLKA : IN std_logic := 'X'; CLKB : IN std_logic := 'X'; CSANeg : IN std_logic := 'X'; CSBNeg : IN std_logic := 'X'; ENA : IN std_logic := 'X'; ENB : IN std_logic := 'X'; IR : OUT std_logic := 'U'; FS0SD : IN std_logic := 'X'; FS1SEN : IN std_logic := 'X'; MBA : IN std_logic := 'X'; MBB : IN std_logic := 'X'; MBF1Neg : OUT std_logic := 'U'; MBF2Neg : OUT std_logic := 'U'; ORB : OUT std_logic := 'U'; RSTNeg : IN std_logic := 'X'; RFM : IN std_logic := 'X'; RTM : IN std_logic := 'X'; WRA : IN std_logic := 'X'; WRB : IN std_logic := 'X' ); PORT MAP ( A_ipd(0) => A0_ipd, A_ipd(1) => A1_ipd, A_ipd(2) => A2_ipd, A_ipd(3) => A3_ipd, A_ipd(4) => A4_ipd, A_ipd(5) => A5_ipd, A_ipd(6) => A6_ipd, A_ipd(7) => A7_ipd, A_ipd(8) => A8_ipd, A_ipd(9) => A9_ipd, A_ipd(10) => A10_ipd, A_ipd(11) => A11_ipd, A_ipd(12) => A12_ipd, A_ipd(13) => A13_ipd, A_ipd(14) => A14_ipd, A_ipd(15) => A15_ipd, A_ipd(16) => A16_ipd, A_ipd(17) => A17_ipd, A_ipd(18) => A18_ipd, A_ipd(19) => A19_ipd, A_ipd(20) => A20_ipd, A_ipd(21) => A21_ipd, A_ipd(22) => A22_ipd, A_ipd(23) => A23_ipd, A_ipd(24) => A24_ipd, A_ipd(25) => A25_ipd, A_ipd(26) => A26_ipd, A_ipd(27) => A27_ipd, A_ipd(28) => A28_ipd, A_ipd(29) => A29_ipd, A_ipd(30) => A30_ipd, A_ipd(31) => A31_ipd, A_ipd(32) => A32_ipd, A_ipd(33) => A33_ipd, A_ipd(34) => A34_ipd, A_ipd(35) => A35_ipd, A(0) => A0, A(1) => A1, A(2) => A2, A(3) => A3, A(4) => A4, A(5) => A5, A(6) => A6, A(7) => A7, A(8) => A8, A(9) => A9, A(10) => A10, A(11) => A11, A(12) => A12, A(13) => A13, A(14) => A14, A(15) => A15, A(16) => A16, A(17) => A17, A(18) => A18, A(19) => A19, A(20) => A20, A(21) => A21, A(22) => A22, A(23) => A23, A(24) => A24, A(25) => A25, A(26) => A26, A(27) => A27, A(28) => A28, A(29) => A29, A(30) => A30, A(31) => A31, A(32) => A32, A(33) => A33, A(34) => A34, A(35) => A35, AENeg => AENeg, AFNeg => AFNeg, B_ipd(0) => B0_ipd, B_ipd(1) => B1_ipd, B_ipd(2) => B2_ipd, B_ipd(3) => B3_ipd, B_ipd(4) => B4_ipd, B_ipd(5) => B5_ipd, B_ipd(6) => B6_ipd, B_ipd(7) => B7_ipd, B_ipd(8) => B8_ipd, B_ipd(9) => B9_ipd, B_ipd(10) => B10_ipd, B_ipd(11) => B11_ipd, B_ipd(12) => B12_ipd, B_ipd(13) => B13_ipd, B_ipd(14) => B14_ipd, B_ipd(15) => B15_ipd, B_ipd(16) => B16_ipd, B_ipd(17) => B17_ipd, B_ipd(18) => B18_ipd, B_ipd(19) => B19_ipd, B_ipd(20) => B20_ipd, B_ipd(21) => B21_ipd, B_ipd(22) => B22_ipd, B_ipd(23) => B23_ipd, B_ipd(24) => B24_ipd, B_ipd(25) => B25_ipd, B_ipd(26) => B26_ipd, B_ipd(27) => B27_ipd, B_ipd(28) => B28_ipd, B_ipd(29) => B29_ipd, B_ipd(30) => B30_ipd, B_ipd(31) => B31_ipd, B_ipd(32) => B32_ipd, B_ipd(33) => B33_ipd, B_ipd(34) => B34_ipd, B_ipd(35) => B35_ipd, B(0) => B0, B(1) => B1, B(2) => B2, B(3) => B3, B(4) => B4, B(5) => B5, B(6) => B6, B(7) => B7, B(8) => B8, B(9) => B9, B(10) => B10, B(11) => B11, B(12) => B12, B(13) => B13, B(14) => B14, B(15) => B15, B(16) => B16, B(17) => B17, B(18) => B18, B(19) => B19, B(20) => B20, B(21) => B21, B(22) => B22, B(23) => B23, B(24) => B24, B(25) => B25, B(26) => B26, B(27) => B27, B(28) => B28, B(29) => B29, B(30) => B30, B(31) => B31, B(32) => B32, B(33) => B33, B(34) => B34, B(35) => B35, CLKA => CLKA_ipd, CLKB => CLKB_ipd, CSANeg => CSANeg_ipd, CSBNeg => CSBNeg_ipd, ENA => ENA_ipd, ENB => ENB_ipd, IR => IR, FS0SD => FS0SD_ipd, FS1SEN => FS1SEN_ipd, MBA => MBA_ipd, MBB => MBB_ipd, MBF1Neg => MBF1Neg, MBF2Neg => MBF2Neg, ORB => ORB, RSTNeg => RSTNeg_ipd, RFM =>RFM_ipd, RTM =>RTM_ipd, WRA => WRA_ipd, WRB => WRB_ipd); -- zero delayed outputs and bidirectional ports -- (func. sec. uses these signals instead of = -- actual outputs and bidirectional ports); -- actual outputs are assigned in Path Delay Section SIGNAL A_zd : std_logic_vector (35 downto 0); SIGNAL B_zd : std_logic_vector (35 downto 0); SIGNAL AENeg_zd : std_logic; SIGNAL AFNeg_zd : std_logic; SIGNAL IR_zd : std_logic; SIGNAL MBF1Neg_zd : std_logic; SIGNAL MBF2Neg_zd : std_logic; SIGNAL ORB_zd : std_logic; ------------------------------------------------------------------------------ -- FIFO memory definitions ------------------------------------------------------------------------------ -- general CONSTANT FIFOWordLength : positive := 36; SUBTYPE FIFOWord IS std_logic_vector(FIFOWordLength - 1 DOWNTO 0); TYPE FIFOArray IS ARRAY (0 TO FIFOSize - 1) OF FIFOWord; CONSTANT MailWordLength : positive := 36; SUBTYPE MailWord IS std_logic_vector(MailWordLength - 1 DOWNTO 0); CONSTANT Offs_Par_Number : positive := 2; -- Number of Words while -- Parallel Offset Loading CONSTANT Offs_Ser_Number : positive := OffsetSize*2; -- Number of Bits while -- Serial Offset Loading CONSTANT Offs_Val_Limit : positive := FIFOSize-4; -- offset value limit while -- Offset Loading -- special CONSTANT FIFOWordBytes : positive := 4; ------------------------------------------------------------------------------ -- internal signals ------------------------------------------------------------------------------ -- FIFO Arrays SIGNAL FIFOMemory1int : FIFOArray := (FIFOArray'range => FIFOWord'(OTHERS => 'X')); -- Main Registers -- Input Registers SIGNAL InputReg1int : FIFOWord := (OTHERS => 'X'); -- Output Registers SIGNAL OutputReg1int : FIFOWord := (OTHERS => 'X'); -- FIFO Pointers SIGNAL ReadPtr1int : Natural RANGE 0 TO FIFOSize-1; SIGNAL WritePtr1int : Natural RANGE 0 TO FIFOSize-1; SIGNAL ReadPtr1int_add : std_logic; -- additional high bits to differ cases when SIGNAL WritePtr1int_add : std_logic; -- FIFO empty or full SIGNAL ShadowReadPtrint : Natural RANGE 0 TO FIFOSize-1; SIGNAL ShadowReadPtrint_add : std_logic; SIGNAL ReadPtr1_sel_int : Natural RANGE 0 TO FIFOSize-1; -- selected from SIGNAL ReadPtr1_sel_int_add : std_logic; -- ReadPtr and ShadowReadPtr -- FIFO Offset for Almoust Empty/Full Flags SIGNAL X1int, Y1int : NATURAL RANGE 0 TO Offs_Val_Limit; -- Mail Registers SIGNAL Mail1int, Mail2int : MailWord := (OTHERS => 'X'); -- Flags SIGNAL IRint, ORint, EFNegint: std_ulogic; SIGNAL AE1int, AF1int : std_ulogic; ---------- Input Registers Controlling Signals ------------ -- Flags "Input Register is loaded" - in this -- model they will be loaded to FIFOMemory on CLK negedge ------?? SIGNAL InputReg1Readyint : std_ulogic; ---------- Output Registers Controlling Signals ------------ SIGNAL FWFTFirst : std_ulogic:='1'; -- first word though in FWFT mode ------------------------------------------------------------------------- -- Reset SIGNAL RST1int: std_ulogic; SIGNAL MRSDoneint: std_ulogic := '0'; -- Counters of Clocks during Master/Partion Reset is active or just after -- Reset SIGNAL CountCLKA1int, CountCLKB1int : Natural; -- Internal Control Signals SIGNAL EnWrFIFO1int, EnRdFIFO1int, EnWrMail1int, EnRdMail1int, EnWrMail2int, EnRdMail2int: std_ulogic; --------------------------------------------------------------------------- -- ALmost-Empty/Almost-Full Offsets Loading Mode SIGNAL Offs_Par_Load_Modeint : std_ulogic := '0'; -- Parallel Offsets Loading Mode SIGNAL Offs_Ser_Load_Modeint : std_ulogic := '0'; -- Serial Offsets Loading Mode -- Word/Bit Counter while Offset Loading SIGNAL CountLoadOffsetint: Natural; ------------------------------------------------------------------- --Retransmit mode signals SIGNAL RetModeBegint, Ret1int, Ret2int: std_ulogic; --------------------------------------------------------------------------- -- Additional Signals SIGNAL SIZBint: std_ulogic; ---------------------------------------------------------------------------- -- Internal Signals for Full /Empty FLAGS implementation according -- to IDT Verilog gate-level model simulation SIGNAL STATE1B,STATE2A:STD_LOGIC; SIGNAL F1ORB,F2ORB,F3ORB,WrORB,WrFORB,BYPB:STD_LOGIC; SIGNAL F1IRA,F2IRA,WrIRA,WrFIRA :STD_LOGIC; SIGNAL B0C1ORB: NATURAL; SIGNAL B0C1IRA: NATURAL; SIGNAL OPTEO :STD_LOGIC; SIGNAL En_ORB, En2_ORB : STD_LOGIC; SIGNAL Counter1_ORB, Counter2_ORB : STD_LOGIC; SIGNAL EFlGen_B, EF1l_B, EF2l_B, ORB_B2 : STD_LOGIC; SIGNAL EF2l_B_add : STD_LOGIC; SIGNAL AFTEn_AE_B, Eql_ORB, Eq_ORB : STD_LOGIC; SIGNAL BMAft_ORB, BMAft_Reg3 : STD_LOGIC; SIGNAL RDP_1, ReadPtr1_l_int : Natural RANGE 0 TO FIFOSize-1; SIGNAL ReadPtr1_l_int_add : std_logic; ---------------------------------------------------------------------------- -- Internal Signals for AFA/AEA/AFB/AEB FLAGS implementation according -- to IDT Verilog gate-level model simulation SIGNAL IRHdl2 : STD_LOGIC; SIGNAL UniEnl : STD_LOGIC := '1'; SIGNAL BEFWFTl : STD_LOGIC; SIGNAL MRSTl1, PRSTl1 : STD_LOGIC; SIGNAL Rd_Ptr1, Wr_Ptr1 : STD_LOGIC_VECTOR (FIFOPOWER -1 DOWNTO 0); SIGNAL AFlGen_A, AF1l_A, AF2l_A, AFlA : STD_LOGIC; SIGNAL RcvEn_AF_A, BCmpEn_AF_A : STD_LOGIC; SIGNAL AElGen_B, AE1l_B, AE2l_B, AElB : STD_LOGIC; SIGNAL RcvEn_AE_B, BCmpEn_AE_B : STD_LOGIC; SIGNAL AF_A, AE_B : STD_LOGIC_VECTOR (FIFOPOWER - 1 DOWNTO 0); BEGIN -- VitalBehavior block -------------------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------------------- TimingChecks: PROCESS ( A_ipd, B_ipd, CLKA, CLKB, CSANeg, CSBNeg, ENA, ENB, FS0SD, FS1SEN, MBA, MBB, RFM , RTM ,RSTNeg, WRA, WRB) -- Timing Check Variables -- Pulse Width Check Variables VARIABLE Pviol_CLKA : X01 := '0'; VARIABLE PD_CLKA : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKB : X01 := '0'; VARIABLE PD_CLKB : VitalPeriodDataType := VitalPeriodDataInit; -- Setup/Hold Check Variables VARIABLE Tviol_A0_CLKA : X01 := '0'; VARIABLE TD_A0_CLKA : VitalTimingDataType; VARIABLE TViol_B0_CLKB : X01 := '0'; VARIABLE TD_B0_CLKB : VitalTimingDataType; VARIABLE Tviol_CSANeg_CLKA : X01 := '0'; VARIABLE TD_CSANeg_CLKA : VitalTimingDataType; VARIABLE Tviol_WRA_CLKA : X01 := '0'; VARIABLE TD_WRA_CLKA : VitalTimingDataType; VARIABLE Tviol_ENA_CLKA : X01 := '0'; VARIABLE TD_ENA_CLKA : VitalTimingDataType; VARIABLE Tviol_MBA_CLKA : X01 := '0'; VARIABLE TD_MBA_CLKA : VitalTimingDataType; VARIABLE Tviol_CSBNeg_CLKB : X01 := '0'; VARIABLE TD_CSBNeg_CLKB : VitalTimingDataType; VARIABLE Tviol_WRB_CLKB : X01 := '0'; VARIABLE TD_WRB_CLKB : VitalTimingDataType; VARIABLE Tviol_ENB_CLKB : X01 := '0'; VARIABLE TD_ENB_CLKB : VitalTimingDataType; VARIABLE Tviol_MBB_CLKB : X01 := '0'; VARIABLE TD_MBB_CLKB : VitalTimingDataType; VARIABLE Tviol_RSTNeg_CLKA : X01 := '0'; VARIABLE TD_RSTNeg_CLKA : VitalTimingDataType; VARIABLE Tviol_RSTNeg_CLKB : X01 := '0'; VARIABLE TD_RSTNeg_CLKB : VitalTimingDataType; VARIABLE Tviol_FS0SD_RSTNeg : X01 := '0'; VARIABLE TD_FS0SD_RSTNeg : VitalTimingDataType; VARIABLE Tviol_FS1SEN_RSTNeg: X01 := '0'; VARIABLE TD_FS1SEN_RSTNeg : VitalTimingDataType; VARIABLE Tviol_FS0SD_CLKA : X01 := '0'; VARIABLE TD_FS0SD_CLKA : VitalTimingDataType; VARIABLE Tviol_FS1SEN_CLKA : X01 := '0'; VARIABLE TD_FS1SEN_CLKA : VitalTimingDataType; VARIABLE Tviol_RFM_CLKB : X01 := '0'; VARIABLE TD_RFM_CLKB : VitalTimingDataType; VARIABLE Tviol_RTM_CLKB : X01 := '0'; VARIABLE TD_RTM_CLKB : VitalTimingDataType; -- Violation variable (used to OR all individual violation variables) VARIABLE Violation : X01 := '0'; BEGIN -------------------------------------------------------------------------------- -- Timing Check Section -- -------------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- CLKA period and pulse width check(high & low) VitalPeriodPulseCheck ( TestSignal => CLKA, TestSignalName => "CLKA", Period => tCLK, PulseWidthHigh => tCLKH, PulseWidthLow => tCLKL, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKA); -- CLKB period and pulse width check(high & low) VitalPeriodPulseCheck ( TestSignal => CLKB, TestSignalName => "CLKB", Period => tCLK, PulseWidthHigh => tCLKH, PulseWidthLow => tCLKL, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKB); -- A/CLKA setup/hold time checks VitalSetupHoldCheck ( TestSignal => A_ipd, TestSignalName => "A", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tDS, SetupLow => tDS, HoldHigh => tDH, HoldLow => tDH, CheckEnabled => (CSANeg = '0') AND (WRA = '1') AND (ENA = '1'), RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_A0_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A0_CLKA); -- B/CLKB setup/hold time checks VitalSetupHoldCheck ( TestSignal => B_ipd, TestSignalName => "B", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tDS, SetupLow => tDS, HoldHigh => tDH, HoldLow => tDH, CheckEnabled => (CSBNeg = '0') AND (WRB = '0') AND (ENB = '1'), RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_B0_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => TViol_B0_CLKB); -- CSANeg/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => CSANeg, TestSignalName => "CSANeg", RefSignal => CLKA, RefSignalName => "CLKA", SetupLow => tENS2, SetupHigh => tENS2, HoldLow => tENH2, HoldHigh => tENH2, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CSANeg_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CSANeg_CLKA); -- WRA/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => WRA, TestSignalName => "WRA", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tENS2, SetupLow => tENS2, HoldHigh => tENH2, HoldLow => tENH2, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WRA_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WRA_CLKA); -- ENA/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => ENA, TestSignalName => "ENA", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tENS1, SetupLow => tENS1, HoldHigh => tENH1, HoldLow => tENH1, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_ENA_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ENA_CLKA); -- MBA/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => MBA, TestSignalName => "MBA", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tENS2, SetupLow => tENS2, HoldHigh => tENH2, HoldLow => tENH2, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_MBA_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MBA_CLKA); -- CSBNeg/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => CSBNeg, TestSignalName => "CSBNeg", RefSignal => CLKB, RefSignalName => "CLKB", SetupLow => tENS2, SetupHigh => tENS2, HoldLow => tENH2, HoldHigh => tENH2, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CSBNeg_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CSBNeg_CLKB); -- WRB/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => WRB, TestSignalName => "WRB", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tENS2, SetupLow => tENS2, HoldHigh => tENH2, HoldLow => tENH2, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WRB_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WRB_CLKB); -- ENB/CLKB setup/hold time check VitalSetupHoldCheck ( -----------------------! TestSignal => ENB, TestSignalName => "ENB", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tENS1, SetupLow => tENS1, HoldHigh => tENH1, HoldLow => tENH1, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_ENB_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ENB_CLKB); -- MBB/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => MBB, TestSignalName => "MBB", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tENS2, SetupLow => tENS2, HoldHigh => tENH2, HoldLow => tENH2, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_MBB_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MBB_CLKB); -- ENB/CLKB setup/hold time check VitalSetupHoldCheck (-------------------------------2 TestSignal => ENB, TestSignalName => "ENB", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tENS1, SetupLow => tENS1, HoldHigh => tENH1, HoldLow => tENH1, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_ENB_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ENB_CLKB); -- MBB/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => MBB, TestSignalName => "MBB", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tENS2, SetupLow => tENS2, HoldHigh => tENH2, HoldLow => tENH2, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_MBB_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MBB_CLKB); -- RSTNeg/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => RSTNeg, TestSignalName => "RSTNeg", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tRSTS, SetupLow => tRSTS, HoldHigh => tRSTH, HoldLow => tRSTH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RSTNeg_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RSTNeg_CLKA); -- RSTNeg/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => RSTNeg, TestSignalName => "RSTNeg", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tRSTS, SetupLow => tRSTS, HoldHigh => tRSTH, HoldLow => tRSTH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RSTNeg_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RSTNeg_CLKB); -- RTM/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => RTM, TestSignalName => "RTM", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => TRMS, SetupLow => TRMS, HoldHigh => TRMH, HoldLow => TRMH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTM_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTM_CLKB); -- RFM/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => RFM, TestSignalName => "RFM", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => TRMS, SetupLow => TRMS, HoldHigh => TRMH, HoldLow => TRMH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RFM_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RFM_CLKB); -- FSOsD/RSTNeg setup/hold time check VitalSetupHoldCheck ( TestSignal => FS0SD, TestSignalName => "FS0SD", RefSignal => RSTNeg, RefSignalName => "RSTNeg", SetupHigh => tFSS, SetupLow => tFSS, HoldHigh => tFSH, HoldLow => tFSH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS0SD_RSTNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS0SD_RSTNeg); -- FS1SEN/RSTNeg setup/hold time check VitalSetupHoldCheck ( TestSignal => FS1SEN, TestSignalName => "FS1SEN", RefSignal => RSTNeg, RefSignalName => "RSTNeg", SetupHigh => tFSS, SetupLow => tFSS, HoldHigh => tFSH, HoldLow => tFSH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS1SEN_RSTNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS1SEN_RSTNeg); -- FS0SD/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => FS0SD, TestSignalName => "FS0SD", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tSDS, SetupLow => tSDS, HoldHigh => tSDH, HoldLow => tSDH, CheckEnabled => Offs_Ser_Load_Modeint = '1', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS0SD_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS0SD_CLKA); -- FS1SEN/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => FS1SEN, TestSignalName => "FS1SEN", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tSENS, SetupLow => tSENS, HoldHigh => tSENH, HoldLow => tSENH, CheckEnabled => Offs_Ser_Load_Modeint = '1', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS1SEN_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS1SEN_CLKA); Violation := Pviol_CLKA OR Pviol_CLKB OR Tviol_A0_CLKA OR TViol_B0_CLKB OR Tviol_CSANeg_CLKA OR Tviol_WRA_CLKA OR Tviol_ENA_CLKA OR Tviol_MBA_CLKA OR Tviol_CSBNeg_CLKB OR Tviol_WRB_CLKB OR Tviol_ENB_CLKB OR Tviol_MBB_CLKB OR Tviol_RSTNeg_CLKA OR Tviol_RSTNeg_CLKB OR Tviol_FS0SD_RSTNeg OR Tviol_FS1SEN_RSTNeg OR Tviol_FS0SD_CLKA OR Tviol_FS1SEN_CLKA OR Tviol_RFM_CLKB OR Tviol_RTM_CLKB ; ASSERT Violation = '0' REPORT InstancePath & partID & " : signal values may be" & " incorret due timing violation(s)" SEVERITY Warning; END IF; END PROCESS TimingChecks; -------------------------------------------------------------------------------- -- Functionality Section -- -------------------------------------------------------------------------------- ------------------------------------------------------------------------------ -- Reset ------------------------------------------------------------------------------ -- Initial Reset - ------------------------------------------------------------------------------ Init_Reset: PROCESS (RSTNeg) BEGIN IF (RSTNeg = '0') THEN MRSDoneint <= '1'; END IF; END PROCESS; ------------------------------------------------------------------------------ -- Internal Reset Signal ------------------------------------------------------------------------------ Internal_Reset: PROCESS (RSTNeg,MRSDoneint) BEGIN IF (MRSDoneint = '1') THEN RST1int<=RSTNeg AND MRSDoneint; END IF; END PROCESS; ------------------------------------------------------------------------------ -- Count Clocks during RSTNeg ------------------------------------------------------------------------------ Count_CLK1: PROCESS (CLKA, CLKB, RST1int) BEGIN IF RST1int'Event THEN IF (RST1int = '0')OR (RST1int'LAST_VALUE = '0') THEN IF RST1int'LAST_VALUE = '0' THEN IF (CountCLKA1int < 4) OR (CountCLKB1int < 4) THEN ASSERT FALSE REPORT InstancePath & partID & ": During RESET should be 4 posedges on CLKA, CLKB"; END IF; END IF; CountCLKA1int <= 0; CountCLKB1int <= 0; END IF; ELSIF MRSDoneint = '1' THEN IF CLKA'EVENT AND CLKA = '1' THEN IF Offs_Ser_Load_Modeint = '0' THEN IF CountCLKA1int < 4 THEN CountCLKA1int <= CountCLKA1int + 1; END IF; ELSE IF (CountLoadOffsetint = Offs_Ser_Number - 1) AND (FS1SEN = '0') THEN -- Current CLKA is the last while Offset Loading CountCLKA1int <= 1; END IF; END IF; END IF; IF CLKB'EVENT AND CLKB = '1' THEN IF CountCLKB1int < 4 THEN CountCLKB1int <= CountCLKB1int + 1; END IF; END IF; END IF; END PROCESS Count_CLK1 ; ------------------------------------------------------------------------------ -- Load Almost-Empty / Almost-Full Offsets ------------------------------------------------------------------------------ Store_Almost_Flags_Offs: PROCESS (RST1int, CLKA) VARIABLE Offs: NATURAL RANGE 0 TO FIFOSize-4; VARIABLE FS: std_logic_vector(1 DOWNTO 0); VARIABLE FlagStart: Boolean; BEGIN -- Fixed Offset for FIFO IF RST1int'Event AND (RST1int = '1') AND (RST1int'LAST_VALUE = '0') THEN FS := (FS1SEN & FS0SD); IF (FS /= "00") THEN CASE FS IS WHEN "01" => Offs := 8; WHEN "10" => Offs := 64; WHEN OTHERS => NULL; END CASE; X1int <= Offs; Y1int <= Offs; END IF; END IF; -- Set Parallel/Serial Offset Loading Mode IF RST1int'Event AND (RST1int = '1') AND (RST1int'LAST_VALUE = '0') THEN FS := (FS1SEN & FS0SD); IF (FS = "00") THEN Offs_Par_Load_Modeint <= '1'; CountLoadOffsetint <= 0; ELSIF (FS = "11")THEN Offs_Ser_Load_Modeint <= '1'; CountLoadOffsetint <= 0; FlagStart := False; END IF; END IF; -- Parallel Offset Loading Mode IF Offs_Par_Load_Modeint = '1' THEN IF CLKA'EVENT AND CLKA = '1' THEN IF (ENA = '1') AND (CountCLKA1int >= 2) THEN------------ zathem 2??-?? CountLoadOffsetint <= CountLoadOffsetint + 1; CASE CountLoadOffsetint IS WHEN 0 => Y1int <= to_nat(A_ipd); WHEN 1 => X1int <= to_nat(A_ipd); Offs_Par_Load_Modeint <= '0'; IF (Y1int=0 )OR (Y1int>Offs_Val_Limit)THEN ASSERT FALSE REPORT InstancePath & partID & " Invalid Offset Value loaded"; END IF; WHEN OTHERS => NULL; END CASE; END IF; END IF; END IF; -- Serial Offset Loading Mode IF Offs_Ser_Load_Modeint = '1' THEN IF CLKA'EVENT AND CLKA = '1' THEN IF FlagStart = FALSE THEN FlagStart := TRUE; Y1int <= 0; X1int <= 0; ELSIF (FS1SEN = '0') THEN CountLoadOffsetint <= CountLoadOffsetint + 1; CASE CountLoadOffsetint IS WHEN 0 TO OffsetSize-1 => Y1int <= Y1int*2 + to_nat(FS0SD); WHEN OffsetSize TO OffsetSize*2-1 => X1int <= X1int*2 + to_nat(FS0SD); IF CountLoadOffsetint = OffsetSize*2-1 THEN Offs_Ser_Load_Modeint <= '0'; IF (Y1int=0 )OR (Y1int>Offs_Val_Limit)THEN ASSERT FALSE REPORT InstancePath & partID & " Invalid Offset Value loaded"; END IF; END IF; WHEN OTHERS => NULL; END CASE; END IF; END IF; END IF; END PROCESS Store_Almost_Flags_Offs ; ------------------------------------------------------------------------------ -- FIFO1 ------------------------------------------------------------------------------ -- Drive Write Enable Signal ------------------------------------------------------------------------------ Drive_EnWrFIFO1: PROCESS(ENA, CSANeg, WRA, MBA, Offs_Par_Load_Modeint, Offs_Ser_Load_Modeint) BEGIN IF (ENA = '1') AND (CSANeg = '0') AND (WRA = '1') AND (MBA = '0') AND (Offs_Par_Load_Modeint = '0') AND (Offs_Ser_Load_Modeint = '0') THEN EnWrFIFO1int <= '1'; ELSE EnWrFIFO1int <= '0'; END IF; END PROCESS; ------------------------------------------------------------------------------ -- FIFO1 Write Data to Input Register from Port-A ------------------------------------------------------------------------------ -- FIFO1 Write Data to FIFO ------------------------------------------------------------------------------ InputReg1_Write_Data: PROCESS (CLKA) VARIABLE InputReg1int : FIFOWord := (OTHERS => 'X'); VARIABLE InputReg1Readyint : std_ulogic; VARIABLE WritePtr1Nextint: Natural RANGE 0 TO FIFOSize-1; BEGIN IF RST1int = '0' THEN WritePtr1int <= 0; WritePtr1int_add <= '0'; ELSIF CLKA'Event AND CLKA = '1' THEN IF (EnWrFIFO1int = '1') AND (IRint = '1') THEN InputReg1int := A_ipd ; InputReg1Readyint := '1'; ELSE InputReg1Readyint := '0'; END IF; IF InputReg1Readyint = '1' THEN FIFOMemory1int (WritePtr1int) <= InputReg1int; WritePtr1Nextint := (WritePtr1int + 1) MOD FIFOSize; WritePtr1int <= WritePtr1Nextint; IF WritePtr1Nextint = 0 THEN WritePtr1int_add <= NOT WritePtr1int_add; END IF; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------ -- FIFO1 Drive Full Flag IR ------------------------------------------------------------------------------ -- Description based on IDT Data and gate-level model simulatiion -- Translated part of Verilog model ------------------------------------------------------------------------------ -- state of WRITE TO FIFO 1 STATE2A <= EnWrFIFO1int; -- IRA flip-flops Drive_FIRA: PROCESS (CLKA) BEGIN IF CLKA'EVENT AND CLKA = '1' THEN IF (NOT ((F1IRA='1') AND (F2IRA='1') AND (RST1int = '1'))) OR (STATE2A = '1') THEN F1IRA <= WrFIRA; END IF; IF (NOT ((F2IRA='1') AND (RST1int = '1')) AND (Offs_Ser_Load_Modeint = '0')) OR (STATE2A = '1') THEN IF (RST1int = '0') AND (FS0SD = '1') AND (FS1SEN = '1') THEN F2IRA <= '0'; ELSE F2IRA <= F1IRA; END IF; END IF; END IF; END PROCESS; IRint <= F2IRA; -- IRA data input B0C1IRA <= 2 WHEN (F1IRA='1') AND (F2IRA='1') ELSE 1 WHEN (F1IRA='1') OR (F2IRA='1') ELSE 0; ReadPtr1_sel_int <= ReadPtr1int WHEN RetModeBegint='0' ELSE ShadowReadPtrint; ReadPtr1_sel_int_add <= ReadPtr1int_add WHEN RetModeBegint='0' ELSE ShadowReadPtrint_add; WrIRA <= TRANSPORT '1' AFTER tdevice_SKEW1 WHEN ( (((WritePtr1int - ReadPtr1_sel_int) MOD FIFOSize) + B0C1IRA) < FIFOSize) AND ( (WritePtr1int /= ReadPtr1_sel_int) OR (WritePtr1int_add = ReadPtr1_sel_int_add) ) ELSE '0'; WrFIRA <= WrIRA AND RST1int; ------------------------------------------------------------------------------ -- FIFO1 Drive Almost Full Flag AF ------------------------------------------------------------------------------ -- Description based on IDT Data and gate-level model simulatiion -- Translated part of Verilog model ------------------------------------------------------------------------------ IRHdl2 <= NOT (Offs_Par_Load_Modeint OR Offs_Ser_Load_Modeint); MRSTl1 <= RSTNeg; PRSTl1 <= '1'; AFlGen_A <= TRANSPORT '0' AFTER tdevice_SKEW2 WHEN (IRHdl2 = '1') AND ( ( ( (((WritePtr1int - ReadPtr1_sel_int) MOD FIFOSize) + Y1int + to_nat(AF1l_A) + to_nat(AF2l_A)) >= FIFOSize) ) OR ( (WritePtr1int = ReadPtr1_sel_int) AND (WritePtr1int_add /= ReadPtr1_sel_int_add) ) ) ELSE '1' AFTER tdevice_SKEW2 ; Drive_AF1l_A: PROCESS(CLKA, MRSTl1, PRSTl1) BEGIN IF (MRSTl1 = '0') OR (PRSTl1 = '0') THEN AF1l_A <= '1'; ELSIF CLKA'EVENT AND CLKA = '1' THEN IF (AFlA = '0') OR (AF1l_A = '0') OR ((EnWrFIFO1int = '1') AND (IRint = '1')) THEN AF1l_A <= AFlGen_A; END IF; END IF; END PROCESS; Drive_AFlA: PROCESS(CLKA, MRSTl1, PRSTl1) BEGIN IF (MRSTl1 = '0') OR (PRSTl1 = '0') THEN AFlA <= '1'; ELSIF CLKA'EVENT AND CLKA = '1' THEN IF (AFlA = '0') OR (RcvEn_AF_A = '1') OR ((EnWrFIFO1int = '1') AND (IRint = '1')) THEN AFlA <= AF1l_A; END IF; END IF; END PROCESS; AF2l_A <= AFLA AND NOT RcvEn_AF_A; Drive_RcvEn_AF_A: PROCESS(CLKA) BEGIN IF CLKA'EVENT AND CLKA = '1' THEN IF( BCmpEn_AF_A = '1') AND (AFlA /= AF1l_A) AND (MRSTl1 = '1') AND (PRSTl1 = '1') THEN RcvEn_AF_A <= '1'; ELSE RcvEn_AF_A <= '0'; END IF; END IF; END PROCESS; Rd_Ptr1 <= to_slv(ReadPtr1_sel_int, FIFOPOWER); BCmpEn_AF_A <= '1' WHEN (Rd_Ptr1(0) = AF_A(0)) AND (Rd_Ptr1(1) = AF_A(1)) ELSE '0'; AF_A <= to_slv (WritePtr1int + Y1int, FIFOPOWER); AFNeg_zd <= AFlA; ------------------------------------------------------------------------------ -- Drive Read Enable Signal ------------------------------------------------------------------------------ Drive_EnRdFIFO1: PROCESS(ENB, CSBNeg, WRB, MBB, Offs_Par_Load_Modeint, Offs_Ser_Load_Modeint) BEGIN IF (ENB = '1') AND (CSBNeg = '0') AND (WRB = '1') AND (MBB = '0') AND (Offs_Par_Load_Modeint = '0') AND (Offs_Ser_Load_Modeint = '0') THEN EnRdFIFO1int <= '1'; ELSE EnRdFIFO1int <= '0'; END IF; END PROCESS; ------------------------------------------------------------------------------ -- FIFO1 Read Data to Output Register with Port-B ------------------------------------------------------------------------------ FIFO1_Read_Data: PROCESS (CLKB, RST1int) VARIABLE Data: FIFOWord; VARIABLE ReadPtr1Nextint: Natural RANGE 0 TO FIFOSize-1; BEGIN IF RST1int = '0' THEN ReadPtr1int <= 0; ReadPtr1int_add <= '0'; ELSIF CLKB'Event AND CLKB = '1' THEN IF ((ORB_zd = '1') AND (EF2l_B = '1') AND (EnRdFIFO1int = '1') AND( (WritePtr1int /=ReadPtr1int) OR ((WritePtr1int =ReadPtr1int) AND (IR_zd='0')))) OR ((ORint = '0') AND (EFNegint = '1')) THEN Data := FIFOMemory1int (ReadPtr1int); OutputReg1int <= Data; ReadPtr1Nextint := (ReadPtr1int + 1) MOD FIFOSize; ReadPtr1int <= ReadPtr1Nextint; IF ReadPtr1Nextint = 0 THEN ReadPtr1int_add <= NOT ReadPtr1int_add; END IF; END IF; IF (RFM='1') AND (RTM='1') AND (RetModeBegint = '1') AND ( Ret2int='1') THEN --Retransmit repeat begin!!!!!!! Data := FIFOMemory1int (ShadowReadPtrint); OutputReg1int <= Data; ReadPtr1Nextint := (ShadowReadPtrint + 1) MOD FIFOSize; ReadPtr1int <= ReadPtr1Nextint; IF ReadPtr1Nextint = 0 THEN ReadPtr1int_add <= NOT ShadowReadPtrint_add; ELSE ReadPtr1int_add <= ShadowReadPtrint_add; END IF; END IF; END IF; END PROCESS FIFO1_Read_Data ; ------------------------------------------------------------------------------ -- FIFO1 Save ReadPtr1int then Retransmit Mode is Set in ShadowReadPtrint ------------------------------------------------------------------------------ FIFO1_Save_ReadPtr1int: PROCESS (CLKB,RST1int) VARIABLE ShadowReadPtr1Nextint: Natural RANGE 0 TO FIFOSize-1; BEGIN IF RST1int = '0' THEN ShadowReadPtrint <= 0; ShadowReadPtrint_add <= '0'; ELSIF CLKB'Event AND CLKB = '1' THEN IF ( RTM='1') AND (ORB_zd ='1' ) AND ( RetModeBegint = '0') THEN ShadowReadPtr1Nextint := (ReadPtr1int - 1) MOD FIFOSize; ShadowReadPtrint <= ShadowReadPtr1Nextint; IF ReadPtr1int = 0 THEN ShadowReadPtrint_add <= NOT ReadPtr1int_add; ELSE ShadowReadPtrint_add <= ReadPtr1int_add; END IF; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------ -- FIFO1 Drive Empty Flag ORB ------------------------------------------------------------------------------ -- Description based on IDT Data and gate-level model simulatiion -- Translated part of Verilog model ------------------------------------------------------------------------------ STATE1B <= EnRdFIFO1int; BYPB <=F2ORB WHEN OPTEO ='1'ELSE F1ORB; BEFWFTl <= '0'; -- FWFT mode Drive_FORB: PROCESS (CLKB, RST1int, Eql_ORB) BEGIN IF CLKB'EVENT AND CLKB = '1' THEN IF RFM = '1' THEN ORint <= '1'; ELSIF ((En_ORB = '1') AND (EN2_ORB = '1') ) OR ((EnRdFIFO1int = '1') AND (ORint = '1') AND (EF2l_B = '0') AND (Eq_ORB = '1')) OR (ORint = '0') OR (RST1int = '0') THEN ORint <= EF2l_B; END IF; END IF; IF RFM = '1' THEN EF1l_B <= '1'; EF2l_B <= '1'; ELSIF (CLKB'EVENT AND CLKB = '1') OR Eql_ORB'EVENT THEN IF Eql_ORB = '0' THEN EF2l_B <= '0'; ELSIF ((En_ORB = '1') AND (EN2_ORB = '1') ) OR (ORint = '0') OR (EF2l_B = '0') OR (RST1int = '0') THEN EF2l_B <= EF1l_B; END IF; IF Eql_ORB = '0' THEN EF1l_B <= '0'; ELSIF ((En_ORB = '1') AND (EN2_ORB = '1') ) OR (ORint = '0') OR (EF1l_B = '0') OR (EF2l_B = '0') OR (RST1int = '0') THEN EF1l_B <= EFlGen_B; END IF; END IF; END PROCESS; RDP_1 <= (ReadPtr1int + to_nat(EF1l_B) + to_nat(EF2l_B)) MOD FIFOSIZE; EFlGen_B <= TRANSPORT '0' AFTER tdevice_SKEW1 WHEN (RST1int = '0') OR ((WritePtr1int = RDP_1) AND (MRSDoneint = '1')) ELSE '1' AFTER tdevice_SKEW1 WHEN MRSDoneint = '1' ELSE 'X'; EFNegint <= EF2l_B OR EF2l_B_add; EF2l_B_add <= '0'; Drive_En_ORB: PROCESS (MRSTl1, PRSTl1, CLKB, IRHdl2, EnRdFIFO1int, EF2l_B) BEGIN IF (MRSTl1 = '0') OR (PRSTl1 = '0') THEN En_ORB <= '0'; ELSIF (CLKB = '0') THEN En_ORB <= IRHdl2 AND ((NOT ORint AND EF2l_B) OR (EnRdFIFO1int AND EF2l_B)); END IF; END PROCESS; En2_ORB <= '1'; AFTEn_AE_B <= ORB_B2 AND ORint; BMAft_ORB <= '0'; Eql_ORB <= '1'; Eq_ORB <= '1'; ------------------------------------------------------------------------------ -- FIFO1 Drive Almost Empty Flag AE ------------------------------------------------------------------------------ -- Description based on IDT Data and gate-level model simulatiion -- Translated part of Verilog model ------------------------------------------------------------------------------ ORB_B2 <= NOT ORint; AElGen_B <= TRANSPORT '0' AFTER tdevice_SKEW2 WHEN (IRHdl2 = '0') OR ( ( (((WritePtr1int - ReadPtr1int) MOD FIFOSize) ) <= X1int + to_nat(AE1l_B) + to_nat(AE2l_B)) AND ( (WritePtr1int_add = ReadPtr1int_add) OR (WritePtr1int /= ReadPtr1int) ) ) ELSE '1' AFTER tdevice_SKEW2 ; Drive_AE1l_B: PROCESS(CLKB, MRSTl1, PRSTl1) BEGIN IF (MRSTl1 = '0') OR (PRSTl1 = '0') THEN AE1l_B <= '0'; ELSIF CLKB'EVENT AND CLKB = '1' THEN IF (AElB = '0') OR (AE1l_B = '0') OR (AFTEn_AE_B = '1') OR ((En_ORB = '1') AND (En2_ORB = '1')) THEN AE1l_B <= AElGen_B; END IF; END IF; END PROCESS; Drive_AElB: PROCESS(CLKB, MRSTl1, PRSTl1) BEGIN IF (MRSTl1 = '0') OR (PRSTl1 = '0') THEN AElB <= '0'; ELSIF CLKB'EVENT AND CLKB = '1' THEN IF (AElB = '0') OR (RcvEn_AE_B = '1') OR ((En_ORB = '1') AND (En2_ORB = '1')) THEN AElB <= AE1l_B; END IF; END IF; END PROCESS; AE2l_B <= AELB AND NOT RcvEn_AE_B; Drive_RcvEn_AE_B: PROCESS(CLKB) BEGIN IF CLKB'EVENT AND CLKB = '1' THEN IF( BCmpEn_AE_B = '1') AND (AElB /= AE1l_B) AND (MRSTl1 = '1') AND (PRSTl1 = '1') THEN RcvEn_AE_B <= '1'; ELSE RcvEn_AE_B <= '0'; END IF; END IF; END PROCESS; Wr_Ptr1 <= to_slv(WritePtr1int, FIFOPOWER); BCmpEn_AE_B <= '1' WHEN (Wr_Ptr1(0) = AE_B(0)) AND (Wr_Ptr1(1) = AE_B(1)) ELSE '0'; AE_B <= to_slv (ReadPtr1int + X1int, FIFOPOWER); AENeg_zd <= AElB; ------------------------------------------------------------------------------ -- Mail1 Register ------------------------------------------------------------------------------ -- Drive Read / Write Enable Signals ------------------------------------------------------------------------------ Drive_EnWrMail1: PROCESS(ENA, CSANeg, WRA, MBA, MBF1Neg_zd) BEGIN IF (ENA = '1') AND (CSANeg = '0') AND (WRA = '1') AND (MBA = '1') AND (MBF1Neg_zd = '1')THEN EnWrMail1int <= '1'; ELSE EnWrMail1int <= '0'; END IF; END PROCESS; Drive_EnRdMail1: PROCESS(ENB, CSBNeg, MBB, WRB) BEGIN IF (ENB = '1') AND (CSBNeg = '0') AND (MBB = '1') AND (WRB = '1') THEN EnRdMail1int <= '1'; ELSE EnRdMail1int <= '0'; END IF; END PROCESS; ------------------------------------------------------------------------------ -- Write Data to Mail1 Register from Port-A ------------------------------------------------------------------------------ Mail1_Write_Data: PROCESS (CLKA, RST1int) BEGIN IF RST1int = '0' THEN Mail1int <= (OTHERS => '0'); ELSIF CLKA'Event AND CLKA = '1' THEN IF EnWrMail1int = '1' THEN Mail1int <= A_ipd; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------ -- Drive MailBox1 Full Flag ------------------------------------------------------------------------------ Drive_MBF1: PROCESS (CLKA, CLKB, RST1int ) BEGIN IF RST1int = '0' THEN -- Reset MBF1Neg_zd<='1'; ELSIF CLKA'EVENT AND CLKA = '1' THEN -- Write IF EnWrMail1int = '1' THEN MBF1Neg_zd<='0'; END IF; ELSIF CLKB'EVENT AND CLKB = '1' THEN -- Read IF EnRdMail1int = '1' THEN MBF1Neg_zd<='1'; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------ -- Mail2 Register ------------------------------------------------------------------------------ -- Drive Read / Write Enable Signals ------------------------------------------------------------------------------ Drive_EnWrMail2: PROCESS(ENB, MBB, WRB, CSBNeg, MBF2Neg_zd) BEGIN IF (ENB = '1') AND (MBB = '1') AND (WRB = '0') AND (CSBNeg = '0') AND (MBF2Neg_zd = '1') THEN EnWrMail2int <= '1'; ELSE EnWrMail2int <= '0'; END IF; END PROCESS; Drive_EnRdMail2: PROCESS(ENA, CSANeg, WRA, MBA) BEGIN IF (ENA = '1') AND (CSANeg = '0') AND (WRA = '0') AND (MBA = '1') THEN EnRdMail2int <= '1'; ELSE EnRdMail2int <= '0'; END IF; END PROCESS; ------------------------------------------------------------------------------ -- Write Data to Mail2 Register from Port-B ------------------------------------------------------------------------------ Mail2_Write_Data: PROCESS (CLKB, RST1int) BEGIN IF RST1int = '0' THEN Mail2int <= (OTHERS => '0'); ELSIF CLKB'Event AND CLKB = '1' THEN IF EnWrMail2int = '1' THEN Mail2int <= B_ipd ; END IF; END IF; END PROCESS Mail2_Write_Data ; ------------------------------------------------------------------------------ -- Drive MailBox2 Full Flag ------------------------------------------------------------------------------ Drive_MBF2: PROCESS (CLKA, CLKB, RST1int) BEGIN IF RST1int = '0' THEN -- Reset MBF2Neg_zd<='1'; ELSIF CLKB'EVENT AND CLKB = '1' THEN -- Write IF EnWrMail2int = '1' THEN MBF2Neg_zd<='0'; END IF; ELSIF CLKA'EVENT AND CLKA = '1' THEN -- Read IF EnRdMail2int = '1' THEN MBF2Neg_zd<='1'; END IF; END IF; END PROCESS Drive_MBF2; ------------------------------------------------------------------------------ -- PORT A Output ------------------------------------------------------------------------------ Drive_A: PROCESS (CSANeg, WRA, MBA, Mail2int, Offs_Par_Load_Modeint) BEGIN IF (CSANeg = '0') AND (WRA = '0') AND (MBA = '1') -- 01/07/99 THEN A_zd <= Mail2int; ELSIF (CSANeg = '1') OR (WRA = '1') OR (Offs_Par_Load_Modeint = '1') THEN A_zd <= (OTHERS => 'Z'); ELSE A_zd <= (OTHERS => 'X'); END IF; END PROCESS Drive_A; ------------------------------------------------------------------------------ -- PORT B Output ------------------------------------------------------------------------------ Drive_B: PROCESS (CSBNeg, WRB, MBB, Mail1int, OutputReg1int) BEGIN IF (CSBNeg = '0') AND (WRB = '1') THEN IF MBB = '0' THEN B_zd <= OutputReg1int; ELSIF MBB = '1' THEN B_zd <= Mail1int; ELSE B_zd <= (OTHERS => 'X'); END IF; ELSIF (CSBNeg = '1') OR (WRB = '0') THEN B_zd <= (OTHERS => 'Z'); ELSE B_zd <= (OTHERS => 'X'); END IF; END PROCESS Drive_B; ------------------------------------------------------------------------------ -- Drive Full / Empty flags ------------------------------------------------------------------------------ Drive_Output_Flags: PROCESS ( IRint, ORint ) BEGIN ORB_zd <= ORint; IR_zd <= IRint; END PROCESS Drive_Output_Flags; ----------------------------------------------------------------------- --Drive Retransmit Mode Begin Signal-----RetModeBegint -------------------------------------------------------------------------------- Drive_RetModeBeg: PROCESS(CLKB, RTM,RFM, RST1int,ORB_zd) BEGIN IF RST1int = '0' THEN RetModeBegint <= '0';Ret1int<= '0';Ret2int<= '0'; ELSIF CLKB'Event AND CLKB = '1' THEN IF( RTM='1') AND (ORB_zd='1' ) THEN --RFM--?? RetModeBegint <= '1'; ELSIF ( RTM='0') THEN RetModeBegint <= '0';Ret1int<= '0';Ret2int<= '0'; END IF; --For check min retr. loop length(it need 2 reading IF(EnRdFIFO1int = '1')AND (RetModeBegint = '1') AND (ORB_zd='1' ) THEN Ret1int<= RetModeBegint; Ret2int<= Ret1int; END IF; IF (( RFM='1')) AND ( Ret2int='1') AND (RetModeBegint = '1') AND ( RTM='1') THEN Ret1int<= '0'; Ret2int<= '0'; END IF; IF (( RFM='1')) AND ( Ret2int='0') AND (RetModeBegint = '1') AND ( RTM='1') THEN ASSERT FALSE REPORT InstancePath & partID & ": During Retransmit Mode should be retransmit Minimum three words"; RetModeBegint <= '0';Ret1int<= '0';Ret2int<= '0'; END IF; END IF; END PROCESS Drive_RetModeBeg ; -------------------------------------------------------------------------------- -- Path Delay Section -- -------------------------------------------------------------------------------- -- Path delay for A PathDelaysA_Gen: FOR i IN 35 DOWNTO 0 GENERATE PathDelayA: PROCESS (A_zd(i)) VARIABLE A_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z ( OutSignal => A(i), OutSignalName => "A", OutTemp => A_zd(i), Mode => VitalInertial, GlitchData => A_GlitchData, Paths => ( 0 => (InputChangeTime => CSANeg'LAST_EVENT, PathDelay => tEN_DIS, PathCondition => TRUE), 1 => (InputChangeTime => WRA'LAST_EVENT, PathDelay => tEN_DIS, PathCondition => TRUE), 2 => (InputChangeTime => CLKB'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tPMR), PathCondition => CSANeg = '0' AND WRA = '0' AND MBA = '1') )); END PROCESS; END GENERATE; -- Path delay for B PathDelaysB_Gen: FOR i IN 35 DOWNTO 0 GENERATE PathDelayA: PROCESS (B_zd(i)) VARIABLE B_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z ( OutSignal => B(i), OutSignalName => "B", OutTemp => B_zd(i), Mode => VitalInertial, GlitchData => B_GlitchData, Paths => ( 0 => (InputChangeTime => CSBNeg'LAST_EVENT, PathDelay => tEN_DIS, PathCondition => TRUE), 1 => (InputChangeTime => WRB'LAST_EVENT, PathDelay => tEN_DIS, PathCondition => TRUE), 2 => (InputChangeTime => MBB'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tMDV), PathCondition => TRUE), 3 => (InputChangeTime => CLKA'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tPMR), PathCondition => CSBNeg = '0' AND MBB = '1'), 4 => (InputChangeTime => CLKB'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tA), PathCondition => (CSBNeg = '0' AND WRB = '1' AND MBB = '0')))); END PROCESS; END GENERATE; -- Path delay for AENeg PathDelayAENeg: PROCESS (AENeg_zd) VARIABLE AENeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => AENeg, OutSignalName => "AENeg", OutTemp => AENeg_zd, Mode => VitalInertial, GlitchData => AENeg_GlitchData, Paths => ( 0 => (InputChangeTime => RST1int'LAST_EVENT, PathDelay => tRSF, PathCondition => RST1int = '0'), 1 => (InputChangeTime => CLKB'LAST_EVENT, PathDelay => tPAE, PathCondition => RST1int = '1'))); END PROCESS; -- Path delay for AFNeg -------------------------------------sdelano PathDelayAFNeg: PROCESS (AFNeg_zd) VARIABLE AFNeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => AFNeg, OutSignalName => "AFNeg", OutTemp => AFNeg_zd, Mode => VitalInertial, GlitchData => AFNeg_GlitchData, Paths => ( 0 => (InputChangeTime => RST1int'LAST_EVENT, PathDelay => tRSF, PathCondition => RST1int = '0'), 1 => (InputChangeTime => CLKA'LAST_EVENT, PathDelay => tPAF, PathCondition => RST1int = '1'))); END PROCESS; -- Path delay for ORB PathDelayORB: PROCESS (ORB_zd) VARIABLE ORB_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => ORB, OutSignalName => "ORB", OutTemp => ORB_zd, Mode => VitalInertial, GlitchData => ORB_GlitchData, Paths => ( 0 => (InputChangeTime => CLKB'LAST_EVENT, PathDelay => tPOR, PathCondition => TRUE))); END PROCESS; -- Path delay for IR PathDelayIR: PROCESS (IR_zd) VARIABLE IR_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => IR, OutSignalName => "IR", OutTemp => IR_zd, Mode => VitalInertial, GlitchData => IR_GlitchData, Paths => ( 0 => (InputChangeTime => CLKA'LAST_EVENT, PathDelay => tPIR, PathCondition => TRUE))); END PROCESS; -- Path delay for MBF1Neg PathDelayMBF1Neg: PROCESS (MBF1Neg_zd) VARIABLE MBF1Neg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => MBF1Neg, OutSignalName => "MBF1Neg", OutTemp => MBF1Neg_zd, Mode => VitalInertial, GlitchData => MBF1Neg_GlitchData, Paths => ( 0 => (InputChangeTime => RST1int'LAST_EVENT, PathDelay => tRSF, PathCondition => RST1int = '0'), 1 => (InputChangeTime => CLKA'LAST_EVENT, PathDelay => tPMF, PathCondition => RST1int = '1' AND MBF1Neg_zd = '0'), 2 => (InputChangeTime => CLKB'LAST_EVENT, PathDelay => tPMF, PathCondition => RST1int = '1' AND MBF1Neg_zd = '1'))); END PROCESS; -- Path delay for MBF2Neg PathDelayMBF2Neg: PROCESS (MBF2Neg_zd) VARIABLE MBF2Neg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 ( OutSignal => MBF2Neg, OutSignalName => "MBF2Neg", OutTemp => MBF2Neg_zd, Mode => VitalInertial, GlitchData => MBF2Neg_GlitchData, Paths => ( 0 => (InputChangeTime => RST1int'LAST_EVENT, PathDelay => tRSF, PathCondition => RST1int = '0'), 1 => (InputChangeTime => CLKA'LAST_EVENT, PathDelay => tPMF, PathCondition => RST1int = '1' AND MBF2Neg_zd = '1'), 2 => (InputChangeTime => CLKB'LAST_EVENT, PathDelay => tPMF, PathCondition => RST1int = '1' AND MBF2Neg_zd = '0'))); END PROCESS; END BLOCK VitalBehavior; END vhdl_behavioral;