-------------------------------------------------------------------------------- -- File name : idt72271.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998 Integrated Device Technology; http://www.idt.com/ -- Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT -- and supported by Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no -- warranty with respect to the information contained herein. IDT DISCLAIMS -- AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE -- ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN -- NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN -- CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, -- CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR -- APPLICATION OF THE VHDL model. Further, IDT reserves the right to make -- changes without notice to any product herein to improve reliability, -- function, or design. IDT does not convey any license under patent rights -- or any other intellectual property rights, including those of third parties. -- IDT is not obligated to provide maintenance or support for the licensed VHDL -- model. -- -- MODIFICATION HISTORY : -- -- version | author | mod date: | changes made -- V1.0 | Vladimir V. Erokhin | 98 MAY 10 | initial coding -- V1.1 | R. Munden | 02 MAY 19 | licensing changed to GPL -------------------------------------------------------------------------------- -- -- PART DESCRIPTION : -- -- Library: IDT_FIFO -- Technology: CMOS -- Part: IDT72271 -- -- Descripton: SuperSync FIFO 32768 x 9 -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.vital_primitives.ALL; USE ieee.vital_timing.ALL; LIBRARY fmf; USE fmf.ff_package.ALL; USE fmf.gen_utils.ALL; USE fmf.conversions.to_nat; USE fmf.conversions.to_slv; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -- -------------------------------------------------------------------------------- ENTITY IDT72271 IS GENERIC ( -- tipd delays: interconnect path delays -- (there must be one generic for each input pin) tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_MRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_PRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_FWFTSI : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK : VitalDelayType01 := VitalZeroDelay01; tipd_WENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_SENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_FS : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays -- tRSF (applicable for all flags and Q) tpd_MRSNeg_EFORNeg : VitalDelayType01 := UnitDelay01; tpd_MRSNeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tA (applicable for RCLKxQ-valid tpd_RCLK_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tOLZ/tOE/tOHZ tpd_OENeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tWFF tpd_WCLK_FFIRNeg : VitalDelayType01 := UnitDelay01; -- tREF tpd_RCLK_EFORNeg : VitalDelayType01 := UnitDelay01; -- tPAF tpd_WCLK_PAFNeg : VitalDelayType01 := UnitDelay01; -- tPAE tpd_RCLK_PAENeg : VitalDelayType01 := UnitDelay01; -- tHF (applicable for both WCLK and RCLK) tpd_RCLK_HFNeg : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths -- tperiod_RCLK_posedgeH tpw_RCLK_posedge : VitalDelayType := UnitDelay; -- tperiod_RCLK_posedgeL tpw_RCLK_negedge : VitalDelayType := UnitDelay; -- tWCLKH tpw_WCLK_posedge : VitalDelayType := UnitDelay; -- tWCLKL tpw_WCLK_negedge : VitalDelayType := UnitDelay; -- tRS (applicable for both MRS and PRS) tpw_MRSNeg_negedge : VitalDelayType := UnitDelay; tpw_PRSNeg_negedge : VitalDelayType := UnitDelay; -- tperiod values: min calculated as 1/max freq -- tperiod_RCLK_posedge tperiod_RCLK_posedge : VitalDelayType := UnitDelay; -- tWCLK tperiod_WCLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS (applicable for D/WCLK) tsetup_D0_WCLK_noedge_posedge : VitalDelayType := UnitDelay; tsetup_FWFTSI_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tENS (applicable for both WEN/WCLK and REN/RCLK) tsetup_RTNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; tsetup_RENNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; tsetup_SENNeg_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tLDS (applicable for LDNeg/WCLK) tsetup_LDNeg_WCLK_noedge_posedge : VitalDelayType := UnitDelay; tsetup_LDNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tRSS (applicable for REN,WEN,LD,RT,SEN/MRS and REN,WEN,RT,SEN/PRS) tsetup_WENNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_RENNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_LDNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_RTNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_SENNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_WENNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_RENNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_RTNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_SENNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; -- tFWFT (applicable for FWFTSI\MRSNeg tsetup_FWFTSI_MRSNeg_noedge_negedge : VitalDelayType := UnitDelay; -- tRTS tsetup_WENNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH (applicable for D/WCLK) thold_D0_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tENH (applicable for both WEN/WCLK and REN/RCLK) thold_RTNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; thold_RENNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; thold_SENNeg_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tLDH (applicable for LDNeg/WCLK) thold_LDNeg_WCLK_noedge_posedge : VitalDelayType := UnitDelay; thold_LDNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- trecovery values: recovery times -- tRSR (applicable for REN,WEN,FWFTSI,LD/MRS and REN,WEN/PRS) thold_LDNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; thold_FWFTSI_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; thold_RENNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; thold_WENNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; thold_RENNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; thold_WENNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; -- tskew values: skew times tdevice_SKEW1 : VitalDelayType := UnitDelay; tdevice_SKEW2 : VitalDelayType := UnitDelay; InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN std_logic := 'X'; ----------------------------- D1 : IN std_logic := 'X'; -- D2 : IN std_logic := 'X'; -- D3 : IN std_logic := 'X'; -- D4 : IN std_logic := 'X'; -- D5 : IN std_logic := 'X'; -- D6 : IN std_logic := 'X'; -- D7 : IN std_logic := 'X'; -- D8 : IN std_logic := 'X'; -- MRSNeg : IN std_logic := 'X'; -- Master Reset PRSNeg : IN std_logic := 'X'; -- Partial Reset RTNeg : IN std_logic := 'X'; -- Retransmit FWFTSI : IN std_logic := 'X'; -- First Word Fall Trough/Serial In WCLK : IN std_logic := 'X'; -- Write Clock WENNeg : IN std_logic := 'X'; -- Write Enable RCLK : IN std_logic := 'X'; -- Read Clock RENNeg : IN std_logic := 'X'; -- Read Enable OENeg : IN std_logic := 'X'; -- Output Enable SENNeg : IN std_logic := 'X'; -- Serial Enable LDNeg : IN std_logic := 'X'; -- Load FS : IN std_logic := 'X'; -- Frequency Select FFIRNeg : OUT std_logic := 'U'; -- Full Flag/Input Ready EFORNeg : OUT std_logic := 'U'; -- Empty Flag/Output Ready PAFNeg : OUT std_logic := 'U'; -- Programmable Almost Full Flag PAENeg : OUT std_logic := 'U'; -- Programmable Almost Empty Flag HFNeg : OUT std_logic := 'U'; -- Programmable Almost Empty Flag Q0 : OUT std_logic := 'U'; --------------------------------- Q1 : OUT std_logic := 'U'; -- Q2 : OUT std_logic := 'U'; -- Q3 : OUT std_logic := 'U'; -- Q4 : OUT std_logic := 'U'; -- Data Output Bus Q5 : OUT std_logic := 'U'; -- Q6 : OUT std_logic := 'U'; -- Q7 : OUT std_logic := 'U'; -- Q8 : OUT std_logic := 'U' --------------------------------- ); ATTRIBUTE vital_level0 OF IDT72271 : ENTITY IS True; END IDT72271; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -- -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF IDT72271 IS ATTRIBUTE vital_level0 OF vhdl_behavioral : ARCHITECTURE IS True; CONSTANT partID : String := "IDT72271"; CONSTANT FIFOWordLength : integer := 9; -- delayed inputs (func. sec. must use these signals instead of actual inputs) SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL D4_ipd : std_ulogic := 'X'; SIGNAL D5_ipd : std_ulogic := 'X'; SIGNAL D6_ipd : std_ulogic := 'X'; SIGNAL D7_ipd : std_ulogic := 'X'; SIGNAL D8_ipd : std_ulogic := 'X'; SIGNAL MRSNeg_ipd : std_ulogic := 'X'; SIGNAL PRSNeg_ipd : std_ulogic := 'X'; SIGNAL RTNeg_ipd : std_ulogic := 'X'; SIGNAL FWFTSI_ipd : std_ulogic := 'X'; SIGNAL WCLK_ipd : std_ulogic := 'X'; SIGNAL WENNeg_ipd : std_ulogic := 'X'; SIGNAL RCLK_ipd : std_ulogic := 'X'; SIGNAL RENNeg_ipd : std_ulogic := 'X'; SIGNAL OENeg_ipd : std_ulogic := 'X'; SIGNAL SENNeg_ipd : std_ulogic := 'X'; SIGNAL LDNeg_ipd : std_ulogic := 'X'; SIGNAL FS_ipd : std_ulogic := 'X'; SIGNAL D : std_ulogic_vector(FIFOWordLength-1 DOWNTO 0); SIGNAL Q : std_ulogic_vector(FIFOWordLength-1 DOWNTO 0); SIGNAL OpenIn, OpenOut : std_logic; -- Additional signals -- FIFO memory definitions (constants) -- internal signals ALIAS tpd_MRSNeg_HFNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_MRSNeg_FFIRNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_MRSNeg_PAFNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_MRSNeg_PAENeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_PRSNeg_HFNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_PRSNeg_FFIRNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_PRSNeg_PAFNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_PRSNeg_PAENeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_PRSNeg_EFORNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_WCLK_HFNeg : VitalDelayType01 IS tpd_RCLK_HFNeg; ALIAS tpd_PRSNeg_Q0 : VitalDelayType01Z IS tpd_MRSNeg_Q0; BEGIN -- architecture body -------------------------------------------------------------------------------- -- Skew Delays -------------------------------------------------------------------------------- -- Artificient VITAL primitives wich allows pass complex non-constaint -- SKEW time into the model SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1)); SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2)); ---------------------------------------------------------------------------- -- Wire Delays -- ---------------------------------------------------------------------------- D <= D0_ipd & D1_ipd & D2_ipd & D3_ipd & D4_ipd & D5_ipd & D6_ipd & D7_ipd & D8_ipd; WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D0_ipd , D0 , tipd_D0 ); w_2: VitalWireDelay (D1_ipd , D1 , tipd_D1 ); w_3: VitalWireDelay (D2_ipd , D2 , tipd_D2 ); w_4: VitalWireDelay (D3_ipd , D3 , tipd_D3 ); w_5: VitalWireDelay (D4_ipd , D4 , tipd_D4 ); w_6: VitalWireDelay (D5_ipd , D5 , tipd_D5 ); w_7: VitalWireDelay (D6_ipd , D6 , tipd_D6 ); w_8: VitalWireDelay (D7_ipd , D7 , tipd_D7 ); w_9: VitalWireDelay (D8_ipd , D8 , tipd_D8 ); w_10: VitalWireDelay (MRSNeg_ipd, MRSNeg, tipd_MRSNeg); w_11: VitalWireDelay (PRSNeg_ipd, PRSNeg, tipd_PRSNeg); w_12: VitalWireDelay (RTNeg_ipd , RTNeg , tipd_RTNeg ); w_13: VitalWireDelay (FWFTSI_ipd, FWFTSI, tipd_FWFTSI); w_14: VitalWireDelay (WCLK_ipd , WCLK , tipd_WCLK ); w_15: VitalWireDelay (WENNeg_ipd, WENNeg, tipd_WENNeg); w_16: VitalWireDelay (RCLK_ipd , RCLK , tipd_RCLK ); w_17: VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg); w_18: VitalWireDelay (OENeg_ipd , OENeg , tipd_OENeg ); w_19: VitalWireDelay (SENNeg_ipd, SENNeg, tipd_SENNeg); w_20: VitalWireDelay (LDNeg_ipd , LDNeg , tipd_LDNeg ); w_21: VitalWireDelay (FS_ipd , FS , tipd_FS ); END BLOCK WireDelay; ---------------------------------------------------------------------------- -- Main Behavior Block -- ---------------------------------------------------------------------------- VitalBehavior: BLOCK PORT ( D : IN std_logic_vector(FIFOWordLength-1 DOWNTO 0) := (OTHERS => 'X'); MRSNeg : IN std_ulogic := 'X'; PRSNeg : IN std_ulogic := 'X'; RTNeg : IN std_ulogic := 'X'; FWFTSI : IN std_ulogic := 'X'; WCLK : IN std_ulogic := 'X'; WENNeg : IN std_ulogic := 'X'; RCLK : IN std_ulogic := 'X'; RENNeg : IN std_ulogic := 'X'; OENeg : IN std_ulogic := 'X'; SENNeg : IN std_ulogic := 'X'; LDNeg : IN std_ulogic := 'X'; FS : IN std_ulogic := 'X'; FFIRNeg : OUT std_ulogic := 'U'; EFORNeg : OUT std_ulogic := 'U'; PAFNeg : OUT std_ulogic := 'U'; PAENeg : OUT std_ulogic := 'U'; HFNeg : OUT std_ulogic := 'U'; Q : OUT std_ulogic_vector(FIFOWordLength -1 DOWNTO 0) := (others => 'Z')); PORT MAP ( D(0) => D0_ipd, D(1) => D1_ipd, D(2) => D2_ipd, D(3) => D3_ipd, D(4) => D4_ipd, D(5) => D5_ipd, D(6) => D6_ipd, D(7) => D7_ipd, D(8) => D8_ipd, MRSNeg => MRSNeg_ipd, PRSNeg => PRSNeg_ipd, RTNeg => RTNeg_ipd, FWFTSI => FWFTSI_ipd, WCLK => WCLK_ipd, WENNeg => WENNeg_ipd, RCLK => RCLK_ipd, RENNeg => RENNeg_ipd, OENeg => OENeg_ipd, SENNeg => SENNeg_ipd, LDNeg => LDNeg_ipd, FS => FS_ipd, FFIRNeg => FFIRNeg, EFORNeg => EFORNeg, PAFNeg => PAFNeg, PAENeg => PAENeg, HFNeg => HFNeg, Q(0) => Q0, Q(1) => Q1, Q(2) => Q2, Q(3) => Q3, Q(4) => Q4, Q(5) => Q5, Q(6) => Q6, Q(7) => Q7, Q(8) => Q8); ----------------------------- SIGNAL FFIRNeg_zd : std_ulogic := 'X'; SIGNAL EFORNeg_zd : std_ulogic := 'X'; -- SIGNAL PAENeg_zd : std_ulogic := 'X'; -- regs for output flags SIGNAL PAFNeg_zd : std_ulogic := 'X'; -- SIGNAL HFNeg_zd : std_ulogic := 'X'; SIGNAL Q_zd : std_logic_vector(FIFOWordLength-1 DOWNTO 0); ----------------------------- BEGIN -- VitalBehavior block ------------------------------------------------------------------------ -- Timing Check Section -- ------------------------------------------------------------------------ TimingChecks: PROCESS (D, MRSNeg, PRSNeg, RTNeg, FWFTSI, WCLK, WENNeg, RCLK, RENNeg, OENeg, SENNeg, LDNeg) -- Timing Check Variables -- Pulse Width & Period Check Variables VARIABLE Pviol_WCLK : X01 := '0'; VARIABLE PD_WCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RCLK : X01 := '0'; VARIABLE PD_RCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MRSNeg : X01 := '0'; VARIABLE PD_MRSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRSNeg : X01 := '0'; VARIABLE PD_PRSNeg : VitalPeriodDataType := VitalPeriodDataInit; -- Setup/Hold Check Variables VARIABLE Tviol_D0_WCLK : X01 := '0'; VARIABLE TD_D0_WCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_WCLK : X01 := '0'; VARIABLE TD_WENNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_SENNeg_WCLK : X01 := '0'; VARIABLE TD_SENNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_RENNeg_RCLK : X01 := '0'; VARIABLE TD_RENNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_RTNeg_RCLK : X01 := '0'; VARIABLE TD_RTNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_LDNeg_WCLK : X01 := '0'; VARIABLE TD_LDNeg_WCLK : VitalTimingDataType; VARIABLE Tviol_LDNeg_RCLK : X01 := '0'; VARIABLE TD_LDNeg_RCLK : VitalTimingDataType; VARIABLE Tviol_WENNeg_MRSNeg : X01 := '0'; VARIABLE TD_WENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_MRSNeg : X01 := '0'; VARIABLE TD_RENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_LDNeg_MRSNeg : X01 := '0'; VARIABLE TD_LDNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_RTNeg_MRSNeg : X01 := '0'; VARIABLE TD_RTNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_SENNeg_MRSNeg : X01 := '0'; VARIABLE TD_SENNeg_MRSNeg : VitalTimingDataType; VARIABLE Tviol_WENNeg_PRSNeg : X01 := '0'; VARIABLE TD_WENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_RENNeg_PRSNeg : X01 := '0'; VARIABLE TD_RENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_RTNeg_PRSNeg : X01 := '0'; VARIABLE TD_RTNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_SENNeg_PRSNeg : X01 := '0'; VARIABLE TD_SENNeg_PRSNeg : VitalTimingDataType; VARIABLE Tviol_FWFTSI_WCLK : X01 := '0'; VARIABLE TD_FWFTSI_WCLK : VitalTimingDataType; VARIABLE Tviol_FWFTSI_MRSNeg : X01 := '0'; VARIABLE TD_FWFTSI_MRSNeg : VitalTimingDataType; VARIABLE Tviol_WENNeg_RCLK : X01 := '0'; VARIABLE TD_WENNeg_RCLK : VitalTimingDataType; -- Violation variable (used to OR all individual violations) VARIABLE Violation : X01 := '0'; BEGIN -- timing checks process IF (TimingChecksOn) THEN Pviol_WCLK := '0'; Pviol_RCLK := '0'; Pviol_MRSNeg := '0'; Pviol_PRSNeg := '0'; Tviol_D0_WCLK := '0'; Tviol_WENNeg_WCLK := '0'; Tviol_SENNeg_WCLK := '0'; Tviol_RENNeg_RCLK := '0'; Tviol_RTNeg_RCLK := '0'; Tviol_LDNeg_WCLK := '0'; Tviol_LDNeg_RCLK := '0'; Tviol_WENNeg_MRSNeg := '0'; Tviol_RENNeg_MRSNeg := '0'; Tviol_LDNeg_MRSNeg := '0'; Tviol_RTNeg_MRSNeg := '0'; Tviol_SENNeg_MRSNeg := '0'; Tviol_WENNeg_PRSNeg := '0'; Tviol_RENNeg_PRSNeg := '0'; Tviol_RTNeg_PRSNeg := '0'; Tviol_SENNeg_PRSNeg := '0'; Tviol_FWFTSI_WCLK := '0'; Tviol_FWFTSI_MRSNeg := '0'; Tviol_RENNeg_RCLK := '0'; --1 WCLK pulse (low & high) width and period check -- (tWCLK, tWCLKH, tWCLKL) IF WCLK'event THEN VitalPeriodPulseCheck ( TestSignal => WCLK, TestSignalName => "WCLK", Period => tperiod_WCLK_posedge, PulseWidthHigh => tpw_WCLK_posedge, PulseWidthLow => tpw_WCLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WCLK); END IF; --2 RCLK pulse (low & high) width and period check -- (tperiod_RCLK_posedge, tperiod_RCLK_posedgeH, -- tperiod_RCLK_posedgeL) IF RCLK'event THEN VitalPeriodPulseCheck ( TestSignal => RCLK, TestSignalName => "RCLK", Period => tperiod_RCLK_posedge, PulseWidthHigh => tpw_RCLK_posedge, PulseWidthLow => tpw_RCLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RCLK); END IF; --3 MRSNeg low pulse width check (tRS) IF MRSNeg'event THEN VitalPeriodPulseCheck ( TestSignal => MRSNeg, TestSignalName => "MRSNeg", PulseWidthLow => tpw_MRSNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MRSNeg); END IF; --4 PRSNeg low pulse width check (tRS) IF PRSNeg'event THEN VitalPeriodPulseCheck ( TestSignal => PRSNeg, TestSignalName => "PRSNeg", PulseWidthLow => tpw_PRSNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_PRSNeg); END IF; IF MRSNeg /= '0' AND PRSNeg /= '0' THEN --(exclude 5-8 if reset) --5 D/WCLK setup/hold time check (tDS, tDH) IF D'event OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => D, TestSignalName => "D", RefSignal => WCLK, RefSignalName => "WCLK", SetupHigh => tsetup_D0_WCLK_noedge_posedge, SetupLow => tsetup_D0_WCLK_noedge_posedge, HoldHigh => thold_D0_WCLK_noedge_posedge, HoldLow => thold_D0_WCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_D0_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_WCLK); END IF; --6 WENNeg/WCLK setup/hold time check (tENS, tENH) IF WENNeg'event OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_RENNeg_RCLK_noedge_posedge, HoldHigh => thold_RENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_WCLK); END IF; --7 SENNeg/WCLK setup/hold time check (tENS, tENH) IF SENNeg'event OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => SENNeg, TestSignalName => "SENNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_SENNeg_WCLK_noedge_posedge, HoldHigh => thold_SENNeg_WCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_WCLK); END IF; --8 RENNeg/RCLK setup/hold time check (tENS, tENH) IF RENNeg'event OR (RCLK'event AND RCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RENNeg_RCLK_noedge_posedge, HoldHigh => thold_RENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RCLK); END IF; --9 RTNeg/RCLK setup/hold time check (tENS, tENH) IF RTNeg'event OR (RCLK'event AND RCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => RTNeg, TestSignalName => "RTNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RTNeg_RCLK_noedge_posedge, HoldHigh => thold_RTNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_RCLK); END IF; --10 WENNeg/RTNeg/RCLK setup time check (tRTS) IF WENNeg'event OR ((RCLK'event AND RCLK = '1') AND RTNeg = '0') THEN VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupHigh => tsetup_WENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_RCLK); END IF; --12 LDNeg/WCLK setup/hold time check (tLDS/tLDH) IF LDNeg'event OR ((WCLK'event AND WCLK = '1') AND (WENNeg ='0' OR SENNeg ='0')) THEN VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_LDNeg_WCLK_noedge_posedge, HoldHigh => thold_LDNeg_WCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_WCLK); END IF; --13 LDNeg/RCLK setup/hold time check (tLDS/tLDH) IF LDNeg'event OR ((RCLK'event AND RCLK = '1') AND (RENNeg = '0')) THEN VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_LDNeg_RCLK_noedge_posedge, HoldHigh => thold_LDNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_RCLK); END IF; END IF; --14 RENNeg/MRSNeg setup/recovery time check (tRSS/tRSR) IF RENNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg_noedge_posedge, HoldLow => thold_RENNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_MRSNeg); END IF; --15 WENNeg/MRSNeg setup/recovery time check (tRSS/tRSR) IF WENNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_WENNeg_MRSNeg_noedge_posedge, HoldLow => thold_WENNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_MRSNeg); END IF; --16 LDNeg/MRSNeg setup/recovery time check (tRSS/tRSR) IF LDNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, SetupLow => tsetup_LDNeg_MRSNeg_noedge_posedge, HoldHigh => thold_LDNeg_MRSNeg_noedge_posedge, HoldLow => thold_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_MRSNeg); END IF; --17 RTNeg/MRSNeg setup time check (tRSS) IF RTNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RTNeg, TestSignalName => "RTNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_RTNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_MRSNeg); END IF; --18 SENNeg/MRSNeg setup time check (tRSS) IF SENNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => SENNeg, TestSignalName => "SENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_SENNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_MRSNeg); END IF; --19 RENNeg/PRSNeg setup/recovery time check (tRSS/tRSR) IF RENNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_PRSNeg_noedge_posedge, HoldLow => thold_RENNeg_PRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_PRSNeg); END IF; --20 WENNeg/PRSNeg setup/recovery time check (tRSS/tRSR) IF WENNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_WENNeg_PRSNeg_noedge_posedge, HoldLow => thold_WENNeg_PRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_PRSNeg); END IF; --21 RTNeg/PRSNeg setup time check (tRSS) IF RTNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RTNeg, TestSignalName => "RTNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_RTNeg_PRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_PRSNeg); END IF; --22 SENNeg/PRSNeg setup time check (tRSS) IF SENNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => SENNeg, TestSignalName => "SENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_SENNeg_PRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_PRSNeg); END IF; --23 FWFTSI/WCLK setup time check (tDS) IF (FWFTSI'event AND SENNeg = '0' AND LDNeg = '0') OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => FWFTSI, TestSignalName => "FWFTSI", RefSignal => WCLK, RefSignalName => "WCLK", SetupHigh => tsetup_FWFTSI_WCLK_noedge_posedge, SetupLow => tsetup_FWFTSI_WCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FWFTSI_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFTSI_WCLK); END IF; --24 FWFTSI_MRSNeg setup time check (tFWFT) IF FWFTSI'event OR (MRSNeg'event AND MRSNeg = '0') THEN VitalSetupHoldCheck ( TestSignal => FWFTSI, TestSignalName => "FWFTSI", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_FWFTSI_MRSNeg_noedge_negedge, SetupLow => tsetup_FWFTSI_MRSNeg_noedge_negedge, CheckEnabled => True, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_FWFTSI_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFTSI_MRSNeg); END IF; --25 FWFTSI_MRSNeg setup time check (tRSR) IF FWFTSI'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => FWFTSI, TestSignalName => "FWFTSI", RefSignal => MRSNeg, RefSignalName => "MRSNeg", HoldHigh => thold_FWFTSI_MRSNeg_noedge_posedge, HoldLow => thold_FWFTSI_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_FWFTSI_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFTSI_MRSNeg); END IF; Violation := Pviol_WCLK OR Pviol_RCLK OR Pviol_MRSNeg OR Pviol_PRSNeg OR Tviol_D0_WCLK OR Tviol_WENNeg_WCLK OR Tviol_SENNeg_WCLK OR Tviol_RENNeg_RCLK OR Tviol_RTNeg_RCLK OR Tviol_LDNeg_WCLK OR Tviol_LDNeg_RCLK OR Tviol_WENNeg_MRSNeg OR Tviol_RENNeg_MRSNeg OR Tviol_LDNeg_MRSNeg OR Tviol_RTNeg_MRSNeg OR Tviol_SENNeg_MRSNeg OR Tviol_WENNeg_PRSNeg OR Tviol_RENNeg_PRSNeg OR Tviol_RTNeg_PRSNeg OR Tviol_SENNeg_PRSNeg OR Tviol_FWFTSI_WCLK OR Tviol_FWFTSI_MRSNeg OR Tviol_WENNeg_RCLK; ASSERT Violation = '0' REPORT InstancePath & partID & " : signal values may be" & " incorret due timing violation(s)" SEVERITY Warning; END IF; END PROCESS TimingChecks; ------------------------------------------------------------------------ -- Functionality section -- ------------------------------------------------------------------------ IDT: BLOCK port(D0 : IN std_ulogic := 'X'; D1 : IN std_ulogic := 'X'; D2 : IN std_ulogic := 'X'; D3 : IN std_ulogic := 'X'; D4 : IN std_ulogic := 'X'; D5 : IN std_ulogic := 'X'; D6 : IN std_ulogic := 'X'; D7 : IN std_ulogic := 'X'; D8 : IN std_ulogic := 'X'; MRSNeg : IN std_ulogic := 'X'; PRSNeg : IN std_ulogic := 'X'; RTNeg : IN std_ulogic := 'X'; FWFTSI : IN std_ulogic := 'X'; WCLK : IN std_ulogic := 'X'; WENNeg : IN std_ulogic := 'X'; RENNeg : IN std_ulogic := 'X'; RCLK : IN std_ulogic := 'X'; OENeg : IN std_ulogic := 'X'; SENNeg : IN std_ulogic := 'X'; LDNeg : IN std_ulogic := 'X'; FS : IN std_ulogic := 'X'; FFIRNeg : OUT std_ulogic := 'U'; EFORNeg : OUT std_ulogic := 'U'; PAFNeg : OUT std_ulogic := 'U'; PAENeg : OUT std_ulogic := 'U'; HFNeg : OUT std_ulogic := 'U'; Q0 : OUT std_ulogic := 'U'; Q1 : OUT std_ulogic := 'U'; Q2 : OUT std_ulogic := 'U'; Q3 : OUT std_ulogic := 'U'; Q4 : OUT std_ulogic := 'U'; Q5 : OUT std_ulogic := 'U'; Q6 : OUT std_ulogic := 'U'; Q7 : OUT std_ulogic := 'U'; Q8 : OUT std_ulogic := 'U' ); port map ( MRSNeg => MRSNeg, D0 => D(0), D1 => D(1), D2 => D(2), D3 => D(3), D4 => D(4), D5 => D(5), D6 => D(6), D7 => D(7), D8 => D(8), Q0 => Q_zd(0), Q1 => Q_zd(1), Q2 => Q_zd(2), Q3 => Q_zd(3), Q4 => Q_zd(4), Q5 => Q_zd(5), Q6 => Q_zd(6), Q7 => Q_zd(7), Q8 => Q_zd(8), RCLK => RCLK, PRSNeg => PRSNeg, RTNeg => RTNeg, FWFTSI => FWFTSI, WCLK => WCLK, RENNeg => RENNeg, WENNeg => WENNeg, OENeg => OENeg, SENNeg => SENNeg, LDNeg => LDNeg, FS => FS, FFIRNeg => FFIRNeg_zd, EFORNeg => EFORNeg_zd, HFNeg => HFNeg_zd, PAENeg => PAENeg_zd, PAFNeg => PAFNeg_zd); CONSTANT cond1 : integer:= 127; CONSTANT cond2 : integer:= 1023; CONSTANT LSBS : integer:= 7; CONSTANT MSBS : integer:= 6; CONSTANT FIFOsize : integer := 32768; SIGNAL FullFlagInt : std_logic; SIGNAL InputReadyInt : std_logic; SIGNAL EmptyFlagInt : std_logic; SIGNAL OutputReadyInt : std_logic; SIGNAL DataInInt : std_logic_vector(8 DOWNTO 0); SIGNAL DataOutInt : std_logic_vector(8 DOWNTO 0); SIGNAL WRPointerInt : integer RANGE FIFOSize DOWNTO 0; SIGNAL RDPointerInt : integer RANGE FIFOSize DOWNTO 0; SIGNAL WRIntoEmptyInt : std_logic; SIGNAL DiffInt : integer RANGE FIFOSize DOWNTO 0; SIGNAL PrevDiffInt: integer RANGE FIFOSize DOWNTO 0; SIGNAL AlmostEmptyCondInt: integer RANGE FIFOSize DOWNTO 0; SIGNAL AlmostFullCondInt : integer RANGE FIFOSize DOWNTO 0; SIGNAL HalfFullCondInt : integer RANGE FIFOSize DOWNTO 0; SIGNAL InternalClockInt : std_logic; SIGNAL ReadFromFullInt : std_logic; SIGNAL OutputRegisterInt : std_logic_vector(8 DOWNTO 0); SIGNAL AEFInt : std_logic; SIGNAL PAE1Int : std_logic; SIGNAL PAE2Int : std_logic; SIGNAL FullFlag1Int : std_logic; SIGNAL HalfFull1Int : std_logic; SIGNAL AFFInt : std_logic; SIGNAL RTAFFInt : std_logic; SIGNAL PAF1Int : std_logic; SIGNAL PAF2Int : std_logic; SIGNAL LSBPAEInt : std_logic_vector(LSBS DOWNTO 0); SIGNAL MSBPAEInt : std_logic_vector(MSBS DOWNTO 0); SIGNAL LSBPAFInt : std_logic_vector(LSBS DOWNTO 0); SIGNAL MSBPAFInt : std_logic_vector(MSBS DOWNTO 0); SIGNAL LSBPAE1Int : std_logic_vector(LSBS DOWNTO 0); SIGNAL MSBPAE1Int : std_logic_vector(MSBS DOWNTO 0); SIGNAL LSBPAF1Int : std_logic_vector(LSBS DOWNTO 0); SIGNAL MSBPAF1Int : std_logic_vector(MSBS DOWNTO 0); SIGNAL FrontNumInt : std_logic_vector(4 DOWNTO 0); SIGNAL ProgFinishedInt : std_logic; SIGNAL ParProgInt : std_logic; SIGNAL SerialRegInt : std_logic_vector (MSBS + LSBS + MSBS+LSBS + 3 DOWNTO 0); SIGNAL ReadFnInt : std_logic_vector(1 DOWNTO 0); SIGNAL OutputValidInt : std_logic; SIGNAL ModeInt : std_logic; SIGNAL RTBeginInt : std_logic; SIGNAL RTEndInt : std_logic; SIGNAL RTExtraInt : std_logic; SIGNAL AfterRTInt : std_logic; SIGNAL AEDisableAfterRTInt: std_logic; SIGNAL AfterRTSkew2Int : std_logic; SIGNAL EmptyRecovExtraInt: std_logic; SIGNAL EmptyRecovInt : std_logic; SIGNAL WrEnInt : std_logic; SIGNAL RdEnInt : std_logic; SIGNAL FFIRint : std_logic; SIGNAL EFORint : std_logic; SIGNAL FirstWordWritedInt: std_logic; SIGNAL ReadFirstAfterRTInt: std_logic; SIGNAL InpRegInt : std_logic_vector(8 DOWNTO 0); SIGNAL IDTFirstWordInt : std_logic; SIGNAL FWFTFirstWordInt : std_logic; SIGNAL SerialInputInt : std_logic; SIGNAL PAFInt : std_logic; SIGNAL PAEInt : std_logic; SIGNAL HFInt : std_logic; SIGNAL VirtualWRAEF : std_logic; SIGNAL VirtualWRAFF : std_logic; SIGNAL PAEEnable : std_logic; SIGNAL PAFEnable : std_logic; SIGNAL PafenDop : std_logic; SIGNAL PaeenDop : std_logic; SIGNAL PaeenDop1 : std_logic; BEGIN SerialInputInt <= FWFTSI; InputReadyInt <= not FullFlagInt; PAFNeg <= PAFInt when PAFEnable = '1' else 'U' when PAFEnable = 'U' else 'X'; PAENeg <= PAEInt when PAEEnable = '1' else 'U' when PAEEnable = 'U' else 'X'; HFNeg <= HFInt; FFIRNeg <= FFIRint; EFORNeg <= EFORint; FFIRint <= FullFlagInt WHEN ModeInt = '0' ELSE InputReadyInt; EFORint <= EmptyFlagInt WHEN ModeInt = '0' ELSE OutputReadyInt; WrEnInt <= '1' WHEN RTBeginInt = '0' AND ((FullFlagInt = '1' AND ModeInt = '0') OR (InputReadyInt = '0' AND ModeInt = '1')) ELSE '0'; RdEnInt <= '1' WHEN (EmptyFlagInt = '1' AND ModeInt = '0') or (OutputReadyInt = '0' AND ModeInt = '1' AND DiffInt > 0) ELSE '0'; InternalClockInt <= RCLK WHEN FS = '0' ELSE WCLK; DataInInt <= D8 & D7 & D6 & D5 & D4 & D3 & D2 & D1& D0; Q0 <= DataOutInt(0); Q1 <= DataOutInt(1); Q2 <= DataOutInt(2); Q3 <= DataOutInt(3); Q4 <= DataOutInt(4); Q5 <= DataOutInt(5); Q6 <= DataOutInt(6); Q7 <= DataOutInt(7); Q8 <= DataOutInt(8); LSBPAE1Int <= SerialRegInt(LSBS DOWNTO 0); MSBPAE1Int <= SerialRegInt(MSBS+LSBS+1 DOWNTO LSBS+1); LSBPAF1Int <= SerialRegInt(LSBS + MSBS + LSBS + 2 DOWNTO MSBS+LSBS+2); MSBPAF1Int <= SerialRegInt(MSBS + LSBS + MSBS + LSBS + 3 DOWNTO LSBS + MSBS+LSBS + 3); Outp_ready:PROCESS(EmptyFlagInt, RCLK) BEGIN IF EmptyFlagInt = '1' and RTNeg = '1' THEN OutputReadyInt <= '0'; ELSIF RCLK'event AND RCLK = '1' THEN IF RTNeg = '0' OR (EmptyFlagInt = '0' AND DiffInt = 0) THEN OutputReadyInt <= '1' ; END IF; END IF; END PROCESS; AEFEN:PROCESS(RCLK) BEGIN IF RCLK'event AND RCLK = '1' THEN IF VirtualWRAEF = '1' THEN PaeenDop1 <= '1'; END IF; IF PaeenDop1 = '1' THEN PaeenDop1 <= '0'; PaeenDop <= '1'; END IF; IF PaeenDop = '1' AND VirtualWRAEF = '0' THEN PaeenDop <= '0'; END IF; END IF; END PROCESS; Offset_loading: PROCESS(WCLK, MRSNeg, PaeenDop) BEGIN IF MRSNeg = '0' THEN PAEEnable <= '1'; PAFEnable <= '1'; FrontNumInt <= "00000"; ProgFinishedInt <= '0'; HalfFullCondInt <= (FIFOSize) / 2; IF LDNeg ='1' THEN AlmostEmptyCondInt <= cond2; AlmostFullCondInt <= FIFOSize - cond2; ParProgInt <= '0'; LSBPAEInt(LSBS DOWNTO 0) <= std_logic_vector(to_slv(cond2, LSBS+1)); LSBPAFInt(LSBS DOWNTO 0) <= std_logic_vector(to_slv(cond2, LSBS+1)); MSBPAEInt(MSBS DOWNTO 0) <= std_logic_vector(to_slv(1, MSBS+1)); MSBPAFInt(MSBS DOWNTO 0) <= std_logic_vector(to_slv(1, MSBS+1)); SerialRegInt(LSBS DOWNTO 0) <= std_logic_vector(to_slv(cond1, LSBS+1)); SerialRegInt(LSBS+MSBS+LSBS+2 DOWNTO MSBS+LSBS+2) <= std_logic_vector(to_slv(cond1, LSBS+1)); SerialRegInt(MSBS+LSBS+1 DOWNTO LSBS+1) <= std_logic_vector(to_slv(1, MSBS+1)); SerialRegInt(MSBS+LSBS+MSBS+LSBS+3 DOWNTO LSBS+MSBS+LSBS+3) <= std_logic_vector(to_slv(1, MSBS+1)); ELSE AlmostEmptyCondInt <= cond1; AlmostFullCondInt <= FIFOSize - cond1; ParProgInt <= '1'; LSBPAEInt(LSBS DOWNTO 0) <= std_logic_vector(to_slv(cond1, LSBS+1)); LSBPAFInt(LSBS DOWNTO 0) <= std_logic_vector(to_slv(cond1, LSBS+1)); MSBPAEInt(MSBS DOWNTO 0) <= std_logic_vector(to_slv(0, MSBS+1)); MSBPAFInt(MSBS DOWNTO 0) <= std_logic_vector(to_slv(0, MSBS+1)); END IF; ELSE IF PaeenDop = '1' THEN PAEEnable <= '1'; VirtualWRAEF <= '0'; END IF; IF WCLK'event AND WCLK = '1' THEN IF VirtualWRAFF = '1' THEN PafenDop <= '1'; VirtualWRAFF <= '0'; END IF; IF PafenDop = '1' THEN PAFEnable <= '1'; PafenDop <= '0'; END IF; IF ParProgInt = '1' THEN IF LDNeg ='0' AND WENNeg = '0' THEN CASE FrontNumInt is WHEN "00000" => PAEEnable <= '0'; FrontNumInt <= "00001"; LSBPAEInt(LSBS DOWNTO 0) <= DataInInt(LSBS DOWNTO 0); AlmostEmptyCondInt <= to_nat(( MSBPAEInt(MSBS DOWNTO 0) & DataInInt(LSBS DOWNTO 0))); WHEN "00001" => FrontNumInt <= "00010"; MSBPAEInt(MSBS DOWNTO 0) <= DataInInt(MSBS DOWNTO 0); AlmostEmptyCondInt <= to_nat(( DataInInt(MSBS DOWNTO 0) & LSBPAEInt(LSBS DOWNTO 0))); VirtualWRAEF <= '1' AFTER tdevice_SKEW2; WHEN "00010" => PAFEnable <= '0'; FrontNumInt <= "00011"; LSBPAFInt(LSBS DOWNTO 0) <= DataInInt(LSBS DOWNTO 0); AlmostFullCondInt <= FIFOSize - to_nat(( MSBPAFInt(MSBS DOWNTO 0) & DataInInt(LSBS DOWNTO 0))); WHEN "00011" => FrontNumInt <= "00000"; MSBPAFInt(MSBS DOWNTO 0) <= DataInInt(MSBS DOWNTO 0); ProgFinishedInt <= '1'; AlmostFullCondInt <= FIFOSize - to_nat(( DataInInt(MSBS DOWNTO 0) & LSBPAFInt(LSBS DOWNTO 0))); VirtualWRAFF <= '1'; WHEN others => NULL; END CASE; END IF; ELSE LSBPAEInt <= LSBPAE1Int; MSBPAEInt <= MSBPAE1Int; LSBPAFInt <= LSBPAF1Int; MSBPAFInt <= MSBPAF1Int; IF LDNeg ='0' AND SENNeg = '0' AND ProgFinishedInt = '0' THEN PAEEnable <= '0'; PAFEnable <= '0'; FrontNumInt <= std_logic_vector(to_slv( to_nat((FrontNumInt)) + 1, 5)); IF to_nat((FrontNumInt)) < SerialRegInt'high THEN SerialRegInt(to_nat((FrontNumInt))) <= SerialInputInt; ELSE SerialRegInt(to_nat((FrontNumInt))) <= SerialInputInt; AlmostEmptyCondInt <= to_nat(( MSBPAEInt(MSBS DOWNTO 0) & LSBPAEInt(LSBS DOWNTO 0))); AlmostFullCondInt <= FIFOSize - to_nat(( SerialInputInt & MSBPAF1Int(MSBS - 1 DOWNTO 0) & LSBPAFInt(LSBS DOWNTO 0))); ProgFinishedInt <= '1'; FrontNumInt <= "00000"; VirtualWRAEF <= '1' AFTER tdevice_SKEW2; VirtualWRAFF <= '1'; END IF; END IF; END IF; END IF; END IF; END PROCESS; Output_latch:PROCESS(MRSNeg, OENeg, OutputRegisterInt, OutputValidInt) BEGIN IF OENeg = '0' THEN OutputValidInt <= '1'; ELSE OutputValidInt <= '0'; END IF; IF MRSNeg = '0' THEN IF OENeg = '1' THEN DataOutInt <= "ZZZZZZZZZ"; ELSE DataOutInt<= "000000000"; END IF; ELSE IF OutputValidInt = '1' THEN DataOutInt <= OutputRegisterInt; ELSE DataOutInt <= "ZZZZZZZZZ"; END IF; END IF; END PROCESS; First_word: PROCESS(WCLK, MRSNeg, ReadFirstAfterRTInt) BEGIN IF MRSNeg = '0' OR ReadFirstAfterRTInt = '1' THEN FWFTFirstWordInt <= '0'; ELSIF RTEndInt = '1' and ModeInt = '1' THEN FWFTFirstWordInt <= '1'; ELSIF WCLK'event AND WCLK = '1' THEN IF ModeInt = '1' AND OutputReadyInt = '1' and FWFTFirstWordInt = '0' AND WENNeg = '0' THEN FWFTFirstWordInt <= '1'; InpRegInt <= DataInInt; END IF; END IF; END PROCESS; First_word_WR: PROCESS(MRSNeg, FWFTFirstWordInt, RCLK) BEGIN IF MRSNeg = '0' THEN FirstWordWritedInt <= '0'; ELSIF FWFTFirstWordInt = '1' THEN FirstWordWritedInt <= '1'; ELSIF RCLK'event AND RCLK = '1' THEN IF RTNeg = '0' OR (EmptyFlagInt = '0' AND DiffInt = 0) THEN FirstWordWritedInt <= '0'; END IF; END IF; END PROCESS; Read_Write: PROCESS(WCLK, HalfFull1Int, MRSNeg, PRSNeg, RCLK, FullFlagInt) variable FIFO0Int : std_logic_vector(FIFOSize DOWNTO 0); variable FIFO1Int : std_logic_vector(FIFOSize DOWNTO 0); variable FIFO2Int : std_logic_vector(FIFOSize DOWNTO 0); variable FIFO3Int : std_logic_vector(FIFOSize DOWNTO 0); variable FIFO4Int : std_logic_vector(FIFOSize DOWNTO 0); variable FIFO5Int : std_logic_vector(FIFOSize DOWNTO 0); variable FIFO6Int : std_logic_vector(FIFOSize DOWNTO 0); variable FIFO7Int : std_logic_vector(FIFOSize DOWNTO 0); variable FIFO8Int : std_logic_vector(FIFOSize DOWNTO 0); BEGIN -- SUBPROCESS Write IF MRSNeg = '0' THEN WRPointerInt <= 0; IF FWFTSI = '1' THEN ModeInt <= '1'; -- FWFT; FullFlagInt <= '1'; HFInt <= '1'; PAFInt <= '1'; PAF1Int <= '1'; WRIntoEmptyInt <= '0'; FullFlag1Int <= '0'; ELSE ModeInt <= '0'; -- IDT; FullFlagInt <= '1'; HFInt <= '1'; PAFInt <= '1'; PAF1Int <= '1'; WRIntoEmptyInt <= '0'; FullFlag1Int <= '1'; END IF; ELSIF PRSNeg = '0' THEN WRPointerInt <= 0; IF ModeInt ='1' THEN FullFlagInt <= '1'; FullFlag1Int <= '0'; HFInt <= '1'; PAFInt <= '1'; PAF1Int <= '1'; ELSE FullFlagInt <= '1'; FullFlag1Int <= '0'; HFInt <= '1'; PAFInt <= '1'; PAF1Int <= '1'; END IF; ELSE IF (AfterRTInt = '1' AND DiffInt >= HalfFullCondInt) AND ((ModeInt = '0' AND RENNeg = '0' AND RCLK = '1') OR (ModeInt = '1')) THEN HFInt <= '0'; ELSIF HalfFull1Int = '0' THEN HFInt <= '1'; END IF; IF WCLK'event AND WCLK = '1' THEN IF ReadFromFullInt = '0' THEN FullFlag1Int <= '1'; END IF; IF FullFlag1Int = '1' THEN FullFlagInt <= '1'; END IF; IF EmptyFlagInt ='1' THEN WRIntoEmptyInt <= '0'; END IF; IF PAEInt ='0' THEN AEFInt <= '0'; END IF; IF PAF2Int = '0' THEN PAF2Int <= '1'; END IF; IF AfterRTSkew2Int = '1' THEN IF PAF2Int = '0' OR RTAFFInt = '0' THEN PAF1Int <= '0'; END IF; IF AFFInt = '1' THEN PAF1Int <= '1'; END IF; END IF; IF PAF1Int = '0' THEN PAFInt <= '0'; ELSE PAFInt <= '1'; END IF; IF WENNeg = '0' AND WrEnInt ='1' AND LDNeg = '1' THEN IF (EmptyFlagInt = '0' AND ModeInt = '0') or (OutputReadyInt = '1' AND ModeInt = '1') THEN WRIntoEmptyInt <= '1'; END IF; IF FirstWordWritedInt = '1' OR ModeInt = '0' THEN IF DiffInt >= AlmostFullCondInt - 1 THEN PAF2Int <= '0'; END IF; IF WRPointerInt = FIFOSize - 1 THEN WRPointerInt <= 0; ELSE WRPointerInt <= WRPointerInt + 1; END IF; IF DiffInt >= AlmostEmptyCondInt THEN AEFInt <= '1' AFTER tdevice_SKEW2; END IF; IF DiffInt = FIFOSize - 1 THEN FullFlagInt <= '0'; FullFlag1Int <= '0'; END IF; IF DiffInt >= HalfFullCondInt THEN HFInt <= '0'; END IF; FIFO0Int(WRPointerInt) := DataInInt(0); FIFO1Int(WRPointerInt) := DataInInt(1); FIFO2Int(WRPointerInt) := DataInInt(2); FIFO3Int(WRPointerInt) := DataInInt(3); FIFO4Int(WRPointerInt) := DataInInt(4); FIFO5Int(WRPointerInt) := DataInInt(5); FIFO6Int(WRPointerInt) := DataInInt(6); FIFO7Int(WRPointerInt) := DataInInt(7); FIFO8Int(WRPointerInt) := DataInInt(8); END IF; END IF; END IF; END IF; -- END SUBPROCESS Write -- SUBPROCESS Read IF MRSNeg = '0' THEN RTBeginInt <= '0'; OutputRegisterInt <= "000000000"; RDPointerInt <= 0; ReadFirstAfterRTInt <= '0'; IF FWFTSI = '1' THEN EmptyFlagInt <= '0'; PAEInt <= '0'; PAE1Int <= '0'; ELSE EmptyFlagInt <= '0'; PAEInt <= '0'; PAE1Int <= '0'; END IF; ELSIF PRSNeg = '0' THEN OutputRegisterInt <= "000000000"; RDPointerInt <= 0; IF ModeInt = '1' THEN EmptyFlagInt <= '0'; PAEInt <= '0'; PAE1Int <= '0'; ELSE EmptyFlagInt <= '0'; PAEInt <= '0'; PAE1Int <= '0'; END IF; ELSE IF FullFlagInt = '1' THEN ReadFromFullInt <= '1'; END IF; IF RCLK'event AND RCLK = '1' THEN IF RTNeg = '0' THEN IF RENNeg = '1' AND WENNeg = '1' THEN EmptyFlagInt <= '0'; RTBeginInt <= '1'; RDPointerInt <= 0; END IF; ELSIF RTEndInt = '1' THEN RTBeginInt <= '0'; EmptyFlagInt <= '1'; ELSIF EmptyRecovExtraInt = '1' THEN EmptyFlagInt <= '1'; END IF; IF PAFInt ='1' THEN AFFInt <= '0'; END IF; IF PAFInt ='0' THEN RTAFFInt <= '1'; END IF; IF PAE2Int = '0' THEN PAE2Int <= '1'; END IF; IF PAE2Int = '0' THEN PAE1Int <= '0'; END IF; IF DiffInt > AlmostEmptyCondInt and PAEInt = '0' THEN IF AEFInt = '1' OR AEDisableAfterRTInt = '1' THEN PAE1Int <= '1'; END IF; END IF; IF PAE1Int = '0' THEN PAEInt <= '0'; ELSE PAEInt <= '1'; END IF; IF LDNeg = '1' THEN ReadFnInt <= "00"; IF ModeInt = '1' AND ((FWFTFirstWordInt = '1' AND EmptyRecovExtraInt = '1') OR (ModeInt = '1' AND RTBeginInt = '1' AND RTEndInt = '1')) THEN OutputRegisterInt <= InpRegInt; ReadFirstAfterRTInt <= '1'; IF DiffInt >= AlmostFullCondInt THEN RTAFFInt <= '0' AFTER tdevice_SKEW2; END IF; ELSIF RENNeg = '0' AND RdEnInt = '1' AND ProgFinishedInt = '1' THEN IF DiffInt = AlmostEmptyCondInt + 1 THEN PAE2Int <= '0'; END IF; ReadFirstAfterRTInt <= '0'; IF RDPointerInt = FIFOSize - 1 THEN RDPointerInt <= 0; ELSE RDPointerInt <= RDPointerInt+1; END IF; IF DiffInt <= 1 THEN EmptyFlagInt <= '0'; END IF; IF FullFlagInt = '0' THEN ReadFromFullInt <= '0' AFTER tdevice_SKEW1; END IF; IF HFInt = '0' AND DiffInt <= HalfFullCondInt + 1 THEN HalfFull1Int <= '0'; ELSE HalfFull1Int <= '1'; END IF; IF DiffInt <= AlmostFullCondInt THEN AFFInt <= '1' AFTER tdevice_SKEW2; END IF; IF DiffInt >= AlmostFullCondInt THEN RTAFFInt <= '0' AFTER tdevice_SKEW2; END IF; OutputRegisterInt(0) <= FIFO0Int(RDPointerInt); OutputRegisterInt(1) <= FIFO1Int(RDPointerInt); OutputRegisterInt(2) <= FIFO2Int(RDPointerInt); OutputRegisterInt(3) <= FIFO3Int(RDPointerInt); OutputRegisterInt(4) <= FIFO4Int(RDPointerInt); OutputRegisterInt(5) <= FIFO5Int(RDPointerInt); OutputRegisterInt(6) <= FIFO6Int(RDPointerInt); OutputRegisterInt(7) <= FIFO7Int(RDPointerInt); OutputRegisterInt(8) <= FIFO8Int(RDPointerInt); END IF; ELSE IF RENNeg = '0' THEN CASE ReadFnInt is WHEN "00" => ReadFnInt <= "01"; OutputRegisterInt(LSBS DOWNTO 0) <= LSBPAEInt; OutputRegisterInt(8 DOWNTO LSBS+1) <= (others => '0'); WHEN "01" => ReadFnInt <= "10"; OutputRegisterInt(MSBS DOWNTO 0) <= MSBPAEInt; OutputRegisterInt(8 DOWNTO MSBS+1) <= (others => '0'); WHEN "10" => ReadFnInt <= "11"; OutputRegisterInt(LSBS DOWNTO 0) <= LSBPAFInt; OutputRegisterInt(8 DOWNTO LSBS+1) <= (others => '0'); WHEN "11" => OutputRegisterInt(MSBS DOWNTO 0) <= MSBPAFInt; OutputRegisterInt(8 DOWNTO MSBS+1) <= (others => '0'); WHEN others => NULL; END CASE; END IF; END IF; END IF; END IF; -- END SUBPROCESS Read END PROCESS Read_Write; Difference:PROCESS(WRPointerInt, RDPointerInt, MRSNeg, PRSNeg) BEGIN IF MRSNeg = '0' OR PRSNeg = '0' THEN DiffInt <= 0; PrevDiffInt <= 0; ELSE PrevDiffInt <= DiffInt; IF WRPointerInt > RDPointerInt THEN DiffInt <= WRPointerInt - RDPointerInt; ELSIF WRPointerInt < RDPointerInt THEN DiffInt <= WRPointerInt + FIFOSize - RDPointerInt; ELSE IF PrevDiffInt > HalfFullCondInt THEN DiffInt <= FIFOSize; ELSE DiffInt <= 0; END IF; END IF; END IF; END PROCESS; Empty_recovery:PROCESS(RCLK) VARIABLE counter: integer := 0; BEGIN IF RCLK'event AND RCLK = '1' THEN IF WRIntoEmptyInt = '1' THEN counter := counter + 1; IF counter = 3 THEN EmptyRecovInt <= '1'; END IF; ELSE EmptyRecovInt <= '0'; counter := 0; END IF; END IF; END PROCESS; Empty_recovery_extra:PROCESS(InternalClockInt, RTNeg) VARIABLE counter: integer := 0; BEGIN IF RTNeg = '0' THEN EmptyRecovExtraInt <= '0'; ELSIF InternalClockInt'event AND InternalClockInt = '1' THEN IF EmptyRecovInt = '1' THEN counter := counter + 1; IF ModeInt = '0' THEN IF counter = 10 THEN EmptyRecovExtraInt <= '1'; END IF; ELSE IF counter = 11 THEN EmptyRecovExtraInt <= '1'; END IF; END IF; ELSE EmptyRecovExtraInt <= '0'; counter := 0; END IF; END IF; END PROCESS; RT_recovery:PROCESS(InternalClockInt) VARIABLE counter: integer := 0; BEGIN IF InternalClockInt'event AND InternalClockInt = '1' THEN IF RTExtraInt = '1' THEN counter := counter + 1; IF counter = 14 THEN RTEndInt <= '1'; END IF; ELSE RTEndInt <= '0'; counter := 0; END IF; END IF; END PROCESS; RT_recovery_extra:PROCESS(RCLK) VARIABLE counter: integer := 0; BEGIN IF RCLK'event AND RCLK = '1' THEN IF RTBeginInt = '1' THEN counter := counter + 1; IF ModeInt = '0' THEN IF counter = 3 THEN RTExtraInt <= '1'; END IF; ELSE IF counter = 4 THEN RTExtraInt <= '1'; END IF; END IF; ELSE RTExtraInt <= '0'; counter := 0; END IF; END IF; END PROCESS; After_retransmit:PROCESS(RCLK, MRSNeg) BEGIN IF MRSNeg = '0' THEN AfterRTInt <= '0'; AEDisableAfterRTInt <= '0'; ELSE IF RCLK'event AND RCLK = '0' THEN IF RTEndInt = '1' THEN AfterRTInt <= '1'; END IF; IF (ModeInt = '0' AND AfterRTInt = '1' AND RENNeg = '0') OR (ModeInt = '1' AND AfterRTInt = '1') THEN AEDisableAfterRTInt <= '1'; AfterRTInt <= '0'; END IF; IF AEDisableAfterRTInt = '1' THEN AEDisableAfterRTInt <= '0'; END IF; END IF; END IF; END PROCESS; After_RT2:PROCESS(RCLK, MRSNeg, RTBeginInt) BEGIN IF MRSNeg = '0' THEN AfterRTSkew2Int <= '1'; ELSIF RTBeginInt = '1' THEN AfterRTSkew2Int <= '0'; ELSE IF RCLK'event AND RCLK = '1' THEN IF RENNeg = '0' OR ModeInt = '1' THEN AfterRTSkew2Int <= '1' AFTER tdevice_SKEW2; END IF; END IF; END IF; END PROCESS; END BLOCK IDT; ------------------------------------------------------------------------ -- Path delay section -- ------------------------------------------------------------------------ -- path delay for EFORNeg EFORPathDelay: PROCESS (EFORNeg_zd) VARIABLE EFORNeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => EFORNeg, OutSignalName => "EFORNeg", OutTemp => EFORNeg_zd, GlitchData => EFORNeg_GlitchData, Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_EFORNeg, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_EFORNeg, PathCondition => true), 2 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_EFORNeg, PathCondition => MRSNeg = '1' AND PRSNeg = '1'))); END PROCESS EFORPathDelay; -- path delay for PAENeg PAEPathDelay: PROCESS (PAENeg_zd) VARIABLE PAENeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => PAENeg, OutSignalName => "PAENeg", OutTemp => PAENeg_zd, GlitchData => PAENeg_GlitchData, Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_PAENeg, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_PAENeg, PathCondition => true), 2 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_PAENeg, PathCondition => MRSNeg = '1' AND PRSNeg = '1'))); END PROCESS PAEPathDelay; -- path delay for HFNeg HFPathDelay: PROCESS (HFNeg_zd) VARIABLE HFNeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => HFNeg, OutSignalName => "HFNeg", OutTemp => HFNeg_zd, GlitchData => HFNeg_GlitchData, Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_HFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_HFNeg, PathCondition => true), 2 => (InputChangeTime => WCLK'last_event, PathDelay => tpd_WCLK_HFNeg, PathCondition => WENNeg = '0'), 3 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_HFNeg, PathCondition => RENNEg = '0'))); END PROCESS HFPathDelay; -- path delay for PAFNeg PAFPathDelay: PROCESS (PAFNeg_zd) VARIABLE PAFNeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => PAFNeg, OutSignalName => "PAFNeg", OutTemp => PAFNeg_zd, GlitchData => PAFNeg_GlitchData, Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_PAFNeg, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_PAFNeg, PathCondition => true), 2 => (InputChangeTime => WCLK'last_event, PathDelay => tpd_WCLK_PAFNeg, PathCondition => MRSNeg = '1' AND PRSNeg = '1'))); END PROCESS PAFPathDelay; -- path delay for FFIRNeg FFIRPathDelay: PROCESS (FFIRNeg_zd) VARIABLE FFIRNeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => FFIRNeg, OutSignalName => "FFIRNeg", OutTemp => FFIRNeg_zd, GlitchData => FFIRNeg_GlitchData, Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_FFIRNeg, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_FFIRNeg, PathCondition => true), 2 => (InputChangeTime => WCLK'last_event, PathDelay => tpd_WCLK_FFIRNeg, PathCondition => MRSNeg = '1' AND PRSNeg = '1'))); END PROCESS FFIRPathDelay; -- path delay for Q QPathDelay_Gen: FOR i IN Q'range GENERATE PROCESS (Q_zd(i)) VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z (OutSignal => Q(i), OutSignalName => "Q", OutTemp => Q_zd(i), GlitchData => Q_GlitchData, Paths => (0 => (InputChangeTime => MRSNeg'last_event, PathDelay => tpd_MRSNeg_Q0, PathCondition => true), 1 => (InputChangeTime => PRSNeg'last_event, PathDelay => tpd_PRSNeg_Q0, PathCondition => true), 2 => (InputChangeTime => OENEg'last_event, PathDelay => tpd_OENeg_Q0, PathCondition => true), 3 => (InputChangeTime => RCLK'last_event, PathDelay => tpd_RCLK_Q0, PathCondition => RENNeg = '0' AND OENeg = '0' AND RCLK = '1'))); END PROCESS; END GENERATE QPathDelay_Gen; END BLOCK VitalBehavior; END vhdl_behavioral;