-------------------------------------------------------------------------------- -- File Name: cy7c453.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2001 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 B.Bizic 01 Oct 02 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FIFO -- Technology: CMOS -- Part: CY7C453 -- -- Description: Clocked FIFO with Programmable Flags 2,048 x 9 -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY cy7c453 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_ENWNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ENRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CKW : VitalDelayType01 := VitalZeroDelay01; tipd_CKR : VitalDelayType01 := VitalZeroDelay01; tipd_XINeg : VitalDelayType01 := VitalZeroDelay01; tipd_MRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_FLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CKR_Q0 : VitalDelayType01 := UnitDelay01; tpd_MRNeg_Q0 : VitalDelayType01 := UnitDelay01;-- tAMR tpd_MRNeg_ENeg : VitalDelayType01 := UnitDelay01;-- tMEF tpd_CKW_ENeg : VitalDelayType01 := UnitDelay01; tpd_OENeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths tpw_CKR_negedge : VitalDelayType := UnitDelay; tpw_CKR_posedge : VitalDelayType := UnitDelay; tpw_MRNeg_negedge : VitalDelayType := UnitDelay; tpw_FLNeg_negedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CKR : VitalDelayType := UnitDelay; -- tsetup values: setup times tsetup_D0_CKW : VitalDelayType := UnitDelay; --tSD tsetup_ENWNeg_CKW : VitalDelayType := UnitDelay; --tSEN tsetup_CKW_MRNeg : VitalDelayType := UnitDelay; --tSCMR -- thold values: hold times thold_D0_CKW : VitalDelayType := UnitDelay; --tHD thold_ENWNeg_CKW : VitalDelayType := UnitDelay; --tHEN -- tskew time:skew times tdevice_SKEW1 : VitalDelayType := UnitDelay; -- tSKEW1 tdevice_SKEW2 : VitalDelayType := UnitDelay; -- tSKEW2 -- trecovery time:recovery time trecovery_CKW_MRNeg : VitalDelayType := UnitDelay; -- tMRR trecovery_ENRNeg_FLNeg : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN STD_ULOGIC := 'U'; D1 : IN STD_ULOGIC := 'U'; D2 : IN STD_ULOGIC := 'U'; D3 : IN STD_ULOGIC := 'U'; D4 : IN STD_ULOGIC := 'U'; D5 : IN STD_ULOGIC := 'U'; D6 : IN STD_ULOGIC := 'U'; D7 : IN STD_ULOGIC := 'U'; D8 : IN STD_ULOGIC := 'U'; Q0 : OUT STD_ULOGIC := 'U'; Q1 : OUT STD_ULOGIC := 'U'; Q2 : OUT STD_ULOGIC := 'U'; Q3 : OUT STD_ULOGIC := 'U'; Q4 : OUT STD_ULOGIC := 'U'; Q5 : OUT STD_ULOGIC := 'U'; Q6 : OUT STD_ULOGIC := 'U'; Q7 : OUT STD_ULOGIC := 'U'; Q8 : OUT STD_ULOGIC := 'U'; ENWNeg : IN STD_ULOGIC := 'U'; ENRNeg : IN STD_ULOGIC := 'U'; CKW : IN STD_ULOGIC := 'U'; CKR : IN STD_ULOGIC := 'U'; ENeg : OUT STD_ULOGIC := 'U'; FLNeg : IN STD_ULOGIC := 'U'; MRNeg : IN STD_ULOGIC := 'U'; OENeg : IN STD_ULOGIC := 'U'; XINeg : IN STD_ULOGIC := 'U'; HFNeg : OUT STD_ULOGIC := 'U'; XONeg : OUT STD_ULOGIC := 'U' ); ATTRIBUTE VITAL_LEVEL0 of cy7c453 : ENTITY IS TRUE; END cy7c453; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of cy7c453 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "CY7C453"; SIGNAL D0_ipd : STD_ULOGIC := 'U'; SIGNAL D1_ipd : STD_ULOGIC := 'U'; SIGNAL D2_ipd : STD_ULOGIC := 'U'; SIGNAL D3_ipd : STD_ULOGIC := 'U'; SIGNAL D4_ipd : STD_ULOGIC := 'U'; SIGNAL D5_ipd : STD_ULOGIC := 'U'; SIGNAL D6_ipd : STD_ULOGIC := 'U'; SIGNAL D7_ipd : STD_ULOGIC := 'U'; SIGNAL D8_ipd : STD_ULOGIC := 'U'; SIGNAL ENWNeg_ipd : STD_ULOGIC := 'U'; SIGNAL ENRNeg_ipd : STD_ULOGIC := 'U'; SIGNAL CKW_ipd : STD_ULOGIC := 'U'; SIGNAL CKR_ipd : STD_ULOGIC := 'U'; SIGNAL XINeg_ipd : STD_ULOGIC := 'U'; SIGNAL FLNeg_ipd : STD_ULOGIC := 'U'; SIGNAL MRNeg_ipd : STD_ULOGIC := 'U'; SIGNAL OENeg_ipd : STD_ULOGIC := 'U'; -- No Weak Values -- SIGNAL D0_nwv : STD_ULOGIC := 'U'; SIGNAL D1_nwv : STD_ULOGIC := 'U'; SIGNAL D2_nwv : STD_ULOGIC := 'U'; SIGNAL D3_nwv : STD_ULOGIC := 'U'; SIGNAL D4_nwv : STD_ULOGIC := 'U'; SIGNAL D5_nwv : STD_ULOGIC := 'U'; SIGNAL D6_nwv : STD_ULOGIC := 'U'; SIGNAL D7_nwv : STD_ULOGIC := 'U'; SIGNAL D8_nwv : STD_ULOGIC := 'U'; SIGNAL ENWNeg_nwv : STD_ULOGIC := 'U'; SIGNAL ENRNeg_nwv : STD_ULOGIC := 'U'; SIGNAL CKW_nwv : STD_ULOGIC := 'U'; SIGNAL CKR_nwv : STD_ULOGIC := 'U'; SIGNAL XINeg_nwv : STD_ULOGIC := 'U'; SIGNAL FLNeg_nwv : STD_ULOGIC := 'U'; SIGNAL MRNeg_nwv : STD_ULOGIC := 'U'; SIGNAL OENeg_nwv : STD_ULOGIC := 'U'; -- FIFO memory definations CONSTANT FIFOSize : POSITIVE := 2048; CONSTANT FIFOWordLenght : POSITIVE := 9; TYPE FIFOArray IS array (0 to FIFOSize) of INTEGER RANGE -2 TO 511; -- internal signals SIGNAL CountPointer : NATURAL RANGE 0 TO FIFOSize :=0; SIGNAL ReadPointer : NATURAL RANGE 0 TO FIFOSize :=0; SIGNAL WritePointer : NATURAL RANGE 0 TO FIFOSize :=0; SIGNAL EmptyOffReg : NATURAL:=16; SIGNAL FullOffReg : NATURAL:=16; SIGNAL ProgReg : STD_LOGIC_VECTOR(FIFOWordLenght - 1 DOWNTO 0) :="000000001"; SIGNAL Start : STD_ULOGIC := '0'; SIGNAL parity_enable : BOOLEAN:=FALSE; SIGNAL parity_odd_even : STD_LOGIC; SIGNAL parity_generate : BOOLEAN:=FALSE; -- SKEW stuff (see also generics list) ALIAS tSKEW1 : VitalDelayType IS tdevice_SKEW1; ALIAS tSKEW2 : VitalDelayType IS tdevice_SKEW2; SIGNAL tSKEW_CKW_CKR : Time := 0 ns; -- actual /CKW/CKR skew time SIGNAL tSKEW_CKR_CKW : Time := 0 ns; -- actual /CKR/CKW skew time SIGNAL OpenIn, OpenOut : STD_LOGIC; ALIAS tCKR : VitalDelayType IS tperiod_CKR; ALIAS tCKW : VitalDelayType IS tperiod_CKR; BEGIN -------------------------------------------------------------------------------- -- Dummy instances for exporting tSKEW vals from SDF file -- using DEVICE construct -------------------------------------------------------------------------------- SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1)); SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2)); ------------------------------------------------------------------- -- Wire Delays ------------------------------------------------------------------- WireDelay: BLOCK BEGIN w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0); w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1); w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2); w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3); w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4); w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5); w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6); w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7); w_9 : VitalWireDelay (D8_ipd, D8, tipd_D8); w_20 : VitalWireDelay (ENWNeg_ipd, ENWNeg, tipd_ENWNeg); w_21 : VitalWireDelay (ENRNeg_ipd, ENRNeg, tipd_ENRNeg); w_22 : VitalWireDelay (CKW_ipd, CKW, tipd_CKW); w_23 : VitalWireDelay (CKR_ipd, CKR, tipd_CKR); w_24 : VitalWireDelay (XINeg_ipd, XINeg, tipd_XINeg); w_25 : VitalWireDelay (FLNeg_ipd, FLNeg, tipd_FLNeg); w_26 : VitalWireDelay (MRNeg_ipd, MRNeg, tipd_MRNeg); w_27 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); END BLOCK WireDelay; D0_nwv <= To_UX01 (s => D0_ipd); D1_nwv <= To_UX01 (s => D1_ipd); D2_nwv <= To_UX01 (s => D2_ipd); D3_nwv <= To_UX01 (s => D3_ipd); D4_nwv <= To_UX01 (s => D4_ipd); D5_nwv <= To_UX01 (s => D5_ipd); D6_nwv <= To_UX01 (s => D6_ipd); D7_nwv <= To_UX01 (s => D7_ipd); D8_nwv <= To_UX01 (s => D8_ipd); ENWNeg_nwv <= To_UX01 (s => ENWNeg_ipd); ENRNeg_nwv <= To_UX01 (s => ENRNeg_ipd); CKW_nwv <= To_UX01 (s => CKW_ipd); CKR_nwv <= To_UX01 (s => CKR_ipd); MRNeg_nwv <= To_UX01 (s => MRNeg_ipd); OENeg_nwv <= To_UX01 (s => OENeg_ipd); XINeg_nwv <= To_UX01 (s => XINeg_ipd); FLNeg_nwv <= To_UX01 (s => FLNeg_ipd); ------------------------------------------------------------------- -- Main behavior Block ------------------------------------------------------------------- VitalBehavior: BLOCK PORT ( Data : IN STD_LOGIC_VECTOR(FIFOWordLenght-1 downto 0); Q : OUT STD_LOGIC_VECTOR(FIFOWordLenght-1 downto 0); ENWNeg : IN std_Ulogic := 'U'; ENRNeg : IN std_Ulogic := 'U'; CKW : IN std_Ulogic := 'U'; CKR : IN std_Ulogic := 'U'; HFNeg : OUT std_Ulogic := 'U'; ENeg : OUT std_Ulogic := 'U'; XONeg : OUT std_Ulogic := 'U'; XINeg : IN std_Ulogic := 'U'; FLNeg : IN std_Ulogic := 'U'; MRNeg : IN std_Ulogic := 'U'; OENeg : IN std_Ulogic := 'U' ); PORT MAP ( Data(0) => D0_nwv, Data(1) => D1_nwv, Data(2) => D2_nwv, Data(3) => D3_nwv, Data(4) => D4_nwv, Data(5) => D5_nwv, Data(6) => D6_nwv, Data(7) => D7_nwv, Data(8) => D8_nwv, Q(0) => Q0, Q(1) => Q1, Q(2) => Q2, Q(3) => Q3, Q(4) => Q4, Q(5) => Q5, Q(6) => Q6, Q(7) => Q7, Q(8) => Q8, ENWNeg => ENWNeg_nwv, ENRNeg => ENRNeg_nwv, CKW => CKW_nwv, CKR => CKR_nwv, XINeg => XINeg_nwv, FLNeg => FLNeg_nwv, MRNeg => MRNeg_nwv, OENeg => OENeg_nwv, HFNeg => HFNeg, ENeg => ENeg, XONeg => XONeg ); SIGNAL ENeg_zd : STD_ULOGIC := 'X'; --------------------- SIGNAL HFNeg_zd : STD_ULOGIC := 'X'; -- regs for output -- SIGNAL XONeg_zd : STD_ULOGIC := 'X'; -- flags -- SIGNAL Q_zd : STD_LOGIC_VECTOR(FIFOWordLenght-1 DOWNTO 0) :=(OTHERS=>'X'); BEGIN -- VitalBehavior block --------------------------------------------------------------- -- Timinf Check Section --------------------------------------------------------------- MainReadWrite:PROCESS (Data,ENWNeg, ENRNeg, CKW, CKR, FLNeg, MRNeg, XINeg, OENeg) VARIABLE FIFOMemory : FIFOArray; TYPE fifo_mode_type IS (unk, single, first_exp, other_exp); TYPE stat_type IS (inact, act); VARIABLE check_parity : STD_LOGIC:='X'; VARIABLE fifo_mode : fifo_mode_type:=unk; VARIABLE rd_stat : stat_type; VARIABLE wr_stat : stat_type ; VARIABLE wr_inhibit : BOOLEAN := false; VARIABLE program_wr : BOOLEAN := false; VARIABLE DataReg : STD_LOGIC_VECTOR(FIFOWordLenght - 1 DOWNTO 0); -- Timing Check Variables VARIABLE Tviol_D0_CKW : X01 := '0'; VARIABLE TD_D0_CKW : VitalTimingDataType; VARIABLE Tviol_MRNeg_CKW : X01 := '0'; VARIABLE TD_MRNeg_CKW : VitalTimingDataType; VARIABLE Tviol_MRNeg_CKR : X01 := '0'; VARIABLE TD_MRNeg_CKR : VitalTimingDataType; VARIABLE Tviol_ENWNeg_CKW : X01 := '0'; VARIABLE TD_ENWNeg_CKW : VitalTimingDataType; VARIABLE Tviol_ENRNeg_CKR : X01 := '0'; VARIABLE TD_ENRNeg_CKR : VitalTimingDataType; VARIABLE Tviol_CKW_MRNeg : X01 := '0'; VARIABLE TD_CKW_MRNeg : VitalTimingDataType; VARIABLE Tviol_CKR_MRNeg : X01 := '0'; VARIABLE TD_CKR_MRNeg : VitalTimingDataType; VARIABLE Pviol_CKW : X01 := '0'; VARIABLE TD_CKW : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CKR : X01 := '0'; VARIABLE TD_CKR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_FLNeg : X01 := '0'; VARIABLE TD_FLNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MRNeg : X01 := '0'; VARIABLE TD_MRNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Rviol_CKW_MRNeg : X01 := '0'; VARIABLE RD_CKW_MRNeg : VitalTimingDataType; VARIABLE Rviol_CKR_MRNeg : X01 := '0'; VARIABLE RD_CKR_MRNeg : VitalTimingDataType; VARIABLE Rviol_ENRNeg_FLNeg : X01 := '0'; VARIABLE RD_ENRNeg_FLNeg : VitalTimingDataType; VARIABLE Rviol_ENWNeg_FLNeg : X01 := '0'; VARIABLE RD_ENWNeg_FLNeg : VitalTimingDataType; -- Functionality Results Variables VARIABLE Violation : X01 := '0'; BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => Data, TestSignalName => "D", RefSignal => CKW, RefSignalName => "CKW", SetupHigh => tsetup_D0_CKW, SetupLow => tsetup_D0_CKW, HoldHigh => thold_D0_CKW, HoldLow => thold_D0_CKW, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_D0_CKW, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_CKW); VitalSetupHoldCheck ( TestSignal => ENWNeg, TestSignalName => "ENWNeg", RefSignal => CKW, RefSignalName => "CKW", SetupHigh => tsetup_ENWNeg_CKW, SetupLow => tsetup_ENWNeg_CKW, HoldHigh => thold_ENWNeg_CKW, HoldLow => thold_ENWNeg_CKW, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ENWNeg_CKW, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ENWNeg_CKW ); VitalSetupHoldCheck ( TestSignal => ENRNeg, TestSignalName => "ENRNeg", RefSignal => CKR, RefSignalName => "CKR", SetupHigh => tsetup_ENWNeg_CKW, SetupLow => tsetup_ENWNeg_CKW, HoldHigh => thold_ENWNeg_CKW, HoldLow => thold_ENWNeg_CKW, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ENRNeg_CKR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ENRNeg_CKR ); VitalSetupHoldCheck ( TestSignal => CKW, TestSignalName => "RNeg", RefSignal => MRNeg, RefSignalName => "MRNeg", SetupLow => tsetup_CKW_MRNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKW_MRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CKW_MRNeg ); VitalSetupHoldCheck ( TestSignal => CKR, TestSignalName => "RNeg", RefSignal => MRNeg, RefSignalName => "MRNeg", SetupLow => tsetup_CKW_MRNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CKR_MRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CKR_MRNeg ); VitalPeriodPulseCheck ( TestSignal => CKR, TestSignalName => "CKR", Period => tperiod_CKR, PulseWidthLow => tpw_CKR_negedge, PulseWidthHigh => tpw_CKR_posedge, PeriodData => TD_CKR, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE, Violation => Pviol_CKR ); VitalPeriodPulseCheck ( TestSignal => CKW, TestSignalName => "CKW", Period => tperiod_CKR, PulseWidthLow => tpw_CKR_negedge, PulseWidthHigh => tpw_CKR_posedge, PeriodData => TD_CKW, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE, Violation => Pviol_CKW ); VitalPeriodPulseCheck ( TestSignal => MRNeg, TestSignalName => "MRNeg", PulseWidthLow => tpw_MRNeg_negedge, PeriodData => TD_MRNeg, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE, Violation => Pviol_MRNeg ); VitalPeriodPulseCheck ( TestSignal => FLNeg, TestSignalName => "MRNeg", PulseWidthLow => tpw_FLNeg_negedge, PeriodData => TD_FLNeg, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE, Violation => Pviol_FLNeg ); VitalRecoveryRemovalCheck ( TestSignal => CKW, TestSignalName => "CKW", RefSignal => MRNeg, RefSignalName => "MRNeg", Recovery => trecovery_CKW_MRNeg, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_CKW_MRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_CKW_MRNeg); VitalRecoveryRemovalCheck ( TestSignal => CKR, TestSignalName => "CKR", RefSignal => MRNeg, RefSignalName => "MRNeg", Recovery => trecovery_CKW_MRNeg, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_CKR_MRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_CKR_MRNeg); VitalRecoveryRemovalCheck ( TestSignal => ENWNeg, TestSignalName => "ENWNeg", RefSignal => FLNeg, RefSignalName => "FLNeg", Recovery => trecovery_ENRNeg_FLNeg, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_ENWNeg_FLNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_ENWNeg_FLNeg); VitalRecoveryRemovalCheck ( TestSignal => ENRNeg, TestSignalName => "ENRNeg", RefSignal => FLNeg, RefSignalName => "FLNeg", Recovery => trecovery_ENRNeg_FLNeg, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_ENRNeg_FLNeg, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_ENRNeg_FLNeg); Violation := Tviol_D0_CKW OR Pviol_CKR OR Pviol_CKW OR Pviol_MRNeg OR Rviol_ENWNeg_FLNeg OR Rviol_ENRNeg_FLNeg OR Rviol_CKW_MRNeg OR Rviol_CKR_MRNeg; ASSERT Violation = '0' REPORT InstancePath & partID & " : signal values may be" & " incorrect due timing violation(s)" SEVERITY Warning; END IF; -- Timing Check Section --------------------------------------------------------------- -- Functionality section --------------------------------------------------------------- IF falling_edge(MRNeg) THEN Start <= '0'; WritePointer <= 0; ReadPointer <= 0; CountPointer <= 0; parity_enable <= FALSE; EmptyOffReg <= 16; FullOffReg <= 16; wr_inhibit := FALSE; ELSIF rising_edge(MRNeg) THEN IF NOT program_wr THEN ProgReg <= "000000001"; END IF; ENeg_zd <= '0'; HFNeg_zd <= '1'; XONeg_zd <= '0'; Start <= '1'; IF OENeg = '0' THEN Q_zd <= (OTHERS => '0'); ELSIF OENeg = '1' THEN Q_zd <= (OTHERS => 'Z'); END IF; IF XINeg='0' THEN fifo_mode := single; rd_stat := act; wr_stat := act; ELSIF FLNeg='0' THEN fifo_mode := first_exp; rd_stat := act; wr_stat := act; ELSE fifo_mode := other_exp; rd_stat := inact; wr_stat := inact; END IF; ELSIF MRNeg='0' THEN IF rising_edge(CKW) AND ENWNeg = '0' THEN program_wr:=TRUE; EmptyOffReg <= 16*to_nat(Data(5 DOWNTO 0)); FullOffReg <= 16*to_nat(Data(5 DOWNTO 0)); ProgReg <= Data; IF Data(8)='0' THEN parity_enable<=FALSE; ELSE parity_enable<=TRUE; END IF; IF Data(7)='0' THEN parity_generate<=TRUE; ELSE parity_generate<=FALSE; END IF; parity_odd_even<=Data(6); END IF; IF rising_edge(CKR) AND ENRNeg = '0' THEN IF OENeg = '0' THEN Q_zd <= ProgReg; ELSIF OENeg = '1' THEN Q_zd <= (OTHERS => 'Z'); END IF; END IF; END IF; IF Start = '1' THEN -- Read/Write Cycles DataReg := Data; -- Write Cycle IF rising_edge(CKW) AND ENWNeg ='0' THEN IF wr_stat=act AND NOT wr_inhibit THEN IF parity_enable THEN IF parity_generate THEN DataReg := GenParity(Data,parity_odd_even,8); ELSE check_parity:=CheckParity(Data, parity_odd_even,9); IF check_parity=Data(8) THEN DataReg(8) := '1'; ELSE DataReg(8) :='0'; END IF; END IF; END IF; IF Violation ='0' THEN FIFOMemory( WritePointer ) := to_nat(DataReg); ELSE FIFOMemory( WritePointer ) := -1; END IF; IF WritePointer < FIFOSize THEN WritePointer <=WritePointer + 1; ELSE WritePointer <=0; END IF; CountPointer <= CountPointer + 1; IF CountPointer > (FIFOSize - FullOffReg - 1) THEN IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKW); END IF; END IF; IF CountPointer = FIFOSize - 1 THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '0'; ELSE ENeg_zd <= '0' AFTER (tCKW); END IF; wr_inhibit := TRUE; END IF; IF CountPointer < FIFOSize/2 - 1 THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '1'; ELSE HFNeg_zd <= '1' AFTER (tCKW); END IF; ELSE IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '0'; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; END IF; IF fifo_mode/=single THEN IF CountPointer = FIFOSize - 1 THEN IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKW); END IF; ELSE IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKW); END IF; END IF; END IF; END IF; END IF; -- End of Write Cycle -- Read Cycle IF rising_edge(CKR) AND ENRNeg = '0' THEN IF rd_stat=act THEN wr_inhibit := FALSE; IF ReadPointer= FIFOSize THEN ReadPointer<=0; ELSE ReadPointer<=ReadPointer + 1; END IF; CountPointer <= CountPointer - 1; IF CountPointer = 1 THEN rd_stat := inact; IF tSKEW_CKW_CKR >= tSKEW1 THEN ENeg_zd <= '0'; ELSE ENeg_zd <= '0' AFTER (tCKR); END IF; ELSE IF tSKEW_CKW_CKR >= tSKEW1 THEN ENeg_zd <= '1'; ELSE ENeg_zd <= '1' AFTER (tCKR); END IF; END IF; IF fifo_mode = single THEN IF CountPointer <= EmptyOffReg + 1 THEN IF tSKEW_CKW_CKR >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKR); END IF; ELSE IF tSKEW_CKW_CKR >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKR); END IF; END IF; END IF; IF fifo_mode /= single AND CountPointer = 0 THEN IF tSKEW_CKW_CKR >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKR); END IF; rd_stat := inact; END IF; END IF; IF OENeg = '0' THEN IF (FIFOMemory(ReadPointer)>=0) THEN Q_zd <= to_slv(FIFOMemory(ReadPointer),9); ELSE Q_zd <= (OTHERS=>'X'); END IF; END IF; END IF; -- End of Read Cycle IF falling_edge(FLNeg) THEN -- Expansion Check IF XINeg='0' THEN ReadPointer <= 0; CountPointer <= WritePointer; IF CountPointer = 0 THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '0'; ELSE ENeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '1'; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKR); END IF; ELSIF CountPointer < EmptyOffReg THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '1'; ELSE ENeg_zd <= '1' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '1' ; ELSE HFNeg_zd <= '1' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKR); END IF; ELSIF CountPointer < FIFOSize/2 THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '1'; ELSE ENeg_zd <= '1' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '0' ; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKR); END IF; ELSIF CountPointer < FIFOSize-FullOffReg THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '1'; ELSE ENeg_zd <= '1' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '0' ; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKR); END IF; ELSIF CountPointer < FIFOSize THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '1'; ELSE ENeg_zd <= '1' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '0' ; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKR); END IF; ELSE IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '0'; ELSE ENeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '0' ; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKR); END IF; END IF; ELSE IF ENWNeg='1' AND ENRNeg='1' THEN ReadPointer <= 0; -- Retransmit END IF; END IF; ELSIF falling_edge(XINeg) AND fifo_mode = other_exp THEN IF wr_stat = inact THEN wr_stat := act; ELSE rd_stat := act; END IF; END IF; -- End of Expansion Checking IF rising_edge(OENeg) THEN Q_zd <= ( OTHERS => 'Z' ); END IF; END IF; -- End of Start END PROCESS MainReadWrite; ------------------------------------------------------------------------ -- Detection of the actual tSKEW vals -- ------------------------------------------------------------------------ SkewDetector: PROCESS(CKR, CKW) VARIABLE tCKRposedge : Time := 0 ns; VARIABLE tCKWposedge : Time := 0 ns; BEGIN IF CKR'event AND CKR = '1' THEN tCKRposedge := Now; tSKEW_CKW_CKR <= Now - tCKWposedge; END IF; IF CKW'event AND CKW = '1' THEN tCKWposedge := Now; tSKEW_CKR_CKW <= Now - tCKRposedge; END IF; END PROCESS SkewDetector; ------------------------------------------------------------------------ -- Path delay section -- ------------------------------------------------------------------------ -- path delay for ENeg EFPathDelay: PROCESS (ENeg_zd) VARIABLE ENeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => ENeg, OutSignalName => "ENeg", OutTemp => ENeg_zd, GlitchData => ENeg_GlitchData, Paths => (0 => (InputChangeTime => MRNeg'LAST_EVENT, PathDelay => tpd_MRNeg_ENeg, PathCondition => true), 1 => (InputChangeTime => CKR'LAST_EVENT, PathDelay => tpd_CKW_ENeg, PathCondition => true), 2 => (InputChangeTime => CKW'LAST_EVENT, PathDelay => tpd_CKW_ENeg, PathCondition => true))); END PROCESS EFPathDelay; -- path delay for XONeg PAEPathDelay: PROCESS (XONeg_zd) VARIABLE XONeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => XONeg, OutSignalName => "XONeg", OutTemp => XONeg_zd, GlitchData => XONeg_GlitchData, Paths => (0 => (InputChangeTime => MRNeg'LAST_EVENT, PathDelay => tpd_MRNeg_ENeg, PathCondition => true), 1 => (InputChangeTime => CKR'LAST_EVENT, PathDelay => tpd_CKW_ENeg, PathCondition => true), 2 => (InputChangeTime => CKW'LAST_EVENT, PathDelay => tpd_CKW_ENeg, PathCondition => true))); END PROCESS PAEPathDelay; -- path delay for HFNeg HFPathDelay: PROCESS (HFNeg_zd) VARIABLE HFNeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => HFNeg, OutSignalName => "HFNeg", OutTemp => HFNeg_zd, GlitchData => HFNeg_GlitchData, Paths => (0 => (InputChangeTime => MRNeg'LAST_EVENT, PathDelay => tpd_MRNeg_ENeg, PathCondition => true), 1 => (InputChangeTime => CKW'LAST_EVENT, PathDelay => tpd_CKW_ENeg, PathCondition => true))); END PROCESS HFPathDelay; -- path delay for ENeg QPathDelay_Gen: FOR i IN FIFOWordLenght-1 DOWNTO 0 GENERATE PROCESS (Q_zd(i)) VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z (OutSignal => Q(i), OutSignalName => "Q", OutTemp => Q_zd(i), GlitchData => Q_GlitchData, Paths =>(0 =>(InputChangeTime => MRNeg'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_MRNeg_Q0), PathCondition =>true), 1 =>(InputChangeTime => CKR'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CKR_Q0), PathCondition =>true), 2 =>(InputChangeTime =>OENeg'LAST_EVENT, PathDelay =>tpd_OENeg_Q0, PathCondition =>TRUE))); END PROCESS; END GENERATE QPathDelay_Gen; END BLOCK VitalBehavior; END vhdl_behavioral;