-------------------------------------------------------------------------------- -- File name: eclpss838.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Steele 98 JAN 05 Conformed to style guide -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPSS838 -- -- Description: Divide by 2 and Divide by 4 or 6 or -- Divide by 1 and Divide by 2 or 3 Clock Generation Chip -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.numeric_std.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.gen_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclpss838 IS GENERIC ( -- tipd delays: interconnect path delays tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_MR : VitalDelayType01 := VitalZeroDelay01; tipd_DIVSEL : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CLK_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_MR_Q0 : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_ENNeg_CLK : VitalDelayType := ECLUnitDelay; tsetup_DIVSEL_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_ENNeg_CLK : VitalDelayType := ECLUnitDelay; thold_DIVSEL_CLK : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_MR_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_MR_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); port ( -- 0 denotes pull-down resistor CLK : IN std_logic := '0'; CLKNeg : IN std_logic := '0'; ENNeg : IN std_logic := '0'; MR : IN std_logic := '0'; DIVSEL : IN std_logic := '0'; FSEL : IN std_logic := '0'; Q0 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q0Neg : OUT std_logic := 'U'; Q1Neg : OUT std_logic := 'U'; Q2Neg : OUT std_logic := 'U'; Q3Neg : OUT std_logic := 'U'; VBB : OUT std_logic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF eclpss838 : ENTITY IS TRUE; END eclpss838; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclpss838 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL ENNeg_ipd : std_ulogic := 'X'; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL DIVSEL_ipd : std_ulogic := 'X'; SIGNAL FSEL_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_2: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_3: VitalWireDelay (ENNeg_ipd, ENNeg, tipd_ENNeg); w_4: VitalWireDelay (MR_ipd, MR, tipd_MR); w_5: VitalWireDelay (DIVSEL_ipd, DIVSEL, tipd_DIVSEL); w_6: VitalWireDelay (FSEL_ipd, FSEL, tipd_FSEL); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- -- Differential outputs a_1: VitalBUF (q => Q0, a => Q0int, ResultMap => ECL_wired_or_rmap); a_2: VitalINV (q => Q0Neg, a => Q0int, ResultMap => ECL_wired_or_rmap); a_3: VitalBUF (q => Q1, a => Q0int, ResultMap => ECL_wired_or_rmap); a_4: VitalINV (q => Q1Neg, a => Q0int, ResultMap => ECL_wired_or_rmap); a_5: VitalBUF (q => Q2, a => Q2int, ResultMap => ECL_wired_or_rmap); a_6: VitalINV (q => Q2Neg, a => Q2int, ResultMap => ECL_wired_or_rmap); a_7: VitalBUF (q => Q3, a => Q2int, ResultMap => ECL_wired_or_rmap); a_8: VitalINV (q => Q3Neg, a => Q2int, ResultMap => ECL_wired_or_rmap); ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (CLK_ipd, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE PrevData : std_logic_vector(0 to 2); VARIABLE CLK_zd : std_ulogic; BEGIN Mode := ECL_diff_mode_tab (CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode), Result => CLK_zd, PreviousDataIn => PrevData ); CLKint <= CLK_zd; END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, MR_ipd, ENNeg_ipd, DIVSEL_ipd) -- Timing Check Variables VARIABLE Tviol_ENNeg_CLK : X01 := '0'; VARIABLE TD_ENNeg_CLK : VitalTimingDataType; VARIABLE Tviol_DIVSEL_CLK: X01 := '0'; VARIABLE TD_DIVSEL_CLK : VitalTimingDataType; VARIABLE Rviol_MR_CLK : X01 := '0'; VARIABLE TD_MR_CLK : VitalTimingDataType; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_MR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MR : X01 := '0'; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Count3 : unsigned(2 downto 0):= (OTHERS => 'X'); VARIABLE Count6 : unsigned(3 downto 0):= (OTHERS => 'X'); VARIABLE NextCount3 : unsigned(2 downto 0):= (OTHERS => 'X'); VARIABLE NextCount6 : unsigned(3 downto 0):= (OTHERS => 'X'); VARIABLE EdgeCount : NATURAL; VARIABLE Out1 : std_ulogic; VARIABLE Out2or3 : std_ulogic; VARIABLE Out4or6 : std_ulogic; VARIABLE Q0_zd : std_ulogic; VARIABLE Q2_zd : std_ulogic; VARIABLE Divided3 : std_ulogic; VARIABLE LastENNeg : std_ulogic; VARIABLE FirstPass : BOOLEAN; -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; -- No Weak Values Variables VARIABLE MR_nwv : UX01 := 'X'; VARIABLE ENNeg_nwv : UX01 := 'X'; VARIABLE DIVSEL_nwv : UX01 := 'X'; VARIABLE FSEL_nwv : UX01 := 'X'; BEGIN MR_nwv := To_UX01 (s => MR_ipd); ENNeg_nwv := To_UX01 (s => ENNeg_ipd); DIVSEL_nwv := To_UX01 (s => DIVSEL_ipd); FSEL_nwv := To_UX01 (s => FSEL_ipd); ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => ENNeg_ipd, TestSignalName => "ENNeg_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_ENNeg_CLK, SetupLow => tsetup_ENNeg_CLK, HoldHigh => thold_ENNeg_CLK, HoldLow => thold_ENNeg_CLK, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/eclpss838", TimingData => TD_ENNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ENNeg_CLK ); VitalSetupHoldCheck ( TestSignal => DIVSEL_ipd, TestSignalName => "DIVSEL_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_DIVSEL_CLK, SetupLow => tsetup_DIVSEL_CLK, HoldHigh => thold_DIVSEL_CLK, HoldLow => thold_DIVSEL_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclpss838", TimingData => TD_DIVSEL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DIVSEL_CLK ); VitalRecoveryRemovalCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", RefSignal => CLKint, RefSignalName => "CLKint", Recovery => trecovery_MR_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclpss838", TimingData => TD_MR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MR_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, HeaderMsg => InstancePath & "/eclpss838", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => MR_ipd, TestSignalName => "MR_ipd", PulseWidthHigh => tpw_MR_posedge, HeaderMsg => InstancePath & "/eclpss838", CheckEnabled => TRUE, PeriodData => PD_MR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MR ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_MR OR Pviol_CLK OR Rviol_MR_CLK OR Tviol_DIVSEL_CLK OR Tviol_ENNeg_CLK; IF (Pviol_MR = 'X') THEN Q0_zd := 'X'; Q2_zd := 'X'; ELSIF (MR_nwv = '1') THEN NextCount3 := "011"; NextCount6 := "0110"; Count3 := "000"; Count6 := "0000"; LastENNeg := '0'; Q0_zd := '0'; Q2_zd := '0'; Out1 := '0'; Out2or3 := '0'; Out4or6 := '0'; EdgeCount := 2; FirstPass := TRUE; Divided3 := '0'; ELSIF (Violation = 'X') THEN Q0_zd := 'X'; Q2_zd := 'X'; --Sync. enable and divide by 3 toggle-- ELSIF (CLKint = '0' AND CLKint'EVENT) THEN LastENNeg := ENNeg_nwv; IF FirstPass = TRUE THEN NULL; ELSE IF EdgeCount = 2 THEN EdgeCount := 0; Divided3 := NOT Divided3; ELSE EdgeCount := EdgeCount + 1; END IF; END IF; --select divide 2 or 3 output-- IF (DIVSEL_nwv = '1') THEN Out2or3 := Divided3; ELSE Out2or3 := Count3(0); END IF; --Divide by 1 (needed to keep Q0 synchronous)-- Out1 := CLKint; --Sync. count-- ELSIF (CLKint = '1' AND CLKint'EVENT AND LastENNeg = '0') THEN FirstPass := FALSE; Count3 := NextCount3; Count6 := NextCount6; --clock generation for divide 3 and 6-- IF EdgeCount = 2 THEN EdgeCount := 0; Divided3 := NOT Divided3; ELSE EdgeCount := EdgeCount + 1; END IF; --select divide 2 or 3 output-- IF (DIVSEL_nwv = '1') THEN Out2or3 := Divided3; ELSE Out2or3 := Count3(0); END IF; --select divide 4 or 6 output-- IF (DIVSEL_nwv = '0') THEN Out4or6 := Count3(1); ELSE Out4or6 := Count6(2); END IF; --clock generation for divide 2 and 4 -- NextCount3 := ('0' & NextCount3(1 downto 0)) - to_unsigned(1,1); NextCount6 := ('0' & NextCount6(2 downto 0)) - to_unsigned(1,1); IF (NextCount6(2 downto 0) = "000") THEN NextCount6 := "0110"; END IF; --Divide by 1 (needed to keep Q0 synchronous)-- Out1 := CLKint; END IF; --Function select-- IF (FSEL_nwv = '1') THEN Q0_zd := Out1; Q2_zd := Out2or3; ELSE Q0_zd := Count3(0); Q2_zd := Out4or6; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0int", OutTemp => Q0_zd, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2int", OutTemp => Q2_zd, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;