-------------------------------------------------------------------------------- -- File Name: eclpsl34.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V3.0 R. Steele 98 MAY 20 Rewritten to make it synchronous -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPSL34 -- -- Description: Divide by 2, 4, and 8 with Reset and Differential Clock -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclpsl34 IS GENERIC ( -- tipd delays: interconnect path delays tipd_MR : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ENNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_MR_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q1 : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q2 : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_ENNeg_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_ENNeg_CLK : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor MR : IN std_logic := '0'; CLK : IN std_logic := '0'; CLKNeg : IN std_logic := '0'; ENNeg : IN std_logic := '0'; Q0 : OUT std_logic := 'U'; Q0Neg : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q1Neg : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q2Neg : OUT std_logic := 'U'; VBB : OUT std_logic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF eclpsl34 : ENTITY IS TRUE; END eclpsl34; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclpsl34 IS ATTRIBUTE VITAL_level0 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL MR_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL ENNeg_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Eint : std_ulogic := 'X'; SIGNAL Q0int : std_ulogic := 'X'; SIGNAL Q1int : std_ulogic := 'X'; SIGNAL Q2int : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (MR_ipd, MR, tipd_MR); w_2: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_3: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_4: VitalWireDelay (ENNeg_ipd, ENNeg, tipd_ENNeg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q0, a => Q0int, ResultMap => ECL_wired_or_rmap); a_2: VitalINV (q => Q0Neg, a => Q0int, ResultMap => ECL_wired_or_rmap); a_3: VitalBUF (q => Q1, a => Q1int, ResultMap => ECL_wired_or_rmap); a_4: VitalINV (q => Q1Neg, a => Q1int, ResultMap => ECL_wired_or_rmap); a_5: VitalBUF (q => Q2, a => Q2int, ResultMap => ECL_wired_or_rmap); a_6: VitalINV (q => Q2Neg, a => Q2int, ResultMap => ECL_wired_or_rmap); ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (CLK_ipd, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(1 to 3); -- Output Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab (CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode), Result => CLKint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (0 ps, VitalZeroDelay, FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehavior : PROCESS (Eint, CLKint, MR_ipd) -- Timing Check Variables VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Tviol_ENNeg_CLK : X01 := '0'; VARIABLE TD_ENNeg_CLK : VitalTimingDataType; VARIABLE Violation : X01 := '0'; -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; -- Functionality Results Variables VARIABLE Count8 : unsigned(3 downto 0):= (OTHERS => 'X'); VARIABLE NextCount8 : unsigned(3 downto 0):= (OTHERS => 'X'); VARIABLE Q0_zd : std_ulogic; VARIABLE Q1_zd : std_ulogic; VARIABLE Q2_zd : std_ulogic; VARIABLE LastENNeg : std_ulogic; -- No Weak Values Variables VARIABLE MR_nwv : UX01 := 'X'; VARIABLE ENNeg_nwv : UX01 := 'X'; BEGIN MR_nwv := To_UX01 (s => MR_ipd); ENNeg_nwv := To_UX01 (s => ENNeg_ipd); ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLK_posedge, HeaderMsg => InstancePath & "/eclpsl34", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalSetupHoldCheck ( TestSignal => ENNeg_ipd, TestSignalName => "ENNeg_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_ENNeg_CLK, SetupLow => tsetup_ENNeg_CLK, HoldHigh => thold_ENNeg_CLK, HoldLow => thold_ENNeg_CLK, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & "/eclpsl34", TimingData => TD_ENNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ENNeg_CLK ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_CLK OR Tviol_ENNeg_CLK; IF (MR_nwv = 'X') THEN Q0_zd := 'X'; Q1_zd := 'X'; Q2_zd := 'X'; NextCount8 := "XXXX"; Count8 := "XXXX"; ELSIF (MR_nwv = '1') THEN NextCount8 := "0111"; Count8 := "0000"; LastENNeg := '0'; Q0_zd := '0'; Q1_zd := '0'; Q2_zd := '0'; ELSIF (Violation = 'X') THEN Q0_zd := 'X'; Q1_zd := 'X'; Q2_zd := 'X'; NextCount8 := "XXXX"; Count8 := "XXXX"; --Sync. enable-- ELSIF (CLKint = '0' AND CLKint'EVENT) THEN LastENNeg := ENNeg_nwv; --Sync. clock generation-- ELSIF (CLKint = '1' AND CLKint'EVENT AND LastENNeg = '0') THEN Count8 := NextCount8; Q0_zd := Count8(0); Q1_zd := Count8(1); Q2_zd := Count8(2); --clock generation-- NextCount8 := ('0' & NextCount8(2 downto 0)) - to_unsigned(1,1); END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0int", OutTemp => Q0_zd, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1int", OutTemp => Q1_zd, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q1, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q2int, OutSignalName => "Q2int", OutTemp => Q2_zd, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q2, PathCondition => TRUE), 1 => (InputChangeTime => MR_ipd'LAST_EVENT, PathDelay => tpd_MR_Q0, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;