-------------------------------------------------------------------------------- -- File Name : eclpsl31.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V2.0 rev3 96 MAR 22 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Steele 96 SEP 18 Change trelease to trecovery -- V2.2 R. Steele 96 OCT 11 Updated timing generics -- V2.3 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.4 R. Munden 98 APR 07 Fixed compile errors found by modelsim -- V2.5 R. Munden 07 APR 09 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPSL31 -- -- Description: Single D Flip-Flop with Set and Reset -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclpsl31 IS GENERIC ( -- tipd delays: interconnect path delays tipd_S : VitalDelayType01 := VitalZeroDelay01; tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_R : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_S_Q : VitalDelayType01 := ECLUnitDelay01; tpd_R_Q : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_Q : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D_CLK : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_S_CLK : VitalDelayType := ECLUnitDelay; trecovery_R_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_S_posedge : VitalDelayType := ECLUnitDelay; tpw_R_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor S : IN std_ulogic := '0'; D : IN std_ulogic := '0'; CLK : IN std_ulogic := '0'; R : IN std_ulogic := '0'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_level0 OF eclpsl31 : ENTITY IS TRUE; END eclpsl31; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclpsl31 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL S_ipd : std_ulogic := 'X'; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL R_ipd : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (S_ipd, S, tipd_S); w_2: VitalWireDelay (D_ipd, D, tipd_D); w_3: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_4: VitalWireDelay (R_ipd, R, tipd_R); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => QNeg, a => Qint, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLK_ipd, D_ipd, S_ipd, R_ipd) -- Timing Check Variables VARIABLE Tviol_D_CLK : X01 := '0'; VARIABLE TD_D_CLK : VitalTimingDataType; VARIABLE Rviol_S_CLK : X01 := '0'; VARIABLE TD_S_CLK : VitalTimingDataType; VARIABLE Rviol_R_CLK : X01 := '0'; VARIABLE TD_R_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_S : X01 := '0'; VARIABLE PD_S : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_R : X01 := '0'; VARIABLE PD_R : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 4); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D_ipd, TestSignalName => "D_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D_CLK, SetupLow => tsetup_D_CLK, HoldHigh => thold_D_CLK, HoldLow => thold_D_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclpsl31", TimingData => TD_D_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_CLK ); VitalRecoveryRemovalCheck ( TestSignal => S_ipd, TestSignalName => "S_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", Recovery => trecovery_S_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclpsl31", TimingData => TD_S_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_S_CLK ); VitalRecoveryRemovalCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", Recovery => trecovery_R_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclpsl31", TimingData => TD_R_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_R_CLK ); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclpsl31", PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => S_ipd, TestSignalName => "S_ipd", PulseWidthHigh => tpw_S_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclpsl31", PeriodData => PD_S, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_S ); VitalPeriodPulseCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", PulseWidthHigh => tpw_R_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclpsl31", PeriodData => PD_R, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_R ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_CLK OR Pviol_CLK OR Rviol_S_CLK OR Rviol_R_CLK OR Pviol_S OR Pviol_R; VitalStateTable ( StateTable => DFFSR_tab, DataIn => (Violation, CLK_ipd, D_ipd, S_ipd, R_ipd), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Q, PathCondition => TRUE), 1 => (InputChangeTime => S_ipd'LAST_EVENT, PathDelay => tpd_S_Q, PathCondition => TRUE), 2 => (InputChangeTime => R_ipd'LAST_EVENT, PathDelay => tpd_R_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;