-------------------------------------------------------------------------------- -- File name : eclpsl29.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1999-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V1.0 M. Li 99 DEC 02 initial release -- V1.1 R. Munden 02 APR 24 Fixed Dummy VPDs -- V1.2 R. Munden 07 APR 09 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPSL29 -- -- Description: Differential data and clock D Flip-Flop with Set and Reset -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclpsl29 IS GENERIC ( -- tipd delays: interconnect path delays tipd_R : VitalDelayType01 := VitalZeroDelay01; tipd_S : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_DNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_Q : VitalDelayType01 := ECLUnitDelay01; tpd_R_Q : VitalDelayType01 := ECLUnitDelay01; tpd_S_Q : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D_CLK : VitalDelayType := ECLUnitDelay; -- trecovery values: release times trecovery_R_CLK : VitalDelayType := ECLUnitDelay; trecovery_S_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_R_posedge : VitalDelayType := ECLUnitDelay; tpw_S_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); -- 0 denotes internal pull-down resistor, 1 pull-up -- (actually clamp circuit) PORT ( CLK : IN std_ulogic := '0'; CLKNeg : IN std_ulogic := '1'; R : IN std_ulogic := '0'; S : IN std_ulogic := '0'; D : IN std_ulogic := '0'; DNeg : IN std_ulogic := '1'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U' ; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_level0 of eclpsl29 : ENTITY IS TRUE; END eclpsl29; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclpsl29 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL R_ipd : std_ulogic := 'X'; SIGNAL S_ipd : std_ulogic := 'X'; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL DNeg_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Dint : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_2: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_3: VitalWireDelay (R_ipd, R, tipd_R); w_4: VitalWireDelay (S_ipd, S, tipd_S); w_5: VitalWireDelay (D_ipd, D, tipd_D); w_6: VitalWireDelay (DNeg_ipd, DNeg, tipd_DNeg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => QNeg, a => Qint, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- D inputs Process ---------------------------------------------------------------------------- Dinputs : PROCESS (D_ipd, DNeg_ipd) -- Functionality Results Variables VARIABLE Dint_zd : X01; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Dint_zd := ECL_s_or_d_inputs_tab (D_ipd, DNeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => Dint, OutSignalName => "Dint", OutTemp => Dint_zd, GlitchData => D_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (CLK_ipd, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab(CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode), Result => CLKint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, Dint, S_ipd, R_ipd) -- Timing Check Variables VARIABLE Tviol_D_CLKint : X01 := '0'; VARIABLE TD_D_CLKint : VitalTimingDataType; VARIABLE Rviol_R_CLKint : X01 := '0'; VARIABLE TD_R_CLKint : VitalTimingDataType; VARIABLE Sviol_S_CLKint : X01 := '0'; VARIABLE TD_S_CLKint : VitalTimingDataType; VARIABLE Pviol_CLKint : X01 := '0'; VARIABLE PD_CLKint : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_R : X01 := '0'; VARIABLE PD_R : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_S : X01 := '0'; VARIABLE PD_S : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 4); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => Dint, TestSignalName => "Dint", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D_CLK, SetupLow => tsetup_D_CLK, HoldHigh => thold_D_CLK, HoldLow => thold_D_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclpsl29", TimingData => TD_D_CLKint, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_CLKint ); VitalRecoveryRemovalCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", RefSignal => CLKint, RefSignalName => "CLKint", Recovery => trecovery_R_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclpsl29", TimingData => TD_R_CLKint, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_R_CLKint ); VitalRecoveryRemovalCheck ( TestSignal => S_ipd, TestSignalName => "S_ipd", RefSignal => CLKint, RefSignalName => "CLKint", Recovery => trecovery_S_CLK, ActiveLow => FALSE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/eclpsl29", TimingData => TD_S_CLKint, XOn => XOn, MsgOn => MsgOn, Violation => Sviol_S_CLKint ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", PulseWidthHigh => tpw_CLK_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclpsl29", PeriodData => PD_CLKint, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKint ); VitalPeriodPulseCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", PulseWidthHigh => tpw_R_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclpsl29", PeriodData => PD_R, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_R ); VitalPeriodPulseCheck ( TestSignal => S_ipd, TestSignalName => "S_ipd", PulseWidthHigh => tpw_S_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/eclpsl29", PeriodData => PD_S, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_S ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_CLKint OR Pviol_CLKint OR Rviol_R_CLKint OR Pviol_R OR Sviol_S_CLKint OR Pviol_S; VitalStateTable ( StateTable => DFFSR_tab, DataIn => (Violation, CLKint, Dint, S_ipd, R_ipd), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q, PathCondition => TRUE), 1 => (InputChangeTime => R_ipd'LAST_EVENT, PathDelay => tpd_R_Q, PathCondition => TRUE), 2 => (InputChangeTime => S_ipd'LAST_EVENT, PathDelay => tpd_S_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;