-------------------------------------------------------------------------------- -- File name: eclpsl14.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2000-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Steele 00 NOV 06 Conformed to style guide -- V1.1 R. Munden 02 APR 25 Fixed Dummy VPD -- V1.2 R. Munden 07 MAR 27 Made resultmap locally static ------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPSL14 -- -- Description: 1 to 5 clock distributor with enable and select mux -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclpsl14 IS GENERIC ( -- tipd delays: interconnect path delays tipd_ENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SCLK : VitalDelayType01 := VitalZeroDelay01; tipd_SEL : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_Q0 : VitalDelayType01 := ECLUnitDelay01; tpd_SCLK_Q0 : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_ENNeg_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_ENNeg_CLK : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor ENNeg : IN std_ulogic := '0'; SCLK : IN std_ulogic := '0'; SEL : IN std_ulogic := '0'; CLK : IN std_ulogic := '0'; CLKNeg : IN std_ulogic := '0'; Q0 : OUT std_ulogic := 'U'; Q0Neg : OUT std_ulogic := 'U'; Q1 : OUT std_ulogic := 'U'; Q1Neg : OUT std_ulogic := 'U'; Q2 : OUT std_ulogic := 'U'; Q2Neg : OUT std_ulogic := 'U'; Q3 : OUT std_ulogic := 'U'; Q3Neg : OUT std_ulogic := 'U'; Q4 : OUT std_ulogic := 'U'; Q4Neg : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF eclpsl14 : ENTITY IS TRUE; END eclpsl14; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclpsl14 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL ENNeg_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL SCLK_ipd : std_ulogic := 'X'; SIGNAL SEL_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Eint : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (ENNeg_ipd, ENNeg, tipd_ENNeg); w_2: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_3: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_4: VitalWireDelay (SEL_ipd, SEL, tipd_SEL); w_5: VitalWireDelay (SCLK_ipd, SCLK, tipd_SCLK); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VITALBUF (q => Q0, a => Qint, ResultMap => ('U','X','Z','1')); a_2: VITALBUF (q => Q1, a => Qint, ResultMap => ('U','X','Z','1')); a_3: VITALBUF (q => Q2, a => Qint, ResultMap => ('U','X','Z','1')); a_4: VITALBUF (q => Q3, a => Qint, ResultMap => ('U','X','Z','1')); a_5: VITALBUF (q => Q4, a => Qint, ResultMap => ('U','X','Z','1')); a_6: VITALINV (q => Q0Neg, a => Qint, ResultMap => ('U','X','Z','1')); a_7: VITALINV (q => Q1Neg, a => Qint, ResultMap => ('U','X','Z','1')); a_8: VITALINV (q => Q2Neg, a => Qint, ResultMap => ('U','X','Z','1')); a_9: VITALINV (q => Q3Neg, a => Qint, ResultMap => ('U','X','Z','1')); a_10: VITALINV (q => Q4Neg, a => Qint, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- ECL CLock Process with mux ---------------------------------------------------------------------------- ECLClock_mux : PROCESS (CLK_ipd, CLKNeg_ipd, SCLK_ipd, SEL_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLK_var : std_ulogic; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab(CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode), Result => CLK_var, PreviousDataIn => PrevData ); CLKint_zd := VitalMUX2 ( data0 => CLK_var, data1 => SCLK_ipd, dselect => SEL_ipd ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Enable Latch Process ---------------------------------------------------------------------------- Enable_lat : PROCESS (ENNeg_ipd, CLKint) -- Timing Check Variables VARIABLE Tviol_E_CLK : X01 := '0'; VARIABLE TD_E_CLK : VitalTimingDataType; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Eint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 TO 2); -- Output Glitch Detection Variables VARIABLE ENeg_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => ENNeg_ipd, TestSignalName => "ENNeg_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_ENNeg_CLK, SetupLow => tsetup_ENNeg_CLK, HoldHigh => thold_ENNeg_CLK, HoldLow => thold_ENNeg_CLK, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath, TimingData => TD_E_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_E_CLK ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_E_CLK; VitalStateTable ( StateTable => DFFNQN_tab, DataIn => (Violation, CLKint, ENNeg_ipd), Result => Eint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => Eint, OutSignalName => "Eint", OutTemp => Eint_zd, GlitchData => ENeg_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => ENNeg_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehavior : PROCESS (Eint, CLKint, SEL_ipd) -- Functionality Results Variables VARIABLE Qint_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE Qint_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Qint_zd := VitalAND2 (a => Eint, b => CLKint); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Qint_zd, GlitchData => Qint_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => (SEL_ipd = '0' OR SEL_ipd = 'L')), 1 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_SCLK_Q0, PathCondition => (SEL_ipd /= '0' OR SEL_ipd /= 'L')) ) ); END PROCESS; END vhdl_behavioral;