-------------------------------------------------------------------------------- -- File Name : eclpsl13.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- version | author | mod date | changes made -- V2.0 rev3 96 MAR 20 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Munden 96 MAY 19 Changed tpd's for VITAL/SDF compliance -- V2.2 rev3 96 JUN 11 Fixed VPD in ECL Clock Process -- V2.3 R. Steele 96 OCT 11 Updated timing generics -- V2.4 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.5 R. Munden 07 MAR 18 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: ECLPS -- Technology: ECL -- Part: ECLPSL13 -- -- Description: Dual 1:3 Fanout Buffer -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY eclpsl13 IS GENERIC ( -- tipd delays: interconnect path delays tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_Y0 : VitalDelayType01 := ECLUnitDelay01; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor, 1 pull-up -- (actually clamp circuit) CLK : IN std_ulogic := '0'; CLKNeg : IN std_ulogic := '1'; Y2 : OUT std_ulogic := 'U'; Y1 : OUT std_ulogic := 'U'; Y0 : OUT std_ulogic := 'U'; Y2Neg : OUT std_ulogic := 'U'; Y1Neg : OUT std_ulogic := 'U'; Y0Neg : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_level0 OF eclpsl13 : ENTITY IS TRUE; END eclpsl13; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF eclpsl13 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_2: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Prodedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Y0, a => CLKint, ResultMap => ('U','X','Z','1')); a_2: VitalBUF (q => Y1, a => CLKint, ResultMap => ('U','X','Z','1')); a_3: VitalBUF (q => Y2, a => CLKint, ResultMap => ('U','X','Z','1')); a_4: VitalINV (q => Y0Neg, a => CLKint, ResultMap => ('U','X','Z','1')); a_5: VitalINV (q => Y1Neg, a => CLKint, ResultMap => ('U','X','Z','1')); a_6: VitalINV (q => Y2Neg, a => CLKint, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- ECL Clock Process with delay ---------------------------------------------------------------------------- ECLClock : Process (CLK_ipd, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab (CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode), Result => CLKint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_Y0, PathCondition => TRUE), 1 => (InputChangeTime => CLKNeg_ipd'LAST_EVENT, PathDelay => tpd_CLK_Y0, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;