--------------------------------------------------------------------------------
--  File name : eclpsl12.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version | author | mod date | changes made
--    V2.0    rev3     96 MAR 22  Conformed to style guide,
--                                New ecl_utils package with more constants
--    V2.1 R. Munden   96 MAY 19  Changed tpd's for VITAL compliance
--    V2.2 R. Munden   07 MAR 18  Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library:       	ECLPS
--  Technology:    	ECL
--  Part:          	ECLPSL12
--
--  Description:   	2-input OR gate with complementary NOR output
--					(Billed as low-impedance driver)
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclpsl12 IS
    GENERIC (
    	-- tipd delays: interconnect path delays
        tipd_A          	: VitalDelayType01 := VitalZeroDelay01;
        tipd_B          	: VitalDelayType01 := VitalZeroDelay01;
    	-- tpd delays: propagation delays
        tpd_A_QA         	: VitalDelayType01 := ECLUnitDelay01;
        tpd_B_QA         	: VitalDelayType01 := ECLUnitDelay01;
    	-- generic control parameters
        InstancePath    	: STRING := DefaultECLInstancePath;
        -- For FMF SDF technology file usage
        TimingModel     	: STRING := DefaultECLTimingModel
	);
    port (    
        -- 0 denotes internal pull-down resistor
        A               	: IN  std_ulogic := '0';
        B               	: IN  std_ulogic := '0';
        QA              	: OUT std_ulogic := 'U';
        QANeg           	: OUT std_ulogic := 'U';
        QB              	: OUT std_ulogic := 'U';
        QBNeg           	: OUT std_ulogic := 'U' 
	);
    ATTRIBUTE VITAL_level0 OF eclpsl12 : ENTITY IS TRUE;
END eclpsl12;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclpsl12 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'X';
    SIGNAL B_ipd            : std_ulogic := 'X';
	SIGNAL Qint				: std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (A_ipd, A, tipd_A);
        w_2: VitalWireDelay (B_ipd, B, tipd_B);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalOR2 (
			q		=> Qint,
			a		=> A_ipd,
			b		=> B_ipd,
            tpd_a_q => tpd_A_QA,
            tpd_b_q => tpd_B_QA
		 );

    a_2: VitalBUF (q => QA, a => Qint, ResultMap => ('U','X','Z','1'));
    a_3: VitalBUF (q => QB, a => Qint, ResultMap => ('U','X','Z','1'));

    a_4: VitalINV (q => QANeg, a => Qint, ResultMap => ('U','X','Z','1'));
    a_5: VitalINV (q => QBNeg, a => Qint, ResultMap => ('U','X','Z','1'));

END vhdl_behavioral;