--------------------------------------------------------------------------------
--   File name : eclpsl11.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version | author | mod date | changes made
--    V2.0    rev3     96 MAR 22  Conformed to style guide,
--                                New ecl_utils package with more constants
--    V2.1 R. Munden   96 MAY 19  Changed tpd's for VITAL compliance
--    V2.2    rev3     96 JUN 11  Fixed VPD in ECL Clock Process
--    V2.3  R. Munden  97 MAR 01  Changed XGenerationOn to XOn, added MsgOn, and
--                                updated TimingChecks & PathDelays
--    V2.4  R. Munden  07 MAR 13  Made resultmap locally static
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library:       	ECLPS
--  Technology:    	ECL
--  Part:          	ECLPSL11
--
--  Description:   	1:2 differential fanout buffer
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclpsl11 IS
    GENERIC (
    	-- tipd delays: interconnect path delays
        tipd_A          	: VitalDelayType01 := VitalZeroDelay01;
        tipd_ANeg       	: VitalDelayType01 := VitalZeroDelay01;
    	-- tpd delays: propagation delays
        tpd_A_Y1         	: VitalDelayType01 := ECLUnitDelay01;
    	-- generic control parameters
        InstancePath    	: STRING := DefaultECLInstancePath;
        MsgOn               : BOOLEAN := DefaultECLMsgOn;
        XOn             	: Boolean := DefaultECLXOn;
		-- For FMF SDF technology file usage
        TimingModel     	: STRING := DefaultECLTimingModel
	);
    port (    
        -- 0 denotes internal pull-down resistor, 1 pull-up
		-- (actually clamp circuit)
        A               	: IN  std_ulogic := '0';
        ANeg            	: IN  std_ulogic := '1';
        Y1              	: OUT std_ulogic := 'U';
        Y1Neg           	: OUT std_ulogic := 'U'; 
        Y2              	: OUT std_ulogic := 'U';
        Y2Neg           	: OUT std_ulogic := 'U' 
	);
    ATTRIBUTE VITAL_level0 OF eclpsl11 : ENTITY IS TRUE;
END eclpsl11;

--------------------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclpsl11 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd            : std_ulogic := 'X';
    SIGNAL ANeg_ipd         : std_ulogic := 'X';
	SIGNAL Aint				: std_ulogic := 'X';
 
BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
 
         w_1: VitalWireDelay (A_ipd, A, tipd_A);
         w_2: VitalWireDelay (ANeg_ipd, ANeg, tipd_ANeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
	a_1: VitalBUF (q => Y1, a => Aint, ResultMap => ('U','X','Z','1'));
	a_2: VitalBUF (q => Y2, a => Aint, ResultMap => ('U','X','Z','1'));
	a_3: VitalINV (q => Y1Neg, a => Aint, ResultMap => ('U','X','Z','1'));
	a_4: VitalINV (q => Y2Neg, a => Aint, ResultMap => ('U','X','Z','1'));

    ----------------------------------------------------------------------------
    -- ECL Clock Process with delay
    ----------------------------------------------------------------------------
    ECLClock : PROCESS (A_ipd, ANeg_ipd)

        -- Functionality Results Variables
        VARIABLE Mode           : X01;
        VARIABLE Aint_zd      	: std_ulogic;
        VARIABLE PrevData       : std_logic_vector(0 to 2);
 
        -- Output Glitch Detection Variables
        VARIABLE A_GlitchData   : VitalGlitchDataType;
 
    BEGIN
 
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Mode := ECL_diff_mode_tab (A_ipd, ANeg_ipd);

        VitalStateTable (
            StateTable      => ECL_clk_tab,
            DataIn          => (A_ipd, ANeg_ipd, Mode),
            Result          => Aint_zd,
            PreviousDataIn  => PrevData
		);
 
        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => Aint,
            OutSignalName   => "Aint",
            OutTemp         => Aint_zd,
            GlitchData      => A_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => tpd_A_Y1,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => ANeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_A_Y1,
                      PathCondition     => TRUE)
			)
		);
 
    END PROCESS;

END vhdl_behavioral;