--------------------------------------------------------------------------------
--  File name : eclpsl08.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1999, 2002 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version | author | mod date | changes made
--    V1.0     mkl      99 NOV 12  Conformed to style guide
--    V1.1   R. Munden  02 APR 25   Fixed Dummy VPD
--------------------------------------------------------------------------------
--  PART DESCRIPTION :
--
--  Library:               ECLPS
--  Technology:            ECL
--  Part:                  ECLPSL08
--
--  Description:           Differential 2-input XOR/XNOR gate 
--
--------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_primitives.all;
                USE IEEE.VITAL_timing.all;
LIBRARY FMF;    USE FMF.ecl_utils.all;

--------------------------------------------------------------------------------
--  ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY eclpsl08 IS
    GENERIC (
            -- tipd delays: interconnect path delays
        tipd_D0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D0Neg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1Neg              : VitalDelayType01 := VitalZeroDelay01;
            -- tpd delays: propagation delays 
        tpd_D0_Q                : VitalDelayType01 := ECLUnitDelay01;
            -- generic control parameters
        InstancePath        : STRING := DefaultECLInstancePath;
        MsgOn               : BOOLEAN := DefaultECLMsgOn;
        XOn                 : BOOLEAN := DefaultECLXOn;
            -- For FMF SDF technology file usage
        TimingModel             : STRING := DefaultECLTimingModel
        );
    PORT (    
        D0                      : IN  std_ulogic := '1';
        D0Neg                   : IN  std_ulogic := '0';
        D1                      : IN  std_ulogic := '1';
        D1Neg                   : IN  std_ulogic := '0';
        Q                       : OUT std_ulogic := 'U';
        QNeg                    : OUT std_ulogic := 'U' 
        );

    ATTRIBUTE VITAL_level0 OF eclpsl08 : ENTITY IS TRUE;
END eclpsl08;

------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF eclpsl08 IS
    ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL D0_ipd            : std_ulogic := 'X';
    SIGNAL D0neg_ipd         : std_ulogic := 'X';
    SIGNAL D1_ipd            : std_ulogic := 'X';
    SIGNAL D1neg_ipd         : std_ulogic := 'X';
    SIGNAL D0int             : std_ulogic := 'X';
    SIGNAL D1int             : std_ulogic := 'X';

BEGIN

    ---------------------------------------------------------------
    -- Wire Delays
    ---------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
 
         w_1: VitalWireDelay (D0_ipd, D0, tipd_D0);
         w_2: VitalWireDelay (D0Neg_ipd, D0Neg, tipd_D0Neg);
         w_3: VitalWireDelay (D1_ipd, D1, tipd_D1);
         w_4: VitalWireDelay (D1Neg_ipd, D1Neg, tipd_D1Neg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- D0 inputs Process
    ----------------------------------------------------------------------------
    D0_inputs : PROCESS (D0_ipd, D0Neg_ipd)

        -- Functionality Results Variables
        VARIABLE D0int_zd        : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE D0_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        D0int_zd := ECL_s_or_d_inputs_tab (D0_ipd, D0Neg_ipd);

        ------------------------------------------------------------------------
        -- (Dummy) Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay (
            OutSignal       => D0int,
            OutSignalName   => "D0int",
            OutTemp         => D0int_zd,
            GlitchData      => D0_GlitchData,
            Paths           => (
                0 => (InputChangeTime   => D0_ipd'LAST_EVENT,
                      PathDelay         => VitalZeroDelay,
                      PathCondition     => FALSE))
                );

    END PROCESS;
    ----------------------------------------------------------------------------
    -- D1 inputs Process
    ----------------------------------------------------------------------------
    D1_inputs : PROCESS (D1_ipd, D1Neg_ipd)

        -- Functionality Results Variables
        VARIABLE D1int_zd        : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE D1_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        D1int_zd := ECL_s_or_d_inputs_tab (D1_ipd, D1Neg_ipd);

        ------------------------------------------------------------------------
        -- (Dummy) Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay (
            OutSignal       => D1int,
            OutSignalName   => "D1int",
            OutTemp         => D1int_zd,
            GlitchData      => D1_GlitchData,
            Paths           => (
                0 => (InputChangeTime   => D1_ipd'LAST_EVENT,
                      PathDelay         => VitalZeroDelay,
                      PathCondition     => FALSE))
                );

    END PROCESS;
    ----------------------------------------------------------------------------
    -- XOR/XNOR Process
    ----------------------------------------------------------------------------
    XorXnor : PROCESS (D0int, D1int)

        -- Functionality Results Variables
        VARIABLE Q_zd           : std_ulogic;
        VARIABLE QNeg_zd        : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE Q_GlitchData      : VitalGlitchDataType;
        VARIABLE QNeg_GlitchData   : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Q_zd := VitalXOR2(a => D0int, b => D1int,
                          ResultMap => ECL_wired_or_rmap);
        QNeg_zd := VitalXNOR2(a => D0int, b => D1int,
                          ResultMap => ECL_wired_or_rmap);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => Q,
            OutSignalName   => "Q",
            OutTemp         => Q_zd,
            GlitchData      => Q_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => D0int'LAST_EVENT,
                      PathDelay         => tpd_D0_Q,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => D1int'LAST_EVENT,
                      PathDelay         => tpd_D0_Q,
                      PathCondition     => TRUE)
            )
        );

        VitalPathDelay01 (
            OutSignal       => QNeg,
            OutSignalName   => "QNeg",
            OutTemp         => QNeg_zd,
            GlitchData      => QNeg_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => D0int'LAST_EVENT,
                      PathDelay         => tpd_D0_Q,
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => D1int'LAST_EVENT,
                      PathDelay         => tpd_D0_Q,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS;

END vhdl_behavioral;